1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 #ifndef __SOC_QUALCOMM_IPQ806X_IOMAP_H_ 4 #define __SOC_QUALCOMM_IPQ806X_IOMAP_H_ 5 6 #include <device/mmio.h> 7 #include <soc/cdp.h> 8 9 /* Typecast to allow integers being passed as address 10 This needs to be included because vendor code is not compliant with our 11 macros for read/write. Hence, special macros for readl_i and writel_i are 12 included to do this in one place for all occurrences in vendor code 13 */ 14 #define readl_i(a) read32((const void *)(a)) 15 #define writel_i(v,a) write32((void *)a, v) 16 #define clrsetbits32_i(addr, clear, set) \ 17 clrsetbits32(((void *)(addr)), (clear), (set)) 18 19 #define MSM_CLK_CTL_BASE ((void *)0x00900000) 20 21 #define MSM_TMR_BASE ((void *)0x0200A000) 22 #define MSM_GPT_BASE (MSM_TMR_BASE + 0x04) 23 #define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) 24 25 #define GPT_REG(off) (MSM_GPT_BASE + (off)) 26 #define DGT_REG(off) (MSM_DGT_BASE + (off)) 27 28 #define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040) 29 #define APCS_WDT0_RST (MSM_TMR_BASE + 0x0038) 30 #define APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C) 31 #define APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C) 32 33 #define APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820) 34 35 #define GPT_MATCH_VAL GPT_REG(0x0000) 36 #define GPT_COUNT_VAL GPT_REG(0x0004) 37 #define GPT_ENABLE GPT_REG(0x0008) 38 #define GPT_CLEAR GPT_REG(0x000C) 39 40 #define GPT1_MATCH_VAL GPT_REG(0x00010) 41 #define GPT1_COUNT_VAL GPT_REG(0x00014) 42 #define GPT1_ENABLE GPT_REG(0x00018) 43 #define GPT1_CLEAR GPT_REG(0x0001C) 44 45 #define DGT_MATCH_VAL DGT_REG(0x0000) 46 #define DGT_COUNT_VAL DGT_REG(0x0004) 47 #define DGT_ENABLE DGT_REG(0x0008) 48 #define DGT_CLEAR DGT_REG(0x000C) 49 #define DGT_CLK_CTL DGT_REG(0x0010) 50 51 /* RPM interface constants */ 52 #define RPM_INT ((void *)0x63020) 53 #define RPM_INT_ACK ((void *)0x63060) 54 #define RPM_SIGNAL_COOKIE ((void *)0x47C20) 55 #define RPM_SIGNAL_ENTRY ((void *)0x47C24) 56 #define RPM_FW_MAGIC_NUM 0x4D505242 57 58 #define TLMM_BASE_ADDR ((void *)0x00800000) 59 #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10) 60 #define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4) 61 62 /* Yes, this is not a typo... host2 is actually mapped before host1. */ 63 #define USB_HOST2_XHCI_BASE 0x10000000 64 #define USB_HOST2_DWC3_BASE 0x1000C100 65 #define USB_HOST2_PHY_BASE 0x100F8800 66 #define USB_HOST1_XHCI_BASE 0x11000000 67 #define USB_HOST1_DWC3_BASE 0x1100C100 68 #define USB_HOST1_PHY_BASE 0x110F8800 69 70 #define GSBI_4 4 71 #define UART1_DM_BASE 0x12450000 72 #define UART_GSBI1_BASE 0x12440000 73 #define UART2_DM_BASE 0x12490000 74 #define UART_GSBI2_BASE 0x12480000 75 #define UART4_DM_BASE 0x16340000 76 #define UART_GSBI4_BASE 0x16300000 77 78 #define UART2_DM_BASE 0x12490000 79 #define UART_GSBI2_BASE 0x12480000 80 81 #define GSBI1_BASE ((void *)0x12440000) 82 #define GSBI2_BASE ((void *)0x12480000) 83 #define GSBI3_BASE ((void *)0x16200000) 84 #define GSBI4_BASE ((void *)0x16300000) 85 #define GSBI5_BASE ((void *)0x1A200000) 86 #define GSBI6_BASE ((void *)0x16500000) 87 #define GSBI7_BASE ((void *)0x16600000) 88 89 #define GSBI1_CTL_REG (GSBI1_BASE + (0x0)) 90 #define GSBI2_CTL_REG (GSBI2_BASE + (0x0)) 91 #define GSBI3_CTL_REG (GSBI3_BASE + (0x0)) 92 #define GSBI4_CTL_REG (GSBI4_BASE + (0x0)) 93 #define GSBI5_CTL_REG (GSBI5_BASE + (0x0)) 94 #define GSBI6_CTL_REG (GSBI6_BASE + (0x0)) 95 #define GSBI7_CTL_REG (GSBI7_BASE + (0x0)) 96 97 #define GSBI_QUP1_BASE (GSBI1_BASE + 0x20000) 98 #define GSBI_QUP2_BASE (GSBI2_BASE + 0x20000) 99 #define GSBI_QUP3_BASE (GSBI3_BASE + 0x80000) 100 #define GSBI_QUP4_BASE (GSBI4_BASE + 0x80000) 101 #define GSBI_QUP5_BASE (GSBI5_BASE + 0x80000) 102 #define GSBI_QUP6_BASE (GSBI6_BASE + 0x80000) 103 #define GSBI_QUP7_BASE (GSBI7_BASE + 0x80000) 104 105 #define GSBI_CTL_PROTO_I2C 2 106 #define GSBI_CTL_PROTO_CODE_SFT 4 107 #define GSBI_CTL_PROTO_CODE_MSK 0x7 108 #define GSBI_HCLK_CTL_GATE_ENA 6 109 #define GSBI_HCLK_CTL_BRANCH_ENA 4 110 #define GSBI_QUP_APPS_M_SHFT 16 111 #define GSBI_QUP_APPS_M_MASK 0xFF 112 #define GSBI_QUP_APPS_D_SHFT 0 113 #define GSBI_QUP_APPS_D_MASK 0xFF 114 #define GSBI_QUP_APPS_N_SHFT 16 115 #define GSBI_QUP_APPS_N_MASK 0xFF 116 #define GSBI_QUP_APPS_ROOT_ENA_SFT 11 117 #define GSBI_QUP_APPS_BRANCH_ENA_SFT 9 118 #define GSBI_QUP_APPS_MNCTR_EN_SFT 8 119 #define GSBI_QUP_APPS_MNCTR_MODE_MSK 0x3 120 #define GSBI_QUP_APPS_MNCTR_MODE_SFT 5 121 #define GSBI_QUP_APPS_PRE_DIV_MSK 0x3 122 #define GSBI_QUP_APPS_PRE_DIV_SFT 3 123 #define GSBI_QUP_APPS_SRC_SEL_MSK 0x7 124 125 #define GSBI_QUP_APSS_MD_REG(gsbi_n) ((MSM_CLK_CTL_BASE + 0x29c8) + \ 126 (32*(gsbi_n-1))) 127 #define GSBI_QUP_APSS_NS_REG(gsbi_n) ((MSM_CLK_CTL_BASE + 0x29cc) + \ 128 (32*(gsbi_n-1))) 129 #define GSBI_HCLK_CTL(n) ((MSM_CLK_CTL_BASE + 0x29C0) + \ 130 (32*(n-1))) 131 #endif // __SOC_QUALCOMM_IPQ806X_IOMAP_H_ 132