1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* 4 * Register definitions for the IPQ GSBI Controller 5 */ 6 7 #ifndef _IPQ806X_SPI_H_ 8 #define _IPQ806X_SPI_H_ 9 10 #include <spi-generic.h> 11 #include <soc/iomap.h> 12 13 #define QUP5_BASE ((uint32_t)GSBI_QUP5_BASE) 14 #define QUP6_BASE ((uint32_t)GSBI_QUP6_BASE) 15 #define QUP7_BASE ((uint32_t)GSBI_QUP7_BASE) 16 17 #define GSBI5_QUP5_REG_BASE (QUP5_BASE + 0x00000000) 18 #define GSBI6_QUP6_REG_BASE (QUP6_BASE + 0x00000000) 19 #define GSBI7_QUP7_REG_BASE (QUP7_BASE + 0x00000000) 20 21 #define GSBI5_REG_BASE ((uint32_t)(GSBI5_BASE + 0x00000000)) 22 #define GSBI6_REG_BASE ((uint32_t)(GSBI6_BASE + 0x00000000)) 23 #define GSBI7_REG_BASE ((uint32_t)(GSBI7_BASE + 0x00000000)) 24 25 #define BOOT_SPI_PORT5_BASE QUP5_BASE 26 #define BOOT_SPI_PORT6_BASE QUP6_BASE 27 #define BOOT_SPI_PORT7_BASE QUP7_BASE 28 29 #define GSBI5_SPI_CONFIG_REG (GSBI5_QUP5_REG_BASE + 0x00000300) 30 #define GSBI6_SPI_CONFIG_REG (GSBI6_QUP6_REG_BASE + 0x00000300) 31 #define GSBI7_SPI_CONFIG_REG (GSBI7_QUP7_REG_BASE + 0x00000300) 32 33 #define GSBI5_SPI_IO_CONTROL_REG (GSBI5_QUP5_REG_BASE + 0x00000304) 34 #define GSBI6_SPI_IO_CONTROL_REG (GSBI6_QUP6_REG_BASE + 0x00000304) 35 #define GSBI7_SPI_IO_CONTROL_REG (GSBI7_QUP7_REG_BASE + 0x00000304) 36 37 #define GSBI5_SPI_ERROR_FLAGS_REG (GSBI5_QUP5_REG_BASE + 0x00000308) 38 #define GSBI6_SPI_ERROR_FLAGS_REG (GSBI6_QUP6_REG_BASE + 0x00000308) 39 #define GSBI7_SPI_ERROR_FLAGS_REG (GSBI7_QUP7_REG_BASE + 0x00000308) 40 41 #define GSBI5_SPI_ERROR_FLAGS_EN_REG (GSBI5_QUP5_REG_BASE + 0x0000030c) 42 #define GSBI6_SPI_ERROR_FLAGS_EN_REG (GSBI6_QUP6_REG_BASE + 0x0000030c) 43 #define GSBI7_SPI_ERROR_FLAGS_EN_REG (GSBI7_QUP7_REG_BASE + 0x0000030c) 44 45 #define GSBI5_GSBI_CTRL_REG_REG (GSBI5_REG_BASE + 0x00000000) 46 #define GSBI6_GSBI_CTRL_REG_REG (GSBI6_REG_BASE + 0x00000000) 47 #define GSBI7_GSBI_CTRL_REG_REG (GSBI7_REG_BASE + 0x00000000) 48 49 #define GSBI5_QUP_CONFIG_REG (GSBI5_QUP5_REG_BASE + 0x00000000) 50 #define GSBI6_QUP_CONFIG_REG (GSBI6_QUP6_REG_BASE + 0x00000000) 51 #define GSBI7_QUP_CONFIG_REG (GSBI7_QUP7_REG_BASE + 0x00000000) 52 53 #define GSBI5_QUP_ERROR_FLAGS_REG (GSBI5_QUP5_REG_BASE + 0x0000001c) 54 #define GSBI6_QUP_ERROR_FLAGS_REG (GSBI6_QUP6_REG_BASE + 0x0000001c) 55 #define GSBI7_QUP_ERROR_FLAGS_REG (GSBI7_QUP7_REG_BASE + 0x0000001c) 56 57 #define GSBI5_QUP_ERROR_FLAGS_EN_REG (GSBI5_QUP5_REG_BASE + 0x00000020) 58 #define GSBI6_QUP_ERROR_FLAGS_EN_REG (GSBI6_QUP6_REG_BASE + 0x00000020) 59 #define GSBI7_QUP_ERROR_FLAGS_EN_REG (GSBI7_QUP7_REG_BASE + 0x00000020) 60 61 #define GSBI5_QUP_OPERATIONAL_REG (GSBI5_QUP5_REG_BASE + 0x00000018) 62 #define GSBI6_QUP_OPERATIONAL_REG (GSBI6_QUP6_REG_BASE + 0x00000018) 63 #define GSBI7_QUP_OPERATIONAL_REG (GSBI7_QUP7_REG_BASE + 0x00000018) 64 65 #define GSBI5_QUP_IO_MODES_REG (GSBI5_QUP5_REG_BASE + 0x00000008) 66 #define GSBI6_QUP_IO_MODES_REG (GSBI6_QUP6_REG_BASE + 0x00000008) 67 #define GSBI7_QUP_IO_MODES_REG (GSBI7_QUP7_REG_BASE + 0x00000008) 68 69 #define GSBI5_QUP_STATE_REG (GSBI5_QUP5_REG_BASE + 0x00000004) 70 #define GSBI6_QUP_STATE_REG (GSBI6_QUP6_REG_BASE + 0x00000004) 71 #define GSBI7_QUP_STATE_REG (GSBI7_QUP7_REG_BASE + 0x00000004) 72 73 #define GSBI5_QUP_OUT_FIFO_WORD_CNT_REG (GSBI5_QUP5_REG_BASE + 0x0000010c) 74 #define GSBI6_QUP_OUT_FIFO_WORD_CNT_REG (GSBI6_QUP6_REG_BASE + 0x0000010c) 75 #define GSBI7_QUP_OUT_FIFO_WORD_CNT_REG (GSBI7_QUP7_REG_BASE + 0x0000010c) 76 77 #define GSBI5_QUP_IN_FIFO_WORD_CNT_REG (GSBI5_QUP5_REG_BASE + 0x00000214) 78 #define GSBI6_QUP_IN_FIFO_WORD_CNT_REG (GSBI6_QUP6_REG_BASE + 0x00000214) 79 #define GSBI7_QUP_IN_FIFO_WORD_CNT_REG (GSBI7_QUP7_REG_BASE + 0x00000214) 80 81 #define GSBI5_QUP_INPUT_FIFOc_REG(c) \ 82 (GSBI5_QUP5_REG_BASE + 0x00000218 + 4 * (c)) 83 #define GSBI6_QUP_INPUT_FIFOc_REG(c) \ 84 (GSBI6_QUP6_REG_BASE + 0x00000218 + 4 * (c)) 85 #define GSBI7_QUP_INPUT_FIFOc_REG(c) \ 86 (GSBI7_QUP7_REG_BASE + 0x00000218 + 4 * (c)) 87 88 #define GSBI5_QUP_OUTPUT_FIFOc_REG(c) \ 89 (GSBI5_QUP5_REG_BASE + 0x00000110 + 4 * (c)) 90 #define GSBI6_QUP_OUTPUT_FIFOc_REG(c) \ 91 (GSBI6_QUP6_REG_BASE + 0x00000110 + 4 * (c)) 92 #define GSBI7_QUP_OUTPUT_FIFOc_REG(c) \ 93 (GSBI7_QUP7_REG_BASE + 0x00000110 + 4 * (c)) 94 95 #define GSBI5_QUP_MX_INPUT_COUNT_REG (GSBI5_QUP5_REG_BASE + 0x00000200) 96 #define GSBI6_QUP_MX_INPUT_COUNT_REG (GSBI6_QUP6_REG_BASE + 0x00000200) 97 #define GSBI7_QUP_MX_INPUT_COUNT_REG (GSBI7_QUP7_REG_BASE + 0x00000200) 98 99 #define GSBI5_QUP_MX_OUTPUT_COUNT_REG (GSBI5_QUP5_REG_BASE + 0x00000100) 100 #define GSBI6_QUP_MX_OUTPUT_COUNT_REG (GSBI6_QUP6_REG_BASE + 0x00000100) 101 #define GSBI7_QUP_MX_OUTPUT_COUNT_REG (GSBI7_QUP7_REG_BASE + 0x00000100) 102 103 #define GSBI5_QUP_SW_RESET_REG (GSBI5_QUP5_REG_BASE + 0x0000000c) 104 #define GSBI6_QUP_SW_RESET_REG (GSBI6_QUP6_REG_BASE + 0x0000000c) 105 #define GSBI7_QUP_SW_RESET_REG (GSBI7_QUP7_REG_BASE + 0x0000000c) 106 107 #define CLK_CTL_REG_BASE 0x00900000 108 #define GSBIn_RESET_REG(n) \ 109 (CLK_CTL_REG_BASE + 0x000029dc + 32 * ((n)-1)) 110 111 #define SFAB_AHB_S3_FCLK_CTL_REG \ 112 (CLK_CTL_REG_BASE + 0x0000216c) 113 #define CFPB_CLK_NS_REG \ 114 (CLK_CTL_REG_BASE + 0x0000264c) 115 #define SFAB_CFPB_S_HCLK_CTL_REG \ 116 (CLK_CTL_REG_BASE + 0x000026c0) 117 #define CFPB_SPLITTER_HCLK_CTL_REG \ 118 (CLK_CTL_REG_BASE + 0x000026e0) 119 #define CFPB0_HCLK_CTL_REG \ 120 (CLK_CTL_REG_BASE + 0x00002650) 121 #define CFPB2_HCLK_CTL_REG \ 122 (CLK_CTL_REG_BASE + 0x00002658) 123 #define GSBIn_HCLK_CTL_REG(n) \ 124 (CLK_CTL_REG_BASE + 0x000029c0 + 32 * ((n)-1)) 125 #define GSBIn_QUP_APPS_NS_REG(n) \ 126 (CLK_CTL_REG_BASE + 0x000029cc + 32 * ((n)-1)) 127 #define GSBIn_QUP_APPS_MD_REG(n) \ 128 (CLK_CTL_REG_BASE + 0x000029c8 + 32 * ((n)-1)) 129 #define CLK_HALT_CFPB_STATEB_REG \ 130 (CLK_CTL_REG_BASE + 0x00002fd0) 131 132 #define GSBI5_HCLK 23 133 #define GSBI6_HCLK 19 134 #define GSBI7_HCLK 15 135 #define GSBI5_QUP_APPS_CLK 20 136 #define GSBI6_QUP_APPS_CLK 16 137 #define GSBI7_QUP_APPS_CLK 12 138 #define GSBI_CLK_BRANCH_ENA_MSK (1 << 4) 139 #define GSBI_CLK_BRANCH_ENA (1 << 4) 140 #define GSBI_CLK_BRANCH_DIS (0 << 4) 141 #define QUP_CLK_BRANCH_ENA_MSK (1 << 9) 142 #define QUP_CLK_BRANCH_ENA (1 << 9) 143 #define QUP_CLK_BRANCH_DIS (0 << 9) 144 #define CLK_ROOT_ENA_MSK (1 << 11) 145 #define CLK_ROOT_ENA (1 << 11) 146 #define CLK_ROOT_DIS (0 << 11) 147 148 #define QUP_STATE_VALID_BIT 2 149 #define QUP_STATE_VALID 1 150 #define QUP_STATE_MASK 0x3 151 #define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8) 152 #define QUP_CONFIG_MINI_CORE_SPI (1 << 8) 153 #define SPI_QUP_CONF_INPUT_MSK (1 << 7) 154 #define SPI_QUP_CONF_INPUT_ENA (0 << 7) 155 #define SPI_QUP_CONF_NO_INPUT (1 << 7) 156 #define SPI_QUP_CONF_OUTPUT_MSK (1 << 6) 157 #define SPI_QUP_CONF_OUTPUT_ENA (0 << 6) 158 #define SPI_QUP_CONF_NO_OUTPUT (1 << 6) 159 #define SPI_QUP_CONF_OUTPUT_ENA (0 << 6) 160 #define QUP_STATE_RESET_STATE 0x0 161 #define QUP_STATE_RUN_STATE 0x1 162 #define QUP_STATE_PAUSE_STATE 0x3 163 #define SPI_BIT_WORD_MSK 0x1F 164 #define SPI_8_BIT_WORD 0x07 165 #define PROTOCOL_CODE_MSK (0x07 << 4) 166 #define PROTOCOL_CODE_SPI (0x03 << 4) 167 #define LOOP_BACK_MSK (1 << 8) 168 #define NO_LOOP_BACK (0 << 8) 169 #define SLAVE_OPERATION_MSK (1 << 5) 170 #define SLAVE_OPERATION (0 << 5) 171 #define CLK_ALWAYS_ON (0 << 9) 172 #define MX_CS_MODE (0 << 8) 173 #define NO_TRI_STATE (1 << 0) 174 #define OUTPUT_BIT_SHIFT_MSK (1 << 16) 175 #define OUTPUT_BIT_SHIFT_EN (1 << 16) 176 #define INPUT_BLOCK_MODE_MSK (0x03 << 12) 177 #define INPUT_BLOCK_MODE (0x01 << 12) 178 #define OUTPUT_BLOCK_MODE_MSK (0x03 << 10) 179 #define OUTPUT_BLOCK_MODE (0x01 << 10) 180 #define GSBI1_RESET (1 << 0) 181 #define GSBI1_RESET_MSK 0x1 182 183 #define GSBI_M_VAL_SHFT 16 184 #define GSBIn_M_VAL_MSK (0xFF << GSBI_M_VAL_SHFT) 185 #define GSBI_N_VAL_SHFT 16 186 #define GSBIn_N_VAL_MSK (0xFF << GSBI_N_VAL_SHFT) 187 #define GSBI_D_VAL_SHFT 0 188 #define GSBIn_D_VAL_MSK (0xFF << GSBI_D_VAL_SHFT) 189 #define MNCNTR_RST_MSK (1 << 7) 190 #define MNCNTR_RST_ENA (1 << 7) 191 #define MNCNTR_RST_DIS (0 << 7) 192 #define MNCNTR_MSK (1 << 8) 193 #define MNCNTR_EN (1 << 8) 194 #define MNCNTR_DIS (0 << 8) 195 #define MNCNTR_MODE_MSK (0x3 << 5) 196 #define MNCNTR_MODE_BYPASS (0 << 5) 197 #define MNCNTR_MODE_DUAL_EDGE (0x2 << 5) 198 #define GSBI_PRE_DIV_SEL_SHFT 3 199 #define GSBIn_PRE_DIV_SEL_MSK (0x3 << GSBI_PRE_DIV_SEL_SHFT) 200 #define GSBIn_PLL_SRC_MSK (0x03 << 0) 201 #define GSBIn_PLL_SRC_PXO (0 << 0) 202 #define GSBIn_PLL_SRC_PLL8 (0x3 << 0) 203 204 #define SPI_INPUT_FIRST_MODE (1 << 9) 205 #define SPI_IO_CONTROL_CLOCK_IDLE_HIGH (1 << 10) 206 #define QUP_DATA_AVAILABLE_FOR_READ (1 << 5) 207 #define QUP_OUTPUT_FIFO_NOT_EMPTY (1 << 4) 208 #define OUTPUT_SERVICE_FLAG (1 << 8) 209 #define INPUT_SERVICE_FLAG (1 << 9) 210 #define QUP_OUTPUT_FIFO_FULL (1 << 6) 211 #define QUP_INPUT_FIFO_NOT_EMPTY (1 << 5) 212 #define SPI_INPUT_BLOCK_SIZE 4 213 #define SPI_OUTPUT_BLOCK_SIZE 4 214 #define GSBI5_SPI_CLK 21 215 #define GSBI5_SPI_MISO 19 216 #define GSBI5_SPI_MOSI 18 217 #define GSBI5_SPI_CS_0 20 218 #define GSBI5_SPI_CS_1 61 219 #define GSBI5_SPI_CS_2 62 220 #define GSBI5_SPI_CS_3 2 221 #define GSBI6_SPI_CLK 30 222 #define GSBI6_SPI_CS_0 29 223 #define GSBI6_SPI_MISO 28 224 #define GSBI6_SPI_MOSI 27 225 #define GSBI7_SPI_CLK 9 226 #define GSBI7_SPI_CS_0 8 227 #define GSBI7_SPI_MISO 7 228 #define GSBI7_SPI_MOSI 6 229 230 #define MSM_GSBI_MAX_FREQ 51200000 231 232 #define SPI_RESET_STATE 0 233 #define SPI_RUN_STATE 1 234 #define SPI_PAUSE_STATE 3 235 #define SPI_CORE_RESET 0 236 #define SPI_CORE_RUNNING 1 237 #define GSBI_SPI_MODE_0 0 238 #define GSBI_SPI_MODE_1 1 239 #define GSBI_SPI_MODE_2 2 240 #define GSBI_SPI_MODE_3 3 241 #define GSBI5_SPI 0 242 #define GSBI6_SPI 1 243 #define GSBI7_SPI 2 244 245 struct gsbi_spi { 246 unsigned int spi_config; 247 unsigned int io_control; 248 unsigned int error_flags; 249 unsigned int error_flags_en; 250 unsigned int gsbi_ctrl; 251 unsigned int qup_config; 252 unsigned int qup_error_flags; 253 unsigned int qup_error_flags_en; 254 unsigned int qup_operational; 255 unsigned int qup_io_modes; 256 unsigned int qup_state; 257 unsigned int qup_input_fifo; 258 unsigned int qup_output_fifo; 259 unsigned int qup_mx_input_count; 260 unsigned int qup_mx_output_count; 261 unsigned int qup_sw_reset; 262 unsigned int qup_ns_reg; 263 unsigned int qup_md_reg; 264 }; 265 266 struct ipq_spi_slave { 267 struct spi_slave slave; 268 const struct gsbi_spi *regs; 269 unsigned int mode; 270 unsigned int initialized; 271 unsigned long freq; 272 int allocated; 273 }; 274 275 #endif /* _IPQ806X_SPI_H_ */ 276