1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 /** 10 ************************************************************************************************************************ 11 * @file gfx9addrlib.h 12 * @brief Contgfx9ns the Gfx9Lib class definition. 13 ************************************************************************************************************************ 14 */ 15 16 #ifndef __GFX9_ADDR_LIB_H__ 17 #define __GFX9_ADDR_LIB_H__ 18 19 #include "addrlib2.h" 20 #include "coord.h" 21 22 namespace Addr 23 { 24 namespace V2 25 { 26 27 /** 28 ************************************************************************************************************************ 29 * @brief GFX9 specific settings structure. 30 ************************************************************************************************************************ 31 */ 32 struct Gfx9ChipSettings 33 { 34 struct 35 { 36 // Asic/Generation name 37 UINT_32 isArcticIsland : 1; 38 UINT_32 isVega10 : 1; 39 UINT_32 isRaven : 1; 40 UINT_32 isVega12 : 1; 41 UINT_32 isVega20 : 1; 42 UINT_32 reserved0 : 27; 43 44 // Display engine IP version name 45 UINT_32 isDce12 : 1; 46 UINT_32 isDcn1 : 1; 47 UINT_32 isDcn2 : 1; 48 UINT_32 reserved1 : 29; 49 50 // Misc configuration bits 51 UINT_32 metaBaseAlignFix : 1; 52 UINT_32 depthPipeXorDisable : 1; 53 UINT_32 htileAlignFix : 1; 54 UINT_32 applyAliasFix : 1; 55 UINT_32 htileCacheRbConflict: 1; 56 UINT_32 reserved2 : 27; 57 }; 58 }; 59 60 /** 61 ************************************************************************************************************************ 62 * @brief GFX9 data surface type. 63 ************************************************************************************************************************ 64 */ 65 enum Gfx9DataType 66 { 67 Gfx9DataColor, 68 Gfx9DataDepthStencil, 69 Gfx9DataFmask 70 }; 71 72 const UINT_32 Gfx9LinearSwModeMask = (1u << ADDR_SW_LINEAR); 73 74 const UINT_32 Gfx9Blk256BSwModeMask = (1u << ADDR_SW_256B_S) | 75 (1u << ADDR_SW_256B_D) | 76 (1u << ADDR_SW_256B_R); 77 78 const UINT_32 Gfx9Blk4KBSwModeMask = (1u << ADDR_SW_4KB_Z) | 79 (1u << ADDR_SW_4KB_S) | 80 (1u << ADDR_SW_4KB_D) | 81 (1u << ADDR_SW_4KB_R) | 82 (1u << ADDR_SW_4KB_Z_X) | 83 (1u << ADDR_SW_4KB_S_X) | 84 (1u << ADDR_SW_4KB_D_X) | 85 (1u << ADDR_SW_4KB_R_X); 86 87 const UINT_32 Gfx9Blk64KBSwModeMask = (1u << ADDR_SW_64KB_Z) | 88 (1u << ADDR_SW_64KB_S) | 89 (1u << ADDR_SW_64KB_D) | 90 (1u << ADDR_SW_64KB_R) | 91 (1u << ADDR_SW_64KB_Z_T) | 92 (1u << ADDR_SW_64KB_S_T) | 93 (1u << ADDR_SW_64KB_D_T) | 94 (1u << ADDR_SW_64KB_R_T) | 95 (1u << ADDR_SW_64KB_Z_X) | 96 (1u << ADDR_SW_64KB_S_X) | 97 (1u << ADDR_SW_64KB_D_X) | 98 (1u << ADDR_SW_64KB_R_X); 99 100 const UINT_32 Gfx9ZSwModeMask = (1u << ADDR_SW_4KB_Z) | 101 (1u << ADDR_SW_64KB_Z) | 102 (1u << ADDR_SW_64KB_Z_T) | 103 (1u << ADDR_SW_4KB_Z_X) | 104 (1u << ADDR_SW_64KB_Z_X); 105 106 const UINT_32 Gfx9StandardSwModeMask = (1u << ADDR_SW_256B_S) | 107 (1u << ADDR_SW_4KB_S) | 108 (1u << ADDR_SW_64KB_S) | 109 (1u << ADDR_SW_64KB_S_T) | 110 (1u << ADDR_SW_4KB_S_X) | 111 (1u << ADDR_SW_64KB_S_X); 112 113 const UINT_32 Gfx9DisplaySwModeMask = (1u << ADDR_SW_256B_D) | 114 (1u << ADDR_SW_4KB_D) | 115 (1u << ADDR_SW_64KB_D) | 116 (1u << ADDR_SW_64KB_D_T) | 117 (1u << ADDR_SW_4KB_D_X) | 118 (1u << ADDR_SW_64KB_D_X); 119 120 const UINT_32 Gfx9RotateSwModeMask = (1u << ADDR_SW_256B_R) | 121 (1u << ADDR_SW_4KB_R) | 122 (1u << ADDR_SW_64KB_R) | 123 (1u << ADDR_SW_64KB_R_T) | 124 (1u << ADDR_SW_4KB_R_X) | 125 (1u << ADDR_SW_64KB_R_X); 126 127 const UINT_32 Gfx9XSwModeMask = (1u << ADDR_SW_4KB_Z_X) | 128 (1u << ADDR_SW_4KB_S_X) | 129 (1u << ADDR_SW_4KB_D_X) | 130 (1u << ADDR_SW_4KB_R_X) | 131 (1u << ADDR_SW_64KB_Z_X) | 132 (1u << ADDR_SW_64KB_S_X) | 133 (1u << ADDR_SW_64KB_D_X) | 134 (1u << ADDR_SW_64KB_R_X); 135 136 const UINT_32 Gfx9TSwModeMask = (1u << ADDR_SW_64KB_Z_T) | 137 (1u << ADDR_SW_64KB_S_T) | 138 (1u << ADDR_SW_64KB_D_T) | 139 (1u << ADDR_SW_64KB_R_T); 140 141 const UINT_32 Gfx9XorSwModeMask = Gfx9XSwModeMask | 142 Gfx9TSwModeMask; 143 144 const UINT_32 Gfx9AllSwModeMask = Gfx9LinearSwModeMask | 145 Gfx9ZSwModeMask | 146 Gfx9StandardSwModeMask | 147 Gfx9DisplaySwModeMask | 148 Gfx9RotateSwModeMask; 149 150 const UINT_32 Gfx9Rsrc1dSwModeMask = Gfx9LinearSwModeMask; 151 152 const UINT_32 Gfx9Rsrc2dSwModeMask = Gfx9AllSwModeMask; 153 154 const UINT_32 Gfx9Rsrc3dSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9RotateSwModeMask; 155 156 const UINT_32 Gfx9Rsrc2dPrtSwModeMask = (Gfx9Blk4KBSwModeMask | Gfx9Blk64KBSwModeMask) & ~Gfx9XSwModeMask; 157 158 const UINT_32 Gfx9Rsrc3dPrtSwModeMask = Gfx9Rsrc2dPrtSwModeMask & ~Gfx9RotateSwModeMask & ~Gfx9DisplaySwModeMask; 159 160 const UINT_32 Gfx9Rsrc3dThinSwModeMask = Gfx9DisplaySwModeMask & ~Gfx9Blk256BSwModeMask; 161 162 const UINT_32 Gfx9Rsrc3dThin4KBSwModeMask = Gfx9Rsrc3dThinSwModeMask & Gfx9Blk4KBSwModeMask; 163 164 const UINT_32 Gfx9Rsrc3dThin64KBSwModeMask = Gfx9Rsrc3dThinSwModeMask & Gfx9Blk64KBSwModeMask; 165 166 const UINT_32 Gfx9Rsrc3dThickSwModeMask = Gfx9Rsrc3dSwModeMask & ~(Gfx9Rsrc3dThinSwModeMask | Gfx9LinearSwModeMask); 167 168 const UINT_32 Gfx9Rsrc3dThick4KBSwModeMask = Gfx9Rsrc3dThickSwModeMask & Gfx9Blk4KBSwModeMask; 169 170 const UINT_32 Gfx9Rsrc3dThick64KBSwModeMask = Gfx9Rsrc3dThickSwModeMask & Gfx9Blk64KBSwModeMask; 171 172 const UINT_32 Gfx9MsaaSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9LinearSwModeMask; 173 174 const UINT_32 Dce12NonBpp32SwModeMask = (1u << ADDR_SW_LINEAR) | 175 (1u << ADDR_SW_4KB_D) | 176 (1u << ADDR_SW_4KB_R) | 177 (1u << ADDR_SW_64KB_D) | 178 (1u << ADDR_SW_64KB_R) | 179 (1u << ADDR_SW_4KB_D_X) | 180 (1u << ADDR_SW_4KB_R_X) | 181 (1u << ADDR_SW_64KB_D_X) | 182 (1u << ADDR_SW_64KB_R_X); 183 184 const UINT_32 Dce12Bpp32SwModeMask = (1u << ADDR_SW_256B_D) | 185 (1u << ADDR_SW_256B_R) | 186 Dce12NonBpp32SwModeMask; 187 188 const UINT_32 Dcn1NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 189 (1u << ADDR_SW_4KB_S) | 190 (1u << ADDR_SW_64KB_S) | 191 (1u << ADDR_SW_64KB_S_T) | 192 (1u << ADDR_SW_4KB_S_X) | 193 (1u << ADDR_SW_64KB_S_X); 194 const UINT_32 Dcn1Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) | 195 (1u << ADDR_SW_64KB_D) | 196 (1u << ADDR_SW_64KB_D_T) | 197 (1u << ADDR_SW_4KB_D_X) | 198 (1u << ADDR_SW_64KB_D_X) | 199 Dcn1NonBpp64SwModeMask; 200 201 const UINT_32 Dcn2NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 202 (1u << ADDR_SW_64KB_S) | 203 (1u << ADDR_SW_64KB_S_T) | 204 (1u << ADDR_SW_64KB_S_X); 205 206 const UINT_32 Dcn2Bpp64SwModeMask = (1u << ADDR_SW_64KB_D) | 207 (1u << ADDR_SW_64KB_D_T) | 208 (1u << ADDR_SW_64KB_D_X) | 209 Dcn2NonBpp64SwModeMask; 210 211 /** 212 ************************************************************************************************************************ 213 * @brief GFX9 meta equation parameters 214 ************************************************************************************************************************ 215 */ 216 struct MetaEqParams 217 { 218 UINT_32 maxMip; 219 UINT_32 elementBytesLog2; 220 UINT_32 numSamplesLog2; 221 ADDR2_META_FLAGS metaFlag; 222 Gfx9DataType dataSurfaceType; 223 AddrSwizzleMode swizzleMode; 224 AddrResourceType resourceType; 225 UINT_32 metaBlkWidthLog2; 226 UINT_32 metaBlkHeightLog2; 227 UINT_32 metaBlkDepthLog2; 228 UINT_32 compBlkWidthLog2; 229 UINT_32 compBlkHeightLog2; 230 UINT_32 compBlkDepthLog2; 231 }; 232 233 /** 234 ************************************************************************************************************************ 235 * @brief This class is the GFX9 specific address library 236 * function set. 237 ************************************************************************************************************************ 238 */ 239 class Gfx9Lib : public Lib 240 { 241 public: 242 /// Creates Gfx9Lib object CreateObj(const Client * pClient)243 static Addr::Lib* CreateObj(const Client* pClient) 244 { 245 VOID* pMem = Object::ClientAlloc(sizeof(Gfx9Lib), pClient); 246 return (pMem != NULL) ? new (pMem) Gfx9Lib(pClient) : NULL; 247 } 248 249 protected: 250 Gfx9Lib(const Client* pClient); 251 virtual ~Gfx9Lib(); 252 HwlIsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)253 virtual BOOL_32 HwlIsStandardSwizzle( 254 AddrResourceType resourceType, 255 AddrSwizzleMode swizzleMode) const 256 { 257 return m_swizzleModeTable[swizzleMode].isStd || 258 (IsTex3d(resourceType) && m_swizzleModeTable[swizzleMode].isDisp); 259 } 260 HwlIsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)261 virtual BOOL_32 HwlIsDisplaySwizzle( 262 AddrResourceType resourceType, 263 AddrSwizzleMode swizzleMode) const 264 { 265 return IsTex2d(resourceType) && m_swizzleModeTable[swizzleMode].isDisp; 266 } 267 HwlIsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)268 virtual BOOL_32 HwlIsThin( 269 AddrResourceType resourceType, 270 AddrSwizzleMode swizzleMode) const 271 { 272 return ((IsTex2d(resourceType) == TRUE) || 273 ((IsTex3d(resourceType) == TRUE) && 274 (m_swizzleModeTable[swizzleMode].isZ == FALSE) && 275 (m_swizzleModeTable[swizzleMode].isStd == FALSE))); 276 } 277 HwlIsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)278 virtual BOOL_32 HwlIsThick( 279 AddrResourceType resourceType, 280 AddrSwizzleMode swizzleMode) const 281 { 282 return (IsTex3d(resourceType) && 283 (m_swizzleModeTable[swizzleMode].isZ || m_swizzleModeTable[swizzleMode].isStd)); 284 } 285 286 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 287 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 288 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 289 290 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo( 291 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 292 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; 293 294 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 295 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 296 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 297 298 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( 299 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 300 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 301 302 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 303 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 304 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 305 306 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 307 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 308 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 309 310 virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord( 311 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn); 312 313 virtual VOID HwlComputeDccAddrFromCoord( 314 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 315 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 316 317 virtual UINT_32 HwlGetEquationIndex( 318 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 319 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 320 321 virtual ADDR_E_RETURNCODE HwlComputeBlock256Equation( 322 AddrResourceType rsrcType, 323 AddrSwizzleMode swMode, 324 UINT_32 elementBytesLog2, 325 ADDR_EQUATION* pEquation) const; 326 327 virtual ADDR_E_RETURNCODE HwlComputeThinEquation( 328 AddrResourceType rsrcType, 329 AddrSwizzleMode swMode, 330 UINT_32 elementBytesLog2, 331 ADDR_EQUATION* pEquation) const; 332 333 virtual ADDR_E_RETURNCODE HwlComputeThickEquation( 334 AddrResourceType rsrcType, 335 AddrSwizzleMode swMode, 336 UINT_32 elementBytesLog2, 337 ADDR_EQUATION* pEquation) const; 338 339 // Get equation table pointer and number of equations HwlGetEquationTableInfo(const ADDR_EQUATION ** ppEquationTable)340 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 341 { 342 *ppEquationTable = m_equationTable; 343 344 return m_numEquations; 345 } 346 347 virtual BOOL_32 IsEquationSupported( 348 AddrResourceType rsrcType, 349 AddrSwizzleMode swMode, 350 UINT_32 elementBytesLog2) const; 351 352 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 353 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 354 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const; 355 356 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 357 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 358 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const; 359 360 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 361 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 362 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const; 363 364 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 365 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 366 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 367 368 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 369 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 370 371 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 372 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 373 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 374 375 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 376 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 377 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 378 379 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 380 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 381 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 382 383 virtual UINT_32 HwlComputeMaxBaseAlignments() const; 384 385 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const; 386 387 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn); 388 389 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 390 391 virtual VOID ComputeThinBlockDimension( 392 UINT_32* pWidth, 393 UINT_32* pHeight, 394 UINT_32* pDepth, 395 UINT_32 bpp, 396 UINT_32 numSamples, 397 AddrResourceType resourceType, 398 AddrSwizzleMode swizzleMode) const; 399 400 private: 401 VOID GetRbEquation(CoordEq* pRbEq, UINT_32 rbPerSeLog2, UINT_32 seLog2) const; 402 403 VOID GetDataEquation(CoordEq* pDataEq, Gfx9DataType dataSurfaceType, 404 AddrSwizzleMode swizzleMode, AddrResourceType resourceType, 405 UINT_32 elementBytesLog2, UINT_32 numSamplesLog2) const; 406 407 VOID GetPipeEquation(CoordEq* pPipeEq, CoordEq* pDataEq, 408 UINT_32 pipeInterleaveLog2, UINT_32 numPipesLog2, 409 UINT_32 numSamplesLog2, Gfx9DataType dataSurfaceType, 410 AddrSwizzleMode swizzleMode, AddrResourceType resourceType) const; 411 412 VOID GenMetaEquation(CoordEq* pMetaEq, UINT_32 maxMip, 413 UINT_32 elementBytesLog2, UINT_32 numSamplesLog2, 414 ADDR2_META_FLAGS metaFlag, Gfx9DataType dataSurfaceType, 415 AddrSwizzleMode swizzleMode, AddrResourceType resourceType, 416 UINT_32 metaBlkWidthLog2, UINT_32 metaBlkHeightLog2, 417 UINT_32 metaBlkDepthLog2, UINT_32 compBlkWidthLog2, 418 UINT_32 compBlkHeightLog2, UINT_32 compBlkDepthLog2) const; 419 420 const CoordEq* GetMetaEquation(const MetaEqParams& metaEqParams); 421 422 VOID GetMetaMipInfo(UINT_32 numMipLevels, Dim3d* pMetaBlkDim, 423 BOOL_32 dataThick, ADDR2_META_MIP_INFO* pInfo, 424 UINT_32 mip0Width, UINT_32 mip0Height, UINT_32 mip0Depth, 425 UINT_32* pNumMetaBlkX, UINT_32* pNumMetaBlkY, UINT_32* pNumMetaBlkZ) const; 426 427 BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 428 429 ADDR_E_RETURNCODE ComputeSurfaceLinearPadding( 430 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 431 UINT_32* pMipmap0PaddedWidth, 432 UINT_32* pSlice0PaddedHeight, 433 ADDR2_MIP_INFO* pMipInfo = NULL) const; 434 GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet,AddrResourceType rsrcType)435 static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet, AddrResourceType rsrcType) 436 { 437 ADDR2_BLOCK_SET allowedBlockSet = {}; 438 439 allowedBlockSet.micro = (allowedSwModeSet.value & Gfx9Blk256BSwModeMask) ? TRUE : FALSE; 440 allowedBlockSet.linear = (allowedSwModeSet.value & Gfx9LinearSwModeMask) ? TRUE : FALSE; 441 442 if (rsrcType == ADDR_RSRC_TEX_3D) 443 { 444 allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx9Rsrc3dThin4KBSwModeMask) ? TRUE : FALSE; 445 allowedBlockSet.macroThick4KB = (allowedSwModeSet.value & Gfx9Rsrc3dThick4KBSwModeMask) ? TRUE : FALSE; 446 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx9Rsrc3dThin64KBSwModeMask) ? TRUE : FALSE; 447 allowedBlockSet.macroThick64KB = (allowedSwModeSet.value & Gfx9Rsrc3dThick64KBSwModeMask) ? TRUE : FALSE; 448 } 449 else 450 { 451 allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx9Blk4KBSwModeMask) ? TRUE : FALSE; 452 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx9Blk64KBSwModeMask) ? TRUE : FALSE; 453 } 454 455 return allowedBlockSet; 456 } 457 GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)458 static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet) 459 { 460 ADDR2_SWTYPE_SET allowedSwSet = {}; 461 462 allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx9ZSwModeMask) ? TRUE : FALSE; 463 allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx9StandardSwModeMask) ? TRUE : FALSE; 464 allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx9DisplaySwModeMask) ? TRUE : FALSE; 465 allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx9RotateSwModeMask) ? TRUE : FALSE; 466 467 return allowedSwSet; 468 } 469 IsInMipTail(AddrResourceType resourceType,AddrSwizzleMode swizzleMode,Dim3d mipTailDim,UINT_32 width,UINT_32 height,UINT_32 depth)470 BOOL_32 IsInMipTail( 471 AddrResourceType resourceType, 472 AddrSwizzleMode swizzleMode, 473 Dim3d mipTailDim, 474 UINT_32 width, 475 UINT_32 height, 476 UINT_32 depth) const 477 { 478 BOOL_32 inTail = ((width <= mipTailDim.w) && 479 (height <= mipTailDim.h) && 480 (IsThin(resourceType, swizzleMode) || (depth <= mipTailDim.d))); 481 482 return inTail; 483 } 484 485 BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 486 BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 487 GetBankXorBits(UINT_32 macroBlockBits)488 UINT_32 GetBankXorBits(UINT_32 macroBlockBits) const 489 { 490 UINT_32 pipeBits = GetPipeXorBits(macroBlockBits); 491 492 // Bank xor bits 493 UINT_32 bankBits = Min(macroBlockBits - pipeBits - m_pipeInterleaveLog2, m_banksLog2); 494 495 return bankBits; 496 } 497 ComputeSurfaceBaseAlignTiled(AddrSwizzleMode swizzleMode)498 UINT_32 ComputeSurfaceBaseAlignTiled(AddrSwizzleMode swizzleMode) const 499 { 500 UINT_32 baseAlign; 501 502 if (IsXor(swizzleMode)) 503 { 504 baseAlign = GetBlockSize(swizzleMode); 505 } 506 else 507 { 508 baseAlign = 256; 509 } 510 511 return baseAlign; 512 } 513 514 // Initialize equation table 515 VOID InitEquationTable(); 516 517 ADDR_E_RETURNCODE ComputeStereoInfo( 518 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 519 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut, 520 UINT_32* pHeightAlign) const; 521 522 UINT_32 GetMipChainInfo( 523 AddrResourceType resourceType, 524 AddrSwizzleMode swizzleMode, 525 UINT_32 bpp, 526 UINT_32 mip0Width, 527 UINT_32 mip0Height, 528 UINT_32 mip0Depth, 529 UINT_32 blockWidth, 530 UINT_32 blockHeight, 531 UINT_32 blockDepth, 532 UINT_32 numMipLevel, 533 ADDR2_MIP_INFO* pMipInfo) const; 534 535 VOID GetMetaMiptailInfo( 536 ADDR2_META_MIP_INFO* pInfo, 537 Dim3d mipCoord, 538 UINT_32 numMipInTail, 539 Dim3d* pMetaBlkDim) const; 540 541 Dim3d GetMipStartPos( 542 AddrResourceType resourceType, 543 AddrSwizzleMode swizzleMode, 544 UINT_32 width, 545 UINT_32 height, 546 UINT_32 depth, 547 UINT_32 blockWidth, 548 UINT_32 blockHeight, 549 UINT_32 blockDepth, 550 UINT_32 mipId, 551 UINT_32 log2ElementBytes, 552 UINT_32* pMipTailBytesOffset) const; 553 GetMajorMode(AddrResourceType resourceType,AddrSwizzleMode swizzleMode,UINT_32 mip0WidthInBlk,UINT_32 mip0HeightInBlk,UINT_32 mip0DepthInBlk)554 AddrMajorMode GetMajorMode( 555 AddrResourceType resourceType, 556 AddrSwizzleMode swizzleMode, 557 UINT_32 mip0WidthInBlk, 558 UINT_32 mip0HeightInBlk, 559 UINT_32 mip0DepthInBlk) const 560 { 561 BOOL_32 yMajor = (mip0WidthInBlk < mip0HeightInBlk); 562 BOOL_32 xMajor = (yMajor == FALSE); 563 564 if (IsThick(resourceType, swizzleMode)) 565 { 566 yMajor = yMajor && (mip0HeightInBlk >= mip0DepthInBlk); 567 xMajor = xMajor && (mip0WidthInBlk >= mip0DepthInBlk); 568 } 569 570 AddrMajorMode majorMode; 571 if (xMajor) 572 { 573 majorMode = ADDR_MAJOR_X; 574 } 575 else if (yMajor) 576 { 577 majorMode = ADDR_MAJOR_Y; 578 } 579 else 580 { 581 majorMode = ADDR_MAJOR_Z; 582 } 583 584 return majorMode; 585 } 586 GetDccCompressBlk(AddrResourceType resourceType,AddrSwizzleMode swizzleMode,UINT_32 bpp)587 Dim3d GetDccCompressBlk( 588 AddrResourceType resourceType, 589 AddrSwizzleMode swizzleMode, 590 UINT_32 bpp) const 591 { 592 UINT_32 index = Log2(bpp >> 3); 593 Dim3d compressBlkDim; 594 595 if (IsThin(resourceType, swizzleMode)) 596 { 597 compressBlkDim.w = Block256_2d[index].w; 598 compressBlkDim.h = Block256_2d[index].h; 599 compressBlkDim.d = 1; 600 } 601 else if (IsStandardSwizzle(resourceType, swizzleMode)) 602 { 603 compressBlkDim = Block256_3dS[index]; 604 } 605 else 606 { 607 compressBlkDim = Block256_3dZ[index]; 608 } 609 610 return compressBlkDim; 611 } 612 613 static const UINT_32 MaxSeLog2 = 3; 614 static const UINT_32 MaxRbPerSeLog2 = 2; 615 616 static const Dim3d Block256_3dS[MaxNumOfBpp]; 617 static const Dim3d Block256_3dZ[MaxNumOfBpp]; 618 619 static const UINT_32 MipTailOffset256B[]; 620 621 static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE]; 622 623 static const UINT_32 MaxCachedMetaEq = 2; 624 625 Gfx9ChipSettings m_settings; 626 627 CoordEq m_cachedMetaEq[MaxCachedMetaEq]; 628 MetaEqParams m_cachedMetaEqKey[MaxCachedMetaEq]; 629 UINT_32 m_metaEqOverrideIndex; 630 }; 631 632 } // V2 633 } // Addr 634 635 #endif 636 637