1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 10 /** 11 ************************************************************************************************************************ 12 * @file addrlib2.h 13 * @brief Contains the Addr::V2::Lib class definition. 14 ************************************************************************************************************************ 15 */ 16 17 #ifndef __ADDR2_LIB2_H__ 18 #define __ADDR2_LIB2_H__ 19 20 #include "addrlib.h" 21 22 namespace Addr 23 { 24 namespace V2 25 { 26 27 /** 28 ************************************************************************************************************************ 29 * @brief Flags for SwizzleModeTable 30 ************************************************************************************************************************ 31 */ 32 union SwizzleModeFlags 33 { 34 struct 35 { 36 // Swizzle mode 37 UINT_32 isLinear : 1; // Linear 38 39 // Block size 40 UINT_32 is256b : 1; // Block size is 256B 41 UINT_32 is4kb : 1; // Block size is 4KB 42 UINT_32 is64kb : 1; // Block size is 64KB 43 UINT_32 isVar : 1; // Block size is variable 44 45 UINT_32 isZ : 1; // Z order swizzle mode 46 UINT_32 isStd : 1; // Standard swizzle mode 47 UINT_32 isDisp : 1; // Display swizzle mode 48 UINT_32 isRot : 1; // Rotate swizzle mode 49 50 // XOR mode 51 UINT_32 isXor : 1; // XOR after swizzle if set 52 53 UINT_32 isT : 1; // T mode 54 55 // GFX10 56 UINT_32 isRtOpt : 1; // mode opt for render target 57 58 UINT_32 reserved : 20; // Reserved bits 59 }; 60 61 UINT_32 u32All; 62 }; 63 64 struct Dim2d 65 { 66 UINT_32 w; 67 UINT_32 h; 68 }; 69 70 struct Dim3d 71 { 72 UINT_32 w; 73 UINT_32 h; 74 UINT_32 d; 75 }; 76 77 // Macro define resource block type 78 enum AddrBlockType 79 { 80 AddrBlockLinear = 0, // Resource uses linear swizzle mode 81 AddrBlockMicro = 1, // Resource uses 256B block 82 AddrBlockThin4KB = 2, // Resource uses thin 4KB block 83 AddrBlockThick4KB = 3, // Resource uses thick 4KB block 84 AddrBlockThin64KB = 4, // Resource uses thin 64KB block 85 AddrBlockThick64KB = 5, // Resource uses thick 64KB block 86 AddrBlockThinVar = 6, // Resource uses thin var block 87 AddrBlockThickVar = 7, // Resource uses thick var block 88 AddrBlockMaxTiledType, 89 90 AddrBlockThin256KB = AddrBlockThinVar, 91 AddrBlockThick256KB = AddrBlockThickVar, 92 }; 93 94 enum AddrSwSet 95 { 96 AddrSwSetZ = 1 << ADDR_SW_Z, 97 AddrSwSetS = 1 << ADDR_SW_S, 98 AddrSwSetD = 1 << ADDR_SW_D, 99 AddrSwSetR = 1 << ADDR_SW_R, 100 101 AddrSwSetAll = AddrSwSetZ | AddrSwSetS | AddrSwSetD | AddrSwSetR, 102 }; 103 104 const UINT_32 Size256 = 256u; 105 const UINT_32 Size4K = 4096u; 106 const UINT_32 Size64K = 65536u; 107 108 const UINT_32 Log2Size256 = 8u; 109 const UINT_32 Log2Size4K = 12u; 110 const UINT_32 Log2Size64K = 16u; 111 112 /** 113 ************************************************************************************************************************ 114 * @brief Bit setting for swizzle pattern 115 ************************************************************************************************************************ 116 */ 117 union ADDR_BIT_SETTING 118 { 119 struct 120 { 121 UINT_16 x; 122 UINT_16 y; 123 UINT_16 z; 124 UINT_16 s; 125 }; 126 UINT_64 value; 127 }; 128 129 /** 130 ************************************************************************************************************************ 131 * @brief Swizzle pattern information 132 ************************************************************************************************************************ 133 */ 134 // Accessed by index representing the logbase2 of (8bpp/16bpp/32bpp/64bpp/128bpp) 135 // contains the indices which map to 2D arrays SW_PATTERN_NIBBLE[0-9] which contain sections of an index equation. They are dependant on pipe# and bpe # 136 struct ADDR_SW_PATINFO 137 { 138 UINT_8 maxItemCount; 139 UINT_8 nibble01Idx; 140 UINT_16 nibble2Idx; 141 UINT_16 nibble3Idx; 142 UINT_8 nibble4Idx; 143 }; 144 145 /** 146 ************************************************************************************************************************ 147 * InitBit 148 * 149 * @brief 150 * Initialize bit setting value via a return value 151 ************************************************************************************************************************ 152 */ 153 #define InitBit(c, index) (1ull << ((c << 4) + index)) 154 155 const UINT_64 X0 = InitBit(0, 0); 156 const UINT_64 X1 = InitBit(0, 1); 157 const UINT_64 X2 = InitBit(0, 2); 158 const UINT_64 X3 = InitBit(0, 3); 159 const UINT_64 X4 = InitBit(0, 4); 160 const UINT_64 X5 = InitBit(0, 5); 161 const UINT_64 X6 = InitBit(0, 6); 162 const UINT_64 X7 = InitBit(0, 7); 163 const UINT_64 X8 = InitBit(0, 8); 164 const UINT_64 X9 = InitBit(0, 9); 165 const UINT_64 X10 = InitBit(0, 10); 166 const UINT_64 X11 = InitBit(0, 11); 167 168 const UINT_64 Y0 = InitBit(1, 0); 169 const UINT_64 Y1 = InitBit(1, 1); 170 const UINT_64 Y2 = InitBit(1, 2); 171 const UINT_64 Y3 = InitBit(1, 3); 172 const UINT_64 Y4 = InitBit(1, 4); 173 const UINT_64 Y5 = InitBit(1, 5); 174 const UINT_64 Y6 = InitBit(1, 6); 175 const UINT_64 Y7 = InitBit(1, 7); 176 const UINT_64 Y8 = InitBit(1, 8); 177 const UINT_64 Y9 = InitBit(1, 9); 178 const UINT_64 Y10 = InitBit(1, 10); 179 const UINT_64 Y11 = InitBit(1, 11); 180 181 const UINT_64 Z0 = InitBit(2, 0); 182 const UINT_64 Z1 = InitBit(2, 1); 183 const UINT_64 Z2 = InitBit(2, 2); 184 const UINT_64 Z3 = InitBit(2, 3); 185 const UINT_64 Z4 = InitBit(2, 4); 186 const UINT_64 Z5 = InitBit(2, 5); 187 const UINT_64 Z6 = InitBit(2, 6); 188 const UINT_64 Z7 = InitBit(2, 7); 189 const UINT_64 Z8 = InitBit(2, 8); 190 191 const UINT_64 S0 = InitBit(3, 0); 192 const UINT_64 S1 = InitBit(3, 1); 193 const UINT_64 S2 = InitBit(3, 2); 194 195 /** 196 ************************************************************************************************************************ 197 * @brief This class contains asic independent address lib functionalities 198 ************************************************************************************************************************ 199 */ 200 class Lib : public Addr::Lib 201 { 202 public: 203 virtual ~Lib(); 204 205 static Lib* GetLib( 206 ADDR_HANDLE hLib); 207 208 // 209 // Interface stubs 210 // 211 212 // For data surface 213 ADDR_E_RETURNCODE ComputeSurfaceInfo( 214 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 215 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 216 217 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord( 218 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 219 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 220 221 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr( 222 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 223 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 224 225 // For HTile 226 ADDR_E_RETURNCODE ComputeHtileInfo( 227 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 228 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 229 230 ADDR_E_RETURNCODE ComputeHtileAddrFromCoord( 231 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 232 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 233 234 ADDR_E_RETURNCODE ComputeHtileCoordFromAddr( 235 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 236 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 237 238 // For CMask 239 ADDR_E_RETURNCODE ComputeCmaskInfo( 240 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 241 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; 242 243 ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord( 244 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 245 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 246 247 ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr( 248 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 249 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const; 250 251 // For FMask 252 ADDR_E_RETURNCODE ComputeFmaskInfo( 253 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn, 254 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut); 255 256 ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord( 257 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 258 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const; 259 260 ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr( 261 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 262 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const; 263 264 // For DCC key 265 ADDR_E_RETURNCODE ComputeDccInfo( 266 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 267 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 268 269 ADDR_E_RETURNCODE ComputeDccAddrFromCoord( 270 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 271 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 272 273 // Misc 274 ADDR_E_RETURNCODE ComputePipeBankXor( 275 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 276 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut); 277 278 ADDR_E_RETURNCODE ComputeSlicePipeBankXor( 279 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 280 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut); 281 282 ADDR_E_RETURNCODE ComputeSubResourceOffsetForSwizzlePattern( 283 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 284 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut); 285 286 ADDR_E_RETURNCODE ComputeNonBlockCompressedView( 287 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 288 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut); 289 290 ADDR_E_RETURNCODE Addr2GetPreferredSurfaceSetting( 291 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 292 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 293 294 ADDR_E_RETURNCODE GetPossibleSwizzleModes( 295 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 296 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 297 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)298 virtual BOOL_32 IsValidDisplaySwizzleMode( 299 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 300 { 301 ADDR_NOT_IMPLEMENTED(); 302 return ADDR_NOTIMPLEMENTED; 303 } 304 305 ADDR_E_RETURNCODE GetAllowedBlockSet( 306 ADDR2_SWMODE_SET allowedSwModeSet, 307 AddrResourceType rsrcType, 308 ADDR2_BLOCK_SET* pAllowedBlockSet) const; 309 310 ADDR_E_RETURNCODE GetAllowedSwSet( 311 ADDR2_SWMODE_SET allowedSwModeSet, 312 ADDR2_SWTYPE_SET* pAllowedSwSet) const; 313 314 protected: 315 Lib(); // Constructor is protected 316 Lib(const Client* pClient); 317 318 static const UINT_32 MaxNumOfBpp = 5; 319 static const UINT_32 MaxNumOfBppCMask = 4; 320 static const UINT_32 MaxNumOfAA = 4; 321 322 static const Dim2d Block256_2d[MaxNumOfBpp]; 323 static const Dim3d Block1K_3d[MaxNumOfBpp]; 324 325 static const UINT_32 PrtAlignment = 64 * 1024; 326 static const UINT_32 MaxMacroBits = 20; 327 328 static const UINT_32 MaxMipLevels = 16; 329 IsValidSwMode(AddrSwizzleMode swizzleMode)330 BOOL_32 IsValidSwMode(AddrSwizzleMode swizzleMode) const 331 { 332 return (m_swizzleModeTable[swizzleMode].u32All != 0); 333 } 334 335 // Checking block size IsBlock256b(AddrSwizzleMode swizzleMode)336 BOOL_32 IsBlock256b(AddrSwizzleMode swizzleMode) const 337 { 338 return m_swizzleModeTable[swizzleMode].is256b; 339 } 340 IsBlock4kb(AddrSwizzleMode swizzleMode)341 BOOL_32 IsBlock4kb(AddrSwizzleMode swizzleMode) const 342 { 343 return m_swizzleModeTable[swizzleMode].is4kb; 344 } 345 IsBlock64kb(AddrSwizzleMode swizzleMode)346 BOOL_32 IsBlock64kb(AddrSwizzleMode swizzleMode) const 347 { 348 return m_swizzleModeTable[swizzleMode].is64kb; 349 } 350 IsBlockVariable(AddrSwizzleMode swizzleMode)351 BOOL_32 IsBlockVariable(AddrSwizzleMode swizzleMode) const 352 { 353 return m_swizzleModeTable[swizzleMode].isVar; 354 } 355 356 // Checking swizzle mode IsLinear(AddrSwizzleMode swizzleMode)357 BOOL_32 IsLinear(AddrSwizzleMode swizzleMode) const 358 { 359 return m_swizzleModeTable[swizzleMode].isLinear; 360 } 361 IsRtOptSwizzle(AddrSwizzleMode swizzleMode)362 BOOL_32 IsRtOptSwizzle(AddrSwizzleMode swizzleMode) const 363 { 364 return m_swizzleModeTable[swizzleMode].isRtOpt; 365 } 366 IsZOrderSwizzle(AddrSwizzleMode swizzleMode)367 BOOL_32 IsZOrderSwizzle(AddrSwizzleMode swizzleMode) const 368 { 369 return m_swizzleModeTable[swizzleMode].isZ; 370 } 371 IsStandardSwizzle(AddrSwizzleMode swizzleMode)372 BOOL_32 IsStandardSwizzle(AddrSwizzleMode swizzleMode) const 373 { 374 return m_swizzleModeTable[swizzleMode].isStd; 375 } 376 IsDisplaySwizzle(AddrSwizzleMode swizzleMode)377 BOOL_32 IsDisplaySwizzle(AddrSwizzleMode swizzleMode) const 378 { 379 return m_swizzleModeTable[swizzleMode].isDisp; 380 } 381 IsRotateSwizzle(AddrSwizzleMode swizzleMode)382 BOOL_32 IsRotateSwizzle(AddrSwizzleMode swizzleMode) const 383 { 384 return m_swizzleModeTable[swizzleMode].isRot; 385 } 386 IsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)387 BOOL_32 IsStandardSwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 388 { 389 return HwlIsStandardSwizzle(resourceType, swizzleMode); 390 } 391 IsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)392 BOOL_32 IsDisplaySwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 393 { 394 return HwlIsDisplaySwizzle(resourceType, swizzleMode); 395 } 396 IsXor(AddrSwizzleMode swizzleMode)397 BOOL_32 IsXor(AddrSwizzleMode swizzleMode) const 398 { 399 return m_swizzleModeTable[swizzleMode].isXor; 400 } 401 IsPrt(AddrSwizzleMode swizzleMode)402 BOOL_32 IsPrt(AddrSwizzleMode swizzleMode) const 403 { 404 return m_swizzleModeTable[swizzleMode].isT; 405 } 406 IsNonPrtXor(AddrSwizzleMode swizzleMode)407 BOOL_32 IsNonPrtXor(AddrSwizzleMode swizzleMode) const 408 { 409 return (IsXor(swizzleMode) && (IsPrt(swizzleMode) == FALSE)); 410 } 411 412 // Checking resource type IsTex1d(AddrResourceType resourceType)413 static BOOL_32 IsTex1d(AddrResourceType resourceType) 414 { 415 return (resourceType == ADDR_RSRC_TEX_1D); 416 } 417 IsTex2d(AddrResourceType resourceType)418 static BOOL_32 IsTex2d(AddrResourceType resourceType) 419 { 420 return (resourceType == ADDR_RSRC_TEX_2D); 421 } 422 IsTex3d(AddrResourceType resourceType)423 static BOOL_32 IsTex3d(AddrResourceType resourceType) 424 { 425 return (resourceType == ADDR_RSRC_TEX_3D); 426 } 427 IsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)428 BOOL_32 IsThick(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 429 { 430 return HwlIsThick(resourceType, swizzleMode); 431 } 432 IsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)433 BOOL_32 IsThin(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 434 { 435 return HwlIsThin(resourceType, swizzleMode); 436 } 437 GetBlockSizeLog2(AddrSwizzleMode swizzleMode)438 UINT_32 GetBlockSizeLog2(AddrSwizzleMode swizzleMode) const 439 { 440 UINT_32 blockSizeLog2 = 0; 441 442 if (IsBlock256b(swizzleMode) || IsLinear(swizzleMode)) 443 { 444 blockSizeLog2 = 8; 445 } 446 else if (IsBlock4kb(swizzleMode)) 447 { 448 blockSizeLog2 = 12; 449 } 450 else if (IsBlock64kb(swizzleMode)) 451 { 452 blockSizeLog2 = 16; 453 } 454 else if (IsBlockVariable(swizzleMode) && (m_blockVarSizeLog2 != 0)) 455 { 456 blockSizeLog2 = m_blockVarSizeLog2; 457 } 458 else 459 { 460 ADDR_ASSERT_ALWAYS(); 461 } 462 463 return blockSizeLog2; 464 } 465 GetBlockSize(AddrSwizzleMode swizzleMode)466 UINT_32 GetBlockSize(AddrSwizzleMode swizzleMode) const 467 { 468 return (1 << GetBlockSizeLog2(swizzleMode)); 469 } 470 GetFmaskBpp(UINT_32 sample,UINT_32 frag)471 static UINT_32 GetFmaskBpp(UINT_32 sample, UINT_32 frag) 472 { 473 sample = (sample == 0) ? 1 : sample; 474 frag = (frag == 0) ? sample : frag; 475 476 UINT_32 fmaskBpp = QLog2(frag); 477 478 if (sample > frag) 479 { 480 fmaskBpp++; 481 } 482 483 if (fmaskBpp == 3) 484 { 485 fmaskBpp = 4; 486 } 487 488 fmaskBpp = Max(8u, fmaskBpp * sample); 489 490 return fmaskBpp; 491 } 492 HwlIsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)493 virtual BOOL_32 HwlIsStandardSwizzle( 494 AddrResourceType resourceType, 495 AddrSwizzleMode swizzleMode) const 496 { 497 ADDR_NOT_IMPLEMENTED(); 498 return FALSE; 499 } 500 HwlIsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)501 virtual BOOL_32 HwlIsDisplaySwizzle( 502 AddrResourceType resourceType, 503 AddrSwizzleMode swizzleMode) const 504 { 505 ADDR_NOT_IMPLEMENTED(); 506 return FALSE; 507 } 508 HwlIsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)509 virtual BOOL_32 HwlIsThin( 510 AddrResourceType resourceType, 511 AddrSwizzleMode swizzleMode) const 512 { 513 ADDR_NOT_IMPLEMENTED(); 514 return FALSE; 515 } 516 HwlIsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)517 virtual BOOL_32 HwlIsThick( 518 AddrResourceType resourceType, 519 AddrSwizzleMode swizzleMode) const 520 { 521 ADDR_NOT_IMPLEMENTED(); 522 return FALSE; 523 } 524 HwlComputeHtileInfo(const ADDR2_COMPUTE_HTILE_INFO_INPUT * pIn,ADDR2_COMPUTE_HTILE_INFO_OUTPUT * pOut)525 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 526 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 527 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const 528 { 529 ADDR_NOT_IMPLEMENTED(); 530 return ADDR_NOTSUPPORTED; 531 } 532 HwlComputeCmaskInfo(const ADDR2_COMPUTE_CMASK_INFO_INPUT * pIn,ADDR2_COMPUTE_CMASK_INFO_OUTPUT * pOut)533 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo( 534 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 535 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const 536 { 537 ADDR_NOT_IMPLEMENTED(); 538 return ADDR_NOTSUPPORTED; 539 } 540 HwlComputeDccInfo(const ADDR2_COMPUTE_DCCINFO_INPUT * pIn,ADDR2_COMPUTE_DCCINFO_OUTPUT * pOut)541 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 542 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 543 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const 544 { 545 ADDR_NOT_IMPLEMENTED(); 546 return ADDR_NOTSUPPORTED; 547 } 548 HwlSupportComputeDccAddrFromCoord(const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT * pIn)549 virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord( 550 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn) 551 { 552 ADDR_NOT_IMPLEMENTED(); 553 return ADDR_NOTSUPPORTED; 554 } 555 HwlComputeDccAddrFromCoord(const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT * pOut)556 virtual VOID HwlComputeDccAddrFromCoord( 557 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 558 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) 559 { 560 ADDR_NOT_IMPLEMENTED(); 561 } 562 HwlComputeCmaskAddrFromCoord(const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT * pOut)563 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( 564 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 565 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) 566 { 567 ADDR_NOT_IMPLEMENTED(); 568 return ADDR_NOTSUPPORTED; 569 } 570 HwlComputeHtileAddrFromCoord(const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT * pOut)571 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 572 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 573 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) 574 { 575 ADDR_NOT_IMPLEMENTED(); 576 return ADDR_NOTSUPPORTED; 577 } 578 HwlComputeHtileCoordFromAddr(const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT * pIn,ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT * pOut)579 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 580 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 581 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) 582 { 583 ADDR_NOT_IMPLEMENTED(); 584 return ADDR_NOTSUPPORTED; 585 } 586 HwlComputeBlock256Equation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)587 virtual ADDR_E_RETURNCODE HwlComputeBlock256Equation( 588 AddrResourceType rsrcType, 589 AddrSwizzleMode swMode, 590 UINT_32 elementBytesLog2, 591 ADDR_EQUATION* pEquation) const 592 { 593 ADDR_NOT_IMPLEMENTED(); 594 return ADDR_NOTSUPPORTED; 595 } 596 HwlComputeThinEquation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)597 virtual ADDR_E_RETURNCODE HwlComputeThinEquation( 598 AddrResourceType rsrcType, 599 AddrSwizzleMode swMode, 600 UINT_32 elementBytesLog2, 601 ADDR_EQUATION* pEquation) const 602 { 603 ADDR_NOT_IMPLEMENTED(); 604 return ADDR_NOTSUPPORTED; 605 } 606 HwlComputeThickEquation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)607 virtual ADDR_E_RETURNCODE HwlComputeThickEquation( 608 AddrResourceType rsrcType, 609 AddrSwizzleMode swMode, 610 UINT_32 elementBytesLog2, 611 ADDR_EQUATION* pEquation) const 612 { 613 ADDR_NOT_IMPLEMENTED(); 614 return ADDR_NOTSUPPORTED; 615 } 616 HwlGetEquationIndex(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)617 virtual UINT_32 HwlGetEquationIndex( 618 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 619 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 620 { 621 ADDR_NOT_IMPLEMENTED(); 622 return ADDR_INVALID_EQUATION_INDEX; 623 } 624 GetEquationIndex(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)625 UINT_32 GetEquationIndex( 626 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 627 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 628 { 629 return HwlGetEquationIndex(pIn, pOut); 630 } 631 HwlComputePipeBankXor(const ADDR2_COMPUTE_PIPEBANKXOR_INPUT * pIn,ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT * pOut)632 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 633 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 634 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const 635 { 636 ADDR_NOT_IMPLEMENTED(); 637 return ADDR_NOTSUPPORTED; 638 } 639 HwlComputeSlicePipeBankXor(const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT * pIn,ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT * pOut)640 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 641 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 642 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const 643 { 644 ADDR_NOT_IMPLEMENTED(); 645 return ADDR_NOTSUPPORTED; 646 } 647 HwlComputeSubResourceOffsetForSwizzlePattern(const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT * pIn,ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT * pOut)648 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 649 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 650 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const 651 { 652 ADDR_NOT_IMPLEMENTED(); 653 return ADDR_NOTSUPPORTED; 654 } 655 HwlComputeNonBlockCompressedView(const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT * pIn,ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT * pOut)656 virtual ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView( 657 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 658 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const 659 { 660 ADDR_NOT_IMPLEMENTED(); 661 return ADDR_NOTSUPPORTED; 662 } 663 HwlGetPreferredSurfaceSetting(const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT * pIn,ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT * pOut)664 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 665 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 666 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const 667 { 668 ADDR_NOT_IMPLEMENTED(); 669 return ADDR_NOTSUPPORTED; 670 } 671 HwlGetPossibleSwizzleModes(const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT * pIn,ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT * pOut)672 virtual ADDR_E_RETURNCODE HwlGetPossibleSwizzleModes( 673 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 674 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const 675 { 676 ADDR_NOT_IMPLEMENTED(); 677 return ADDR_NOTSUPPORTED; 678 } 679 HwlGetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet,AddrResourceType rsrcType,ADDR2_BLOCK_SET * pAllowedBlockSet)680 virtual ADDR_E_RETURNCODE HwlGetAllowedBlockSet( 681 ADDR2_SWMODE_SET allowedSwModeSet, 682 AddrResourceType rsrcType, 683 ADDR2_BLOCK_SET* pAllowedBlockSet) const 684 { 685 ADDR_NOT_IMPLEMENTED(); 686 return ADDR_NOTIMPLEMENTED; 687 } 688 HwlGetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet,ADDR2_SWTYPE_SET * pAllowedSwSet)689 virtual ADDR_E_RETURNCODE HwlGetAllowedSwSet( 690 ADDR2_SWMODE_SET allowedSwModeSet, 691 ADDR2_SWTYPE_SET* pAllowedSwSet) const 692 { 693 ADDR_NOT_IMPLEMENTED(); 694 return ADDR_NOTIMPLEMENTED; 695 } 696 HwlComputeSurfaceInfoSanityCheck(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)697 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 698 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 699 { 700 ADDR_NOT_IMPLEMENTED(); 701 return ADDR_NOTSUPPORTED; 702 } 703 HwlComputeSurfaceInfoTiled(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)704 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 705 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 706 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 707 { 708 ADDR_NOT_IMPLEMENTED(); 709 return ADDR_NOTIMPLEMENTED; 710 } 711 HwlComputeSurfaceInfoLinear(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)712 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 713 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 714 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 715 { 716 ADDR_NOT_IMPLEMENTED(); 717 return ADDR_NOTIMPLEMENTED; 718 } 719 HwlComputeSurfaceAddrFromCoordTiled(const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT * pOut)720 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 721 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 722 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const 723 { 724 ADDR_NOT_IMPLEMENTED(); 725 return ADDR_NOTIMPLEMENTED; 726 } 727 728 ADDR_E_RETURNCODE ComputeBlock256Equation( 729 AddrResourceType rsrcType, 730 AddrSwizzleMode swMode, 731 UINT_32 elementBytesLog2, 732 ADDR_EQUATION* pEquation) const; 733 734 ADDR_E_RETURNCODE ComputeThinEquation( 735 AddrResourceType rsrcType, 736 AddrSwizzleMode swMode, 737 UINT_32 elementBytesLog2, 738 ADDR_EQUATION* pEquation) const; 739 740 ADDR_E_RETURNCODE ComputeThickEquation( 741 AddrResourceType rsrcType, 742 AddrSwizzleMode swMode, 743 UINT_32 elementBytesLog2, 744 ADDR_EQUATION* pEquation) const; 745 746 ADDR_E_RETURNCODE ComputeSurfaceInfoSanityCheck( 747 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 748 749 ADDR_E_RETURNCODE ComputeSurfaceInfoLinear( 750 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 751 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 752 753 ADDR_E_RETURNCODE ComputeSurfaceInfoTiled( 754 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 755 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 756 757 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordLinear( 758 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 759 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 760 761 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordTiled( 762 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 763 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 764 765 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrLinear( 766 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 767 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 768 769 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrTiled( 770 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 771 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 772 773 UINT_32 ComputeSurface2DMicroBlockOffset( 774 const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const; 775 776 UINT_32 ComputeSurface3DMicroBlockOffset( 777 const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const; 778 779 // Misc 780 ADDR_E_RETURNCODE ComputeBlockDimensionForSurf( 781 UINT_32* pWidth, 782 UINT_32* pHeight, 783 UINT_32* pDepth, 784 UINT_32 bpp, 785 UINT_32 numSamples, 786 AddrResourceType resourceType, 787 AddrSwizzleMode swizzleMode) const; 788 789 ADDR_E_RETURNCODE ComputeBlockDimension( 790 UINT_32* pWidth, 791 UINT_32* pHeight, 792 UINT_32* pDepth, 793 UINT_32 bpp, 794 AddrResourceType resourceType, 795 AddrSwizzleMode swizzleMode) const; 796 797 virtual VOID ComputeThinBlockDimension( 798 UINT_32* pWidth, 799 UINT_32* pHeight, 800 UINT_32* pDepth, 801 UINT_32 bpp, 802 UINT_32 numSamples, 803 AddrResourceType resourceType, 804 AddrSwizzleMode swizzleMode) const; 805 806 VOID ComputeThickBlockDimension( 807 UINT_32* pWidth, 808 UINT_32* pHeight, 809 UINT_32* pDepth, 810 UINT_32 bpp, 811 AddrResourceType resourceType, 812 AddrSwizzleMode swizzleMode) const; 813 ComputePadSize(const Dim3d * pBlkDim,UINT_32 width,UINT_32 height,UINT_32 numSlices,Dim3d * pPadDim)814 static UINT_64 ComputePadSize( 815 const Dim3d* pBlkDim, 816 UINT_32 width, 817 UINT_32 height, 818 UINT_32 numSlices, 819 Dim3d* pPadDim) 820 { 821 pPadDim->w = PowTwoAlign(width ,pBlkDim->w); 822 pPadDim->h = PowTwoAlign(height ,pBlkDim->h); 823 pPadDim->d = PowTwoAlign(numSlices, pBlkDim->d); 824 return static_cast<UINT_64>(pPadDim->w) * pPadDim->h * pPadDim->d; 825 } 826 827 static ADDR_E_RETURNCODE ExtractPipeBankXor( 828 UINT_32 pipeBankXor, 829 UINT_32 bankBits, 830 UINT_32 pipeBits, 831 UINT_32* pBankX, 832 UINT_32* pPipeX); 833 Valid3DMipSliceIdConstraint(UINT_32 numSlices,UINT_32 mipId,UINT_32 slice)834 static BOOL_32 Valid3DMipSliceIdConstraint( 835 UINT_32 numSlices, 836 UINT_32 mipId, 837 UINT_32 slice) 838 { 839 return (Max((numSlices >> mipId), 1u) > slice); 840 } 841 842 Dim3d GetMipTailDim( 843 AddrResourceType resourceType, 844 AddrSwizzleMode swizzleMode, 845 UINT_32 blockWidth, 846 UINT_32 blockHeight, 847 UINT_32 blockDepth) const; 848 IsLocalHeap(AddrResrouceLocation resourceType)849 static BOOL_32 IsLocalHeap(AddrResrouceLocation resourceType) 850 { 851 return ((resourceType == ADDR_RSRC_LOC_LOCAL) || 852 (resourceType == ADDR_RSRC_LOC_INVIS)); 853 } 854 IsInvisibleHeap(AddrResrouceLocation resourceType)855 static BOOL_32 IsInvisibleHeap(AddrResrouceLocation resourceType) 856 { 857 return (resourceType == ADDR_RSRC_LOC_INVIS); 858 } 859 IsNonlocalHeap(AddrResrouceLocation resourceType)860 static BOOL_32 IsNonlocalHeap(AddrResrouceLocation resourceType) 861 { 862 return ((resourceType == ADDR_RSRC_LOC_USWC) || 863 (resourceType == ADDR_RSRC_LOC_CACHED)); 864 } 865 GetPipeLog2ForMetaAddressing(BOOL_32 pipeAligned,AddrSwizzleMode swizzleMode)866 UINT_32 GetPipeLog2ForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const 867 { 868 UINT_32 numPipeLog2 = pipeAligned ? Min(m_pipesLog2 + m_seLog2, 5u) : 0; 869 870 if (IsXor(swizzleMode)) 871 { 872 UINT_32 maxPipeLog2 = GetBlockSizeLog2(swizzleMode) - m_pipeInterleaveLog2; 873 874 numPipeLog2 = Min(numPipeLog2, maxPipeLog2); 875 } 876 877 return numPipeLog2; 878 } 879 GetPipeNumForMetaAddressing(BOOL_32 pipeAligned,AddrSwizzleMode swizzleMode)880 UINT_32 GetPipeNumForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const 881 { 882 return (1 << GetPipeLog2ForMetaAddressing(pipeAligned, swizzleMode)); 883 } 884 VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)885 VOID VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 886 { 887 #if DEBUG 888 if (pIn->numMipLevels > 1) 889 { 890 UINT_32 actualMipLevels = 1; 891 switch (pIn->resourceType) 892 { 893 case ADDR_RSRC_TEX_3D: 894 // Fall through to share 2D case 895 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->numSlices) + 1); 896 case ADDR_RSRC_TEX_2D: 897 // Fall through to share 1D case 898 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->height) + 1); 899 case ADDR_RSRC_TEX_1D: 900 // Base 1D case 901 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->width) + 1); 902 break; 903 default: 904 ADDR_ASSERT_ALWAYS(); 905 break; 906 } 907 // Client pass wrong number of MipLevels to addrlib and result will be bad. 908 // Not sure if we should fail this calling instead of putting an assertion here. 909 ADDR_ASSERT(actualMipLevels >= pIn->numMipLevels); 910 } 911 #endif 912 } 913 ApplyCustomerPipeBankXor(AddrSwizzleMode swizzleMode,UINT_32 pipeBankXor,UINT_32 bankBits,UINT_32 pipeBits,UINT_32 * pBlockOffset)914 ADDR_E_RETURNCODE ApplyCustomerPipeBankXor( 915 AddrSwizzleMode swizzleMode, 916 UINT_32 pipeBankXor, 917 UINT_32 bankBits, 918 UINT_32 pipeBits, 919 UINT_32* pBlockOffset) const 920 { 921 ADDR_E_RETURNCODE returnCode = ADDR_OK; 922 923 if (IsXor(swizzleMode)) 924 { 925 // Apply driver set bankPipeXor 926 UINT_32 bankX = 0; 927 UINT_32 pipeX = 0; 928 returnCode = ExtractPipeBankXor(pipeBankXor, bankBits, pipeBits, &bankX, &pipeX); 929 *pBlockOffset ^= (pipeX << m_pipeInterleaveLog2); 930 *pBlockOffset ^= (bankX << (m_pipeInterleaveLog2 + pipeBits)); 931 } 932 933 return returnCode; 934 } 935 936 UINT_32 GetPipeXorBits(UINT_32 macroBlockBits) const; 937 938 ADDR_E_RETURNCODE ApplyCustomizedPitchHeight( 939 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 940 UINT_32 elementBytes, 941 UINT_32 pitchAlignInElement, 942 UINT_32* pPitch, 943 UINT_32* pHeight) const; 944 945 VOID ComputeQbStereoInfo(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 946 947 VOID FilterInvalidEqSwizzleMode( 948 ADDR2_SWMODE_SET& allowedSwModeSet, 949 AddrResourceType resourceType, 950 UINT_32 elemLog2, 951 UINT_32 maxComponents) const; 952 953 #if DEBUG 954 VOID ValidateStereoInfo( 955 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 956 const ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 957 #endif 958 959 UINT_32 m_se; ///< Number of shader engine 960 UINT_32 m_rbPerSe; ///< Number of render backend per shader engine 961 UINT_32 m_maxCompFrag; ///< Number of max compressed fragment 962 963 UINT_32 m_banksLog2; ///< Number of bank Log2 964 UINT_32 m_pipesLog2; ///< Number of pipe per shader engine Log2 965 UINT_32 m_seLog2; ///< Number of shader engine Log2 966 UINT_32 m_rbPerSeLog2; ///< Number of render backend per shader engine Log2 967 UINT_32 m_maxCompFragLog2; ///< Number of max compressed fragment Log2 968 969 UINT_32 m_pipeInterleaveLog2; ///< Log2 of pipe interleave bytes 970 971 UINT_32 m_blockVarSizeLog2; ///< Log2 of block var size 972 973 SwizzleModeFlags m_swizzleModeTable[ADDR_SW_MAX_TYPE]; ///< Swizzle mode table 974 975 // Max number of swizzle mode supported for equation 976 static const UINT_32 MaxSwModeType = 32; 977 // Max number of resource type (2D/3D) supported for equation 978 static const UINT_32 MaxRsrcType = 2; 979 // Max number of bpp (8bpp/16bpp/32bpp/64bpp/128bpp) 980 static const UINT_32 MaxElementBytesLog2 = 5; 981 // Almost all swizzle mode + resource type support equation 982 static const UINT_32 EquationTableSize = MaxElementBytesLog2 * MaxSwModeType * MaxRsrcType; 983 // Equation table 984 ADDR_EQUATION m_equationTable[EquationTableSize]; 985 986 // Number of equation entries in the table 987 UINT_32 m_numEquations; 988 // Equation lookup table according to bpp and tile index 989 UINT_32 m_equationLookupTable[MaxRsrcType][MaxSwModeType][MaxElementBytesLog2]; 990 991 private: 992 // Disallow the copy constructor 993 Lib(const Lib& a); 994 995 // Disallow the assignment operator 996 Lib& operator=(const Lib& a); 997 }; 998 999 } // V2 1000 } // Addr 1001 1002 #endif 1003 1004