1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_CHIP_H_ 4 #define _SOC_CHIP_H_ 5 6 #include <acpi/acpi_device.h> 7 #include <device/i2c_simple.h> 8 #include <drivers/i2c/designware/dw_i2c.h> 9 #include <drivers/intel/gma/gma.h> 10 #include <gpio.h> 11 #include <intelblocks/cfg.h> 12 #include <intelblocks/gspi.h> 13 #include <intelblocks/lpc_lib.h> 14 #include <intelblocks/power_limit.h> 15 #include <intelblocks/xhci.h> 16 #include <stdbool.h> 17 #include <stdint.h> 18 #include <soc/gpe.h> 19 #include <soc/irq.h> 20 #include <soc/pci_devs.h> 21 #include <soc/pmc.h> 22 #include <soc/serialio.h> 23 #include <soc/usb.h> 24 #include <soc/vr_config.h> 25 26 #define MAX_PEG_PORTS 3 27 28 enum skylake_i2c_voltage { 29 I2C_VOLTAGE_3V3, 30 I2C_VOLTAGE_1V8 31 }; 32 33 struct soc_intel_skylake_config { 34 /* Common struct containing soc config data required by common code */ 35 struct soc_intel_common_config common_soc_config; 36 37 /* Common struct containing power limits configuration information */ 38 struct soc_power_limits_config power_limits_config; 39 40 /* IGD panel configuration */ 41 struct i915_gpu_panel_config panel_cfg; 42 43 /* Gpio group routed to each dword of the GPE0 block. Values are 44 * of the form GPP_[A:G] or GPD. */ 45 uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ 46 uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ 47 uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ 48 49 /* LPC fixed enables and ranges */ 50 uint16_t lpc_iod; 51 uint16_t lpc_ioe; 52 53 /* Generic IO decode ranges */ 54 uint32_t gen1_dec; 55 uint32_t gen2_dec; 56 uint32_t gen3_dec; 57 uint32_t gen4_dec; 58 59 /* Enable S0iX support */ 60 bool s0ix_enable; 61 62 /* Enable DPTF support */ 63 bool dptf_enable; 64 65 /* Deep SX enables */ 66 bool deep_s3_enable_ac; 67 bool deep_s3_enable_dc; 68 bool deep_s5_enable_ac; 69 bool deep_s5_enable_dc; 70 71 /* 72 * Deep Sx Configuration 73 * DSX_EN_WAKE_PIN - Enable WAKE# pin 74 * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin 75 * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin 76 */ 77 uint32_t deep_sx_config; 78 79 /* TCC activation offset */ 80 uint32_t tcc_offset; 81 82 /* 83 * System Agent dynamic frequency configuration 84 * When enabled memory will be trained at two different frequencies. 85 * 0 = Disabled 86 * 1 = FixedLow 87 * 2 = FixedHigh 88 * 3 = Enabled 89 */ 90 enum { 91 SaGv_Disabled, 92 SaGv_FixedLow, 93 SaGv_FixedHigh, 94 SaGv_Enabled, 95 } SaGv; 96 97 /* Enable/disable Rank Margin Tool */ 98 bool RMT; 99 100 /* Disable Command TriState */ 101 bool CmdTriStateDis; 102 103 /* Lan */ 104 bool EnableLanLtr; 105 bool EnableLanK1Off; 106 bool LanClkReqSupported; 107 u8 LanClkReqNumber; 108 109 /* SATA related */ 110 enum { 111 SATA_AHCI = 0, 112 SATA_RAID = 1, 113 } SataMode; 114 bool SataSalpSupport; 115 bool SataPortsEnable[8]; 116 bool SataPortsDevSlp[8]; 117 bool SataPortsSpinUp[8]; 118 bool SataPortsHotPlug[8]; 119 u8 SataSpeedLimit; 120 121 /* Audio related */ 122 bool DspEnable; 123 124 /* HDA Virtual Channel Type Select */ 125 enum { 126 Vc0, 127 Vc1, 128 } PchHdaVcType; 129 130 /* 131 * I/O Buffer Ownership: 132 * 0: HD-A Link 133 * 1 Shared, HD-A Link and I2S Port 134 * 3: I2S Ports 135 */ 136 u8 IoBufferOwnership; 137 138 /* Trace Hub function */ 139 u32 TraceHubMemReg0Size; 140 u32 TraceHubMemReg1Size; 141 142 /* DCI Enable/Disable */ 143 bool PchDciEn; 144 145 /* 146 * PCIe Root Port configuration: 147 * each element of array corresponds to 148 * respective PCIe root port. 149 */ 150 151 /* PEG Max Link Width */ 152 enum { 153 Peg0_x16, 154 Peg0_x1, 155 Peg0_x2, 156 Peg0_x4, 157 Peg0_x8, 158 } Peg0MaxLinkWidth; 159 160 enum { 161 Peg1_x8, 162 Peg1_x1, 163 Peg1_x2, 164 Peg1_x4, 165 } Peg1MaxLinkWidth; 166 167 enum { 168 Peg2_x4, 169 Peg2_x1, 170 Peg2_x2, 171 } Peg2MaxLinkWidth; 172 173 /* 174 * Enable/Disable Root Port 175 * 0: Disable Root Port 176 * 1: Enable Root Port 177 */ 178 bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; 179 180 /* 181 * Enable/Disable Clk-req support for Root Port 182 * 0: Disable Clk-Req 183 * 1: Enable Clk-req 184 */ 185 bool PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS]; 186 187 /* 188 * Clk-req source for Root Port 189 */ 190 u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS]; 191 192 /* 193 * Clk source number for Root Port 194 */ 195 u8 PcieRpClkSrcNumber[CONFIG_MAX_ROOT_PORTS]; 196 197 /* 198 * Enable/Disable AER (Advanced Error Reporting) for Root Port 199 * 0: Disable AER 200 * 1: Enable AER 201 */ 202 bool PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; 203 204 /* 205 * Enable/Disable Latency Tolerance Reporting for Root Port 206 * 0: Disable LTR 207 * 1: Enable LTR 208 */ 209 bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; 210 211 /* Enable/Disable HotPlug support for Root Port */ 212 bool PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; 213 214 /* PCIE RP Max Payload, Max Payload Size supported */ 215 enum { 216 RpMaxPayload_128, 217 RpMaxPayload_256, 218 } PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS]; 219 220 /* PCIE RP ASPM, ASPM support for the root port */ 221 enum { 222 AspmDefault, 223 AspmDisabled, 224 AspmL0s, 225 AspmL1, 226 AspmL0sL1, 227 AspmAutoConfig, 228 } pcie_rp_aspm[CONFIG_MAX_ROOT_PORTS]; 229 230 /* PCIe RP L1 substate */ 231 enum { 232 L1SS_Default, 233 L1SS_Disabled, 234 L1SS_L1_1, 235 L1SS_L1_2, 236 } pcie_rp_l1substates[CONFIG_MAX_ROOT_PORTS]; 237 238 /* USB related */ 239 struct usb2_port_config usb2_ports[16]; 240 struct usb3_port_config usb3_ports[10]; 241 bool SsicPortEnable; 242 243 /* 244 * SerialIO device mode selection: 245 * 246 * Device index: 247 * PchSerialIoIndexI2C0 248 * PchSerialIoIndexI2C1 249 * PchSerialIoIndexI2C2 250 * PchSerialIoIndexI2C3 251 * PchSerialIoIndexI2C4 252 * PchSerialIoIndexI2C5 253 * PchSerialIoIndexI2C6 254 * PchSerialIoIndexSpi0 255 * PchSerialIoIndexSpi1 256 * PchSerialIoIndexUart0 257 * PchSerialIoIndexUart1 258 * PchSerialIoIndexUart2 259 * 260 * Mode select: 261 * PchSerialIoDisabled 262 * PchSerialIoAcpi 263 * PchSerialIoPci 264 * PchSerialIoAcpiHidden 265 * PchSerialIoLegacyUart 266 */ 267 u8 SerialIoDevMode[PchSerialIoIndexMax]; 268 269 /* I2C */ 270 /* Bus voltage level, default is 3.3V */ 271 enum skylake_i2c_voltage i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX]; 272 273 /* eMMC and SD */ 274 bool ScsEmmcHs400Enabled; 275 bool EmmcHs400DllNeed; 276 u8 ScsEmmcHs400RxStrobeDll1; 277 u8 ScsEmmcHs400TxDataDll; 278 279 enum { 280 Display_iGFX, 281 Display_PEG, 282 Display_PCH_PCIe, 283 Display_Auto, 284 Display_Switchable, 285 } PrimaryDisplay; 286 bool SkipExtGfxScan; 287 288 /* GPIO IRQ Route The valid values is 14 or 15*/ 289 u8 GpioIrqSelect; 290 /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23*/ 291 u8 SciIrqSelect; 292 /* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23*/ 293 u8 TcoIrqSelect; 294 bool TcoIrqEnable; 295 /* Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.*/ 296 bool LockDownConfigGlobalSmi; 297 /* 298 * Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh 299 * in the upper and lower 128-byte bank of RTC RAM. 300 */ 301 bool LockDownConfigRtcLock; 302 303 /* 304 * Determine if WLAN wake from Sx, corresponds to the 305 * HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. 306 */ 307 bool PchPmWoWlanEnable; 308 309 /* 310 * Determine if WLAN wake from DeepSx, corresponds to 311 * the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. 312 */ 313 bool PchPmWoWlanDeepSxEnable; 314 315 /* 316 * Corresponds to the "WOL Enable Override" bit in the General PM 317 * Configuration B (GEN_PMCON_B) register 318 */ 319 bool WakeConfigWolEnableOverride; 320 /* Determine if enable PCIe to wake from deep Sx*/ 321 bool WakeConfigPcieWakeFromDeepSx; 322 /* Deep Sx Policy. Values 0: PchDeepSxPolDisable, 323 * 1: PchDpS5BatteryEn, 2: PchDpS5AlwaysEn, 3: PchDpS4S5BatteryEn, 324 * 4: PchDpS4S5AlwaysEn, 5: PchDpS3S4S5BatteryEn, 6: PchDpS3S4S5AlwaysEn 325 */ 326 u8 PmConfigDeepSxPol; 327 328 enum { 329 SLP_S3_MIN_ASSERT_60US = 0, 330 SLP_S3_MIN_ASSERT_1MS = 1, 331 SLP_S3_MIN_ASSERT_50MS = 2, 332 SLP_S3_MIN_ASSERT_2S = 3, 333 } PmConfigSlpS3MinAssert; 334 335 enum { 336 SLP_S4_MIN_ASSERT_PCH = 0, 337 SLP_S4_MIN_ASSERT_1S = 1, 338 SLP_S4_MIN_ASSERT_2S = 2, 339 SLP_S4_MIN_ASSERT_3S = 3, 340 SLP_S4_MIN_ASSERT_4S = 4, 341 } PmConfigSlpS4MinAssert; 342 343 /* When deep Sx enabled: Must be greater than or equal to 344 all other minimum assertion widths. */ 345 enum { 346 SLP_SUS_MIN_ASSERT_0MS = 0, 347 SLP_SUS_MIN_ASSERT_500MS = 1, 348 SLP_SUS_MIN_ASSERT_1S = 2, 349 SLP_SUS_MIN_ASSERT_4S = 3, 350 } PmConfigSlpSusMinAssert; 351 352 enum { 353 SLP_A_MIN_ASSERT_0MS = 0, 354 SLP_A_MIN_ASSERT_4S = 1, 355 SLP_A_MIN_ASSERT_98MS = 2, 356 SLP_A_MIN_ASSERT_2S = 3, 357 } PmConfigSlpAMinAssert; 358 359 /* 360 * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, 361 * 1: Enabled 362 */ 363 bool PmConfigSlpStrchSusUp; 364 /* 365 * PCH power button override period. 366 * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s 367 */ 368 u8 PmConfigPwrBtnOverridePeriod; 369 370 /* 371 * PCH Pm Slp S0 Voltage Margining Enable 372 * Indicates platform supports VCCPrim_Core Voltage Margining 373 * in SLP_S0# asserted state. 374 */ 375 bool PchPmSlpS0VmEnable; 376 377 enum { 378 RESET_POWER_CYCLE_DEFAULT = 0, 379 RESET_POWER_CYCLE_1S = 1, 380 RESET_POWER_CYCLE_2S = 2, 381 RESET_POWER_CYCLE_3S = 3, 382 RESET_POWER_CYCLE_4S = 4, 383 } PmConfigPwrCycDur; 384 385 enum serirq_mode serirq_mode; 386 387 enum { 388 SERIAL_IRQ_FRAME_PULSE_4CLK = 0, 389 SERIAL_IRQ_FRAME_PULSE_6CLK = 1, 390 SERIAL_IRQ_FRAME_PULSE_8CLK = 2, 391 } SerialIrqConfigStartFramePulse; 392 393 /* 394 * VrConfig Settings for 5 domains 395 * 0 = System Agent, 1 = IA Core, 2 = Ring, 396 * 3 = GT unsliced, 4 = GT sliced 397 */ 398 struct vr_config domain_vr_config[NUM_VR_DOMAINS]; 399 400 /* 401 * Enable VR specific mailbox command 402 * 000b - Don't Send any VR command 403 * 001b - VR command specifically for the MPS IMPV8 VR will be sent 404 * 010b - VR specific command sent for PS4 exit issue 405 * 011b - VR specific command sent for both MPS IMPV8 & PS4 exit issue 406 */ 407 u8 SendVrMbxCmd; 408 409 /* Enable/Disable host reads to PMC XRAM registers */ 410 bool PchPmPmcReadDisable; 411 412 /* 413 * Use SD card detect GPIO with default config: 414 * - Edge triggered 415 * - No internal pull 416 * - Active both (high + low) 417 * - Can wake device from D3 418 * - 100ms debounce timeout 419 * 420 * GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000, 421 * "\\_SB.PCI0.GPIO", 0, ResourceConsumer) 422 * { sdcard_cd_gpio } 423 */ 424 unsigned int sdcard_cd_gpio; 425 426 /* Wake Enable Bitmap for USB2 ports */ 427 u16 usb2_wake_enable_bitmap; 428 429 /* Wake Enable Bitmap for USB3 ports */ 430 u8 usb3_wake_enable_bitmap; 431 432 /* 433 * Acoustic Noise Mitigation 434 * 0b - Disable 435 * 1b - Enable noise mitigation 436 */ 437 bool AcousticNoiseMitigation; 438 439 /* 440 * Disable Fast Package C-state ramping 441 * Need to set AcousticNoiseMitigation = '1' first 442 * 0b - Enabled 443 * 1b - Disabled 444 */ 445 bool FastPkgCRampDisableIa; 446 bool FastPkgCRampDisableGt; 447 bool FastPkgCRampDisableSa; 448 449 /* 450 * Adjust the VR slew rates 451 * Need to set AcousticNoiseMitigation = '1' first 452 * 000b - Fast/2 453 * 001b - Fast/4 454 * 010b - Fast/8 455 * 011b - Fast/16 456 */ 457 u8 SlowSlewRateForIa; 458 u8 SlowSlewRateForGt; 459 u8 SlowSlewRateForSa; 460 461 /* Enable/Disable EIST 462 * 1b - Enabled 463 * 0b - Disabled 464 */ 465 bool eist_enable; 466 467 /* 468 * Activates VR mailbox command for Intersil VR C-state issues. 469 * 0 - no mailbox command sent. 470 * 1 - VR mailbox command sent for IA/GT rails only. 471 * 2 - VR mailbox command sent for IA/GT/SA rails. 472 */ 473 u8 IslVrCmd; 474 475 /* i915 struct for GMA backlight control */ 476 struct i915_gpu_controller_info gfx; 477 }; 478 479 typedef struct soc_intel_skylake_config config_t; 480 481 #endif 482