1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* 4 * These definitions are used to describe PCIe bifurcation and display physical 5 * connector types connected to the SOC. 6 */ 7 8 #ifndef __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ 9 #define __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ 10 11 /* Engine descriptor type */ 12 typedef enum { 13 UNUSED_ENGINE = 0x00, // Unused descriptor 14 PCIE_ENGINE = 0x01, // PCIe port 15 USB_ENGINE = 0x02, // USB port 16 SATA_ENGINE = 0x03, // SATA 17 DP_ENGINE = 0x08, // Digital Display 18 ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe) 19 MAX_ENGINE // Max engine type for boundary check. 20 } dxio_engine_type; 21 22 /* PCIe link capability/speed */ 23 typedef enum { 24 GEN_MAX = 0, // Maximum supported 25 GEN1, 26 GEN2, 27 GEN3, 28 GEN_INVALID // Max Gen for boundary check 29 } dxio_link_speed_cap; 30 31 /* Upstream Auto Speed Change Allowed */ 32 typedef enum { 33 SPDC_DEFAULT = 0, // Enabled for Gen2 and Gen3 34 SPDC_DISABLED, 35 SPDC_ENABLED, 36 SPDC_INVALID 37 } dxio_upstream_auto_speed_change; 38 39 /* SATA ChannelType initialization */ 40 typedef enum { 41 SATA_CHANNEL_OTHER = 0, // Default Channel Type 42 SATA_CHANNEL_SHORT, // Short Trace Channel Type 43 SATA_CHANNEL_LONG // Long Trace Channel Type 44 } dxio_sata_channel_type; 45 46 /* CLKREQ for PCIe type descriptors */ 47 enum cpm_clk_req { 48 CLK_DISABLE = 0x00, 49 CLK_REQ0, 50 CLK_REQ1, 51 CLK_REQ2, 52 CLK_REQ3, 53 CLK_REQ4, 54 CLK_REQ5, 55 CLK_REQ6, 56 CLK_REQ7, 57 CLK_REQ8, 58 CLK_REQGFX = 0x0c, 59 CLK_ENABLE = 0xff, 60 }; 61 62 /* PCIe link ASPM initialization */ 63 typedef enum { 64 ASPM_DISABLED = 0, // Disabled 65 ASPM_L0s, // PCIe L0s link state 66 ASPM_L1, // PCIe L1 link state 67 ASPM_L0sL1, // PCIe L0s & L1 link state 68 ASPM_MAX // Not valid value, used to verify input 69 } dxio_aspm_type; 70 71 /* PCIe link hotplug */ 72 enum dxio_link_hotplug_type { 73 HOTPLUG_DISABLED = 0, 74 HOTPLUG_BASIC, 75 HOTPLUG_SERVER, 76 HOTPLUG_ENHANCED, 77 HOTPLUG_INBOARD, 78 HOTPLUG_SERVER_SSD, 79 }; 80 81 /* DDI Aux channel */ 82 typedef enum { 83 AUX1 = 0, 84 AUX2, 85 AUX3, 86 AUX4, 87 AUX5, 88 AUX6, 89 AUX_MAX // Not valid value, used to verify input 90 } ddi_aux_type; 91 92 /* DDI Hdp Index */ 93 typedef enum { 94 HDP1 = 0, 95 HDP2, 96 HDP3, 97 HDP4, 98 HDP5, 99 HDP6, 100 HDP_MAX // Not valid value, used to verify input 101 } ddi_hdp_type; 102 103 /* DDI display connector type */ 104 typedef enum { 105 DP = 0, // DP 106 EDP, // eDP 107 SINGLE_LINK_DVI, // Single Link DVI-D 108 DUAL_LINK_DVI, // Dual Link DVI-D 109 HDMI, // HDMI 110 DP_TO_VGA, // DP-to-VGA 111 DP_TO_LVDS, // DP-to-LVDS 112 NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA 113 SINGLE_LINK_DVI_I, // Single Link DVI-I 114 CRT, // CRT (VGA) 115 LVDS, // LVDS 116 EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init 117 EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init 118 AUTO_DETECT, // VBIOS auto detect connector type 119 UNUSED_TYPE, // UnusedType 120 MAX_CONNECTOR_TYPE // Not valid value, used to verify input 121 } ddi_connector_type; 122 123 /* DDI Descriptor: used for configuring display outputs */ 124 typedef struct __packed { 125 uint8_t connector_type; 126 uint8_t aux_index; 127 uint8_t hdp_index; 128 uint8_t reserved; 129 } fsp_ddi_descriptor; 130 131 /* 132 * Picasso DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines, configure 133 * bifurcation and other settings. Beware that the lane numbers in here are the logical and not 134 * the physical lane numbers! 135 * 136 * Picasso DXIO lane mapping: 137 * 138 * physical | logical | protocol 139 * ---------|---------|----------- 140 * GFX[7:0] | [15:8] | PCIe 141 * GPP[3:0] | [7:4] | PCIe 142 * GPP[5:4] | [1:0] | PCIe, XGBE 143 * GPP[7:6] | [3:2] | PCIe, SATA 144 * 145 * Picasso supports up to 7 PCIe ports. The 8 GFX PCIe lanes can either be used as an x8 port 146 * or split into two x4 ports. The GPP general purpose lanes can be used as PCIe x4, x2 and x1 147 * ports. The ports can only start at logical lane numbers that are integer multiples of the 148 * lane width, so for example an x4 port can only start with the logical lane 0, 4, 8 or 12. 149 * Different ports mustn't overlap or be assigned to the same lane(s). Within ports with the 150 * same width the one with a higher start logical lane number needs to be assigned to a higher 151 * PCIe root port number; ports of the same size don't have to be assigned to consecutive PCIe 152 * root ports though. 153 * 154 * Dali only supports up to 5 PCIe ports and has less DXIO connectivity than Picasso: 155 * 156 * physical | logical | protocol 157 * ---------|---------|----------- 158 * GFX[3:0] | [11:8] | PCIe 159 * GPP[1:0] | [5:4] | PCIe 160 * GPP[5:4] | [1:0] | PCIe, XGBE 161 * GPP[7:6] | [3:2] | SATA 162 * 163 * Pollock has even less DXIO lanes and the mapping of GPP lane numbers to the logical lane 164 * numbers differs to Picasso/Dali: 165 * 166 * physical | logical | protocol 167 * ---------|---------|---------- 168 * GPP[1:0] | [1:0] | PCIe 169 * GPP[3:2] | [5:4] | PCIe 170 */ 171 typedef struct __packed { 172 uint8_t engine_type; // See dxio_engine_type 173 uint8_t start_logical_lane; // Start lane of the pci device 174 uint8_t end_logical_lane; // End lane of the pci device 175 uint8_t gpio_group_id; // Currently unused by FSP 176 uint32_t port_present :1; // Should be TRUE if train link 177 uint32_t reserved_3 :7; 178 uint32_t device_number :5; // Desired root port device number 179 uint32_t function_number :3; // Desired root port function number 180 uint32_t link_speed_capability :2; // See dxio_link_speed_cap 181 uint32_t auto_spd_change :2; // See dxio_upstream_auto_speed_change 182 uint32_t eq_preset :4; // Gen3 equalization preset 183 uint32_t link_aspm :2; // See dxio_aspm_type 184 uint32_t link_aspm_L1_1 :1; // En/Dis root port capabilities for L1.1 185 uint32_t link_aspm_L1_2 :1; // En/Dis root port capabilities for L1.2 186 uint32_t clk_req :4; // See cpm_clk_req 187 uint8_t link_hotplug; // See dxio_link_hotplug_type 188 uint8_t slot_power_limit; // Currently unused by FSP 189 uint32_t slot_power_limit_scale :2; // Currently unused by FSP 190 uint32_t reserved_4 :6; 191 uint32_t link_compliance_mode :1; // Currently unused by FSP 192 uint32_t link_safe_mode :1; // Currently unused by FSP 193 uint32_t sb_link :1; // Currently unused by FSP 194 uint32_t clk_pm_support :1; // Currently unused by FSP 195 uint32_t channel_type :3; // See dxio_sata_channel_type 196 uint32_t turn_off_unused_lanes :1; // Power down lanes if device not present 197 uint8_t reserved[4]; 198 } fsp_dxio_descriptor; 199 200 #endif /* __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ */ 201