1 /* SPDX-License-Identifier: BSD-3-Clause */
2
3 //-----------------------------------------------------------------------------
4 // Include files
5 //-----------------------------------------------------------------------------
6 #include "dramc_common.h"
7 #include "dramc_int_global.h"
8 #include "x_hal_io.h"
9
10 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
11 #include "dramc_top.h"
12 #ifndef MT6779_FPGA
13 #endif
14 #endif
15
16
17 //-----------------------------------------------------------------------------
18 // Global variables
19 //-----------------------------------------------------------------------------
20
21 #if ENABLE_EYESCAN_GRAPH || defined(FOR_HQA_REPORT_USED)
22 EXTERN const U16 gRXVref_Voltage_Table_0P5V_T[EYESCAN_RX_VREF_RANGE_END];
23 EXTERN const U16 gRXVref_Voltage_Table_0P5V_UT[EYESCAN_RX_VREF_RANGE_END];
24 EXTERN const U16 gRXVref_Voltage_Table_0P3V_UT[EYESCAN_RX_VREF_RANGE_END];
25 EXTERN const U16 gRXVref_Voltage_Table_0P6V_T[EYESCAN_RX_VREF_RANGE_END];
26 EXTERN const U16 gRXVref_Voltage_Table_0P6V_UT[EYESCAN_RX_VREF_RANGE_END];
27 EXTERN const U16 gVref_Voltage_Table_LP4X[VREF_RANGE_MAX][VREF_VOLTAGE_TABLE_NUM_LP4];
28 EXTERN const U16 gVref_Voltage_Table_LP4[VREF_RANGE_MAX][VREF_VOLTAGE_TABLE_NUM_LP4];
29 EXTERN const U16 gVref_Voltage_Table_LP5[VREF_VOLTAGE_TABLE_NUM_LP5];
30 #endif
31
32 #if __ETT__
33 #define __NOBITS_SECTION__(x)
34 #endif
35
36 #if ENABLE_EYESCAN_GRAPH || defined(FOR_HQA_REPORT_USED)
37 const U16 gRXVref_Voltage_Table_0P5V_T[EYESCAN_RX_VREF_RANGE_END] = {
38 3990,4140,4290,4440,4590,4740,4890,5030,5180,5330,
39 5480,5630,5770,5920,6070,6220,6480,6630,6780,6920,
40 7070,7220,7370,7520,7670,7820,7970,8110,8260,8410,
41 8560,8710,8950,9110,9250,9400,9550,9700,9850,10000,
42 10150,10300,10450,10590,10740,10890,11040,11190,11430,11590,
43 11740,11890,12040,12190,12340,12500,12650,12800,12950,13100,
44 13260,13410,13560,13710,13950,14110,14260,14410,14560,14710,
45 14860,15010,15170,15320,15470,15620,15770,15920,16080,16230,
46 16470,16620,16770,16920,17070,17220,17360,17510,17670,17820,
47 17960,18110,18260,18410,18560,18710,18950,19100,19250,19400,
48 19550,19700,19850,20000,20150,20300,20450,20600,20750,20900,
49 21040,21190,21430,21580,21730,21880,22030,22180,22330,22480,
50 22630,22780,22930,23080,23230,23380,23530,23680
51 };
52 const U16 gRXVref_Voltage_Table_0P5V_UT[EYESCAN_RX_VREF_RANGE_END] = {
53 7890,8190,8490,8780,9080,9380,9670,9970,10270,10560,
54 10860,11160,11450,11750,12050,12350,12830,13120,13420,13720,
55 14010,14310,14610,14900,15200,15500,15800,16090,16390,16680,
56 16980,17280,17760,18060,18350,18650,18940,19240,19540,19830,
57 20130,20430,20720,21020,21320,21610,21910,22210,22690,22990,
58 23290,23590,23900,24200,24500,24800,25100,25410,25710,26010,
59 26310,26610,26920,27220,27700,28000,28300,28610,28910,29210,
60 29510,29810,30110,30420,30720,31020,31320,31620,31920,32220,
61 32700,32990,33290,33590,33880,34180,34480,34770,35070,35370,
62 35670,35970,36260,36560,36860,37150,37630,37930,38220,38520,
63 38820,39110,39410,39710,40010,40300,40600,40900,41190,41490,
64 41790,42090,42560,42860,43150,43450,43750,44040,44340,44630,
65 44930,45230,45530,45820,46120,46420,46710,47010
66 };
67 const U16 gRXVref_Voltage_Table_0P3V_UT[EYESCAN_RX_VREF_RANGE_END] = {
68 4720,4900,5080,5250,5430,5600,5780,5950,6130,6310,
69 6480,6660,6840,7010,7190,7370,7650,7830,8010,8180,
70 8360,8540,8710,8890,9070,9240,9420,9590,9770,9950,
71 10120,10300,10580,10760,10940,11110,11290,11470,11640,11820,
72 12000,12170,12350,12530,12700,12880,13050,13230,13520,13700,
73 13880,14060,14240,14420,14600,14780,14960,15140,15320,15500,
74 15680,15860,16030,16220,16500,16680,16860,17040,17220,17400,
75 17580,17760,17940,18120,18300,18480,18660,18840,19010,19190,
76 19480,19660,19830,20010,20190,20360,20540,20720,20900,21070,
77 21250,21430,21600,21780,21960,22130,22420,22600,22780,22950,
78 23130,23310,23480,23660,23840,24010,24190,24370,24540,24720,
79 24900,25080,25360,25540,25710,25890,26070,26240,26420,26600,
80 26780,26950,27130,27310,27480,27660,27840,28020
81 };
82 const U16 gRXVref_Voltage_Table_0P6V_T[EYESCAN_RX_VREF_RANGE_END] = {
83 4790,4970,5150,5330,5500,5680,5860,6040,6220,6390,
84 6570,6750,6930,7110,7290,7470,7770,7950,8130,8310,
85 8490,8660,8840,9020,9200,9380,9560,9740,9920,10100,
86 10280,10460,10750,10930,11110,11280,11460,11640,11820,12000,
87 12180,12360,12540,12720,12900,13080,13250,13430,13720,13910,
88 14090,14270,14450,14640,14820,15000,15180,15370,15550,15730,
89 15910,16100,16280,16460,16750,16940,17120,17300,17480,17660,
90 17850,18030,18210,18390,18580,18760,18940,19120,19300,19490,
91 19780,19960,20140,20310,20490,20670,20850,21030,21210,21390,
92 21570,21750,21930,22110,22290,22470,22760,22940,23120,23300,
93 23480,23650,23830,24010,24190,24370,24550,24730,24910,25090,
94 25270,25450,25740,25920,26100,26280,26450,26630,26810,26990,
95 27170,27350,27530,27710,27890,28070,28250,28430
96 };
97 const U16 gRXVref_Voltage_Table_0P6V_UT[EYESCAN_RX_VREF_RANGE_END] = {
98 9470,9830,10190,10540,10900,11260,11610,11970,12330,12680,
99 13040,13400,13750,14110,14460,14820,15400,15760,16120,16470,
100 16830,17180,17540,17890,18250,18610,18970,19320,19680,20040,
101 20390,20750,21330,21680,22040,22400,22750,23110,23460,23820,
102 24180,24530,24890,25250,25600,25960,26310,26670,27250,27610,
103 27970,28330,28700,29060,29420,29780,30150,30520,30880,31240,
104 31600,31960,32330,32690,33270,33630,33990,34350,34710,35080,
105 35440,35800,36160,36530,36890,37250,37610,37970,38330,38700,
106 39270,39630,39980,40340,40690,41050,41410,41760,42120,42480,
107 42840,43190,43550,43900,44260,44620,45190,45550,45910,46260,
108 46620,46970,47330,47680,48040,48400,48760,49110,49470,49820,
109 50180,50540,51120,51480,51830,52190,52540,52890,53250,53600,
110 53960,54320,54670,55030,55380,55740,56090,56450
111 };
112 const U16 gRXVref_Voltage_Table_LP4[EYESCAN_RX_VREF_RANGE_END+1]={
113 #if __Petrus_TO_BE_PORTING__
114 (364+821)/2,
115 (1202+1621)/2,
116 (2039+2420)/2,
117 (2875+3219)/2,
118 (3711+4018)/2,
119 (4548+4817)/2,
120 (5384+5615)/2,
121 (6221+6414)/2,
122 (7057+7213)/2,
123 (7893+8012)/2,
124 (8727+8811)/2,
125 (9554+9618)/2,
126 (10380+10430)/2,
127 (11200+11250)/2,
128 (12010+12080)/2,
129 (12810+12910)/2,
130 (13120+13540)/2,
131 (13830+14210)/2,
132 (14530+14870)/2,
133 (15240+15540)/2,
134 (15950+16210)/2,
135 (16650+16880)/2,
136 (17360+17550)/2,
137 (18070+18220)/2,
138 (18770+18890)/2,
139 (19470+19560)/2,
140 (20160+20240)/2,
141 (20850+20930)/2,
142 (21520+21610)/2,
143 (22190+22310)/2,
144 (22860+23010)/2,
145 (23540+23720)/2,
146 (23330+23770)/2,
147 (24040+24430)/2,
148 (24740+25090)/2,
149 (25450+25740)/2,
150 (26150+26400)/2,
151 (26860+27060)/2,
152 (27560+27730)/2,
153 (28240+28400)/2,
154 (28920+29070)/2,
155 (29580+29730)/2,
156 (30230+30410)/2,
157 (30890+31100)/2,
158 (31540+31790)/2,
159 (32190+32490)/2,
160 (32840+33200)/2,
161 (33500+33900)/2,
162 (33540+34030)/2,
163 (34250+34660)/2,
164 (34950+35300)/2,
165 (35650+35950)/2,
166 (36360+36600)/2,
167 (37060+37250)/2,
168 (37760+37900)/2,
169 (38420+38560)/2,
170 (39050+39230)/2,
171 (39680+39900)/2,
172 (40310+40590)/2,
173 (40940+41280)/2,
174 (41570+41990)/2,
175 (42190+42690)/2,
176 (42820+43400)/2,
177 (43450+44100)/2,
178 #endif
179 };
180
181 const U16 gVref_Voltage_Table_LP4X[VREF_RANGE_MAX][VREF_VOLTAGE_TABLE_NUM_LP4] = {
182 {1500, 1560, 1620, 1680, 1740, 1800, 1860, 1920, 1980, 2040, 2100, 2160, 2220, 2280, 2340, 2400, 2460, 2510, 2570, 2630, 2690, 2750, 2810, 2870, 2930, 2990, 3050, 3110, 3170, 3230, 3290, 3350, 3410, 3470, 3530, 3590, 3650, 3710, 3770, 3830, 3890, 3950, 4010, 4070, 4130, 4190, 4250, 4310, 4370, 4430, 4490},
183 {3290, 3350, 3410, 3470, 3530, 3590, 3650, 3710, 3770, 3830, 3890, 3950, 4010, 4070, 4130, 4190, 4250, 4310, 4370, 4430, 4490, 4550, 4610, 4670, 4730, 4790, 4850, 4910, 4970, 5030, 5090, 5150, 5210, 5270, 5330, 5390, 5450, 5510, 5570, 5630, 5690, 5750, 5810, 5870, 5930, 5990, 6050, 6110, 6170, 6230, 6290}
184 };
185 const U16 gVref_Voltage_Table_LP4[VREF_RANGE_MAX][VREF_VOLTAGE_TABLE_NUM_LP4] = {
186 {1000, 1040, 1080, 1120, 1160, 1200, 1240, 1280, 1320, 1360, 1400, 1440, 1480, 1520, 1560, 1600, 1640, 1680, 1720, 1760, 1800, 1840, 1880, 1920, 1960, 2000, 2040, 2080, 2120, 2160, 2200, 2240, 2280, 2320, 2360, 2400, 2440, 2480, 2520, 2560, 2600, 2640, 2680, 2720, 2760, 2800, 2840, 2880, 2920, 2960, 3000},
187 {2200, 2240, 2280, 2320, 2360, 2400, 2440, 2480, 2520, 2560, 2600, 2640, 2680, 2720, 2760, 2800, 2840, 2880, 2920, 2960, 3000, 3040, 3080, 3120, 3160, 3200, 3240, 3280, 3320, 3360, 3400, 3440, 3480, 3520, 3560, 3600, 3640, 3680, 3720, 3760, 3880, 3840, 3880, 3920, 3960, 4000, 4040, 4080, 4120, 4160, 4200}
188 };
189 const U16 gVref_Voltage_Table_LP5[VREF_VOLTAGE_TABLE_NUM_LP5] = {
190 1000,1050,1100,1150,1200,1250,1300,1350,1400,1450,
191 1500,1550,1600,1650,1700,1750,1800,1850,1900,1950,
192 2000,2050,2100,2150,2200,2250,2300,2350,2400,2450,
193 2500,2550,2600,2650,2700,2750,2800,2850,2900,2950,
194 3000,3050,3100,3150,3200,3250,3300,3350,3400,3450,
195 3500,3550,3600,3650,3700,3750,3800,3850,3900,3950,
196 4000,4050,4100,4150,4200,4250,4300,4350,4400,4450,
197 4500,4550,4600,4650,4700,4750,4800,4850,4900,4950,
198 5000,5050,5100,5150,5200,5250,5300,5350,5400,5450,
199 5500,5550,5600,5650,5700,5750,5800,5850,5900,5950,
200 6000,6050,6100,6150,6200,6250,6300,6350,6400,6450,
201 6500,6550,6600,6650,6700,6750,6800,6850,6900,6950,
202 7000,7050,7100,7150,7200,7250,7300,7350
203 };
204 #endif
205
206
207 #if ENABLE_EYESCAN_GRAPH
208 __NOBITS_SECTION__(.gEyeScan_Min) S16 gEyeScan_Min[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH][EYESCAN_BROKEN_NUM];
209 __NOBITS_SECTION__(.gEyeScan_Max) S16 gEyeScan_Max[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH][EYESCAN_BROKEN_NUM];
210 U16 gEyeScan_CaliDelay[DQS_BYTE_NUMBER];
211 S16 gEyeScan_MinMax_store_delay[DQS_BYTE_NUMBER];
212 __NOBITS_SECTION__(.gEyeScan_WinSize) U16 gEyeScan_WinSize[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH];
213 S16 gEyeScan_DelayCellPI[DQ_DATA_WIDTH];
214 U16 gEyeScan_ContinueVrefHeight[DQ_DATA_WIDTH];
215 U16 gEyeScan_TotalPassCount[DQ_DATA_WIDTH];
216 #endif
217
HQA_LOG_Parsing_Freq(void)218 const char* HQA_LOG_Parsing_Freq(void)
219 {
220 if (gHQA_Test_Freq_Vcore_Level != 0)
221 {
222 return (gHQA_Test_Freq_Vcore_Level == 1? "_L" : "_H");
223 }
224
225 return " ";
226 }
HQA_LOG_Print_Prefix_String(DRAMC_CTX_T * p)227 void HQA_LOG_Print_Prefix_String(DRAMC_CTX_T *p)
228 {
229 mcSHOW_DBG_MSG(("[HQALOG] %d%s ", p->frequency * 2, HQA_LOG_Parsing_Freq() ));
230 }
231
HQA_LOG_Print_Freq_String(DRAMC_CTX_T * p)232 void HQA_LOG_Print_Freq_String(DRAMC_CTX_T *p)
233 {
234 #if VENDER_JV_LOG
235 mcSHOW_EYESCAN_MSG(("%d%s ", p->frequency * 2, HQA_LOG_Parsing_Freq() ));
236 #else
237 mcSHOW_DBG_MSG(("%d%s ", p->frequency * 2, HQA_LOG_Parsing_Freq() ));
238 #endif
239 }
240
241 #ifdef FOR_HQA_TEST_USED
EYESCAN_LOG_Print_Prefix_String(void)242 static void EYESCAN_LOG_Print_Prefix_String(void)
243 {
244 mcSHOW_DBG_MSG(("[EYESCAN_LOG] "));
245 }
246
print_EYESCAN_LOG_type(U8 print_type)247 static const char* print_EYESCAN_LOG_type(U8 print_type)
248 {
249 switch (print_type)
250 {
251 case EYESCAN_TYPE_CBT: return "CBT";
252 case EYESCAN_TYPE_RX: return "RX";
253 default:
254 case EYESCAN_TYPE_TX: return "TX";
255 }
256 }
257
258
259
HQA_measure_message_reset_all_data(DRAMC_CTX_T * p)260 void HQA_measure_message_reset_all_data(DRAMC_CTX_T *p)
261 {
262 U32 uiCA, u1BitIdx, u1ByteIdx, u1RankIdx, u1ChannelIdx;
263
264 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < CHANNEL_NUM; u1ChannelIdx++)
265 {
266 for (u1RankIdx = RANK_0; u1RankIdx < RANK_MAX; u1RankIdx++)
267 {
268 for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
269 {
270 gFinalRXPerbitWin[u1ChannelIdx][u1RankIdx][u1BitIdx] = 0;
271 gFinalTXPerbitWin[u1ChannelIdx][u1RankIdx][u1BitIdx] = 0;
272 }
273 }
274 }
275 }
276
print_HQA_SLT_BIN_message(DRAMC_CTX_T * p)277 void print_HQA_SLT_BIN_message(DRAMC_CTX_T *p)
278 {
279 S8 u1ShuIdx;
280 S8 ucstatus;
281
282 if (gHQALog_flag == 1)
283 {
284 ucstatus = 0;
285 for (u1ShuIdx = DRAM_DFS_SRAM_MAX - 1; u1ShuIdx >= SRAM_SHU0; u1ShuIdx--)
286 {
287 if (gHQALog_SLT_BIN[u1ShuIdx] != 0)
288 {
289 mcSHOW_DBG_MSG(("SLT_BIN%d\n", gHQALog_SLT_BIN[u1ShuIdx]));
290 ucstatus = 1;
291 }
292 }
293
294 if (ucstatus==0)
295 {
296 mcSHOW_DBG_MSG(("SLT_BIN1\n"));
297 }
298 }
299 }
300
301 #if defined(FOR_HQA_REPORT_USED)
print_HQA_message_before_CalibrationAllChannel(DRAMC_CTX_T * p)302 void print_HQA_message_before_CalibrationAllChannel(DRAMC_CTX_T *p)
303 {
304 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DBI_W_ONOFF %d\n", p->DBI_W_onoff[p->dram_fsp]));
305 }
306 #endif
307
308 #ifdef RELEASE
309 #undef mcSHOW_DBG_MSG
310 #define mcSHOW_DBG_MSG(_x_) opt_print _x_
311 #endif
print_HQA_measure_message(DRAMC_CTX_T * p)312 void print_HQA_measure_message(DRAMC_CTX_T *p)
313 {
314 U32 uiCA, u1BitIdx, u1ByteIdx, u1RankIdx, u1ChannelIdx;
315 U32 min_ca_value[CHANNEL_NUM][RANK_MAX], min_ca_bit[CHANNEL_NUM][RANK_MAX];
316 U32 min_rx_value[CHANNEL_NUM][RANK_MAX], min_tx_value[CHANNEL_NUM][RANK_MAX];
317 U32 min_RX_DQ_bit[CHANNEL_NUM][RANK_MAX], min_TX_DQ_bit[CHANNEL_NUM][RANK_MAX];
318 U8 SRAMIdx, local_channel_num = CHANNEL_NUM, shuffle_index;
319 U8 print_imp_option[2] = {FALSE, FALSE};
320 int i;
321 U32 read_voltage_value;
322
323 mcSHOW_DBG_MSG(("\n\n\n[HQA] information for measurement, "));
324 mcSHOW_DBG_MSG(("\tDram Data rate = ")); HQA_LOG_Print_Freq_String(p); mcSHOW_DBG_MSG(("\n"));
325 //mcDUMP_REG_MSG(("\n\n\n[HQA] information for measurement, "));
326 //mcDUMP_REG_MSG(("\tDram Data rate = "));
327 //mcDUMP_REG_MSG(("%d%s ", p->frequency * 2, HQA_LOG_Parsing_Freq() ));
328 //mcDUMP_REG_MSG(("\n"));
329 vPrintCalibrationBasicInfo(p);
330 HQA_LOG_Print_Prefix_String(p);
331 mcSHOW_DBG_MSG(("Frequency = %u\n", DDRPhyGetRealFreq(p)));
332
333
334 if (gHQALog_flag == 1)
335 {
336 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("ETT_Commit_Version = %s\n", _COMMIT_VERSION_));
337 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("ETT_Commit_Date = %s\n", _COMMIT_DATE_));
338 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Frequency = %d\n", DDRPhyGetRealFreq(p)));
339 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("fsp = %d\n", p->dram_fsp));
340 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("odt_onoff = %d\n", p->odt_onoff));
341 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("byte_mode = %d\n", p->dram_cbt_mode[p->rank]));
342 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DivMode = %d\n", vGet_Div_Mode(p)));
343 }
344 SRAMIdx = vGet_Current_SRAMIdx(p);
345
346 if (u1IsLP4Family(p->dram_type))
347 {
348 local_channel_num = p->support_channel_num;
349 }
350
351 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
352 {
353 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
354 {
355 min_ca_value[u1ChannelIdx][u1RankIdx] = 0xffff;
356 min_rx_value[u1ChannelIdx][u1RankIdx] = 0xffff;
357 min_tx_value[u1ChannelIdx][u1RankIdx] = 0xffff;
358 min_RX_DQ_bit[u1ChannelIdx][u1RankIdx] = 0xffff;
359 min_TX_DQ_bit[u1ChannelIdx][u1RankIdx] = 0xffff;
360
361 for (uiCA = 0; uiCA < ((u1IsLP4Family(p->dram_type) == 1)? CATRAINING_NUM_LP4: CATRAINING_NUM_LP5); uiCA++)
362 {
363 if (gFinalCBTCA[u1ChannelIdx][u1RankIdx][uiCA] < min_ca_value[u1ChannelIdx][u1RankIdx])
364 {
365 min_ca_value[u1ChannelIdx][u1RankIdx] = gFinalCBTCA[u1ChannelIdx][u1RankIdx][uiCA];
366 min_ca_bit[u1ChannelIdx][u1RankIdx] = uiCA;
367 }
368 }
369
370 for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
371 {
372 if (gFinalRXPerbitWin[u1ChannelIdx][u1RankIdx][u1BitIdx] < min_rx_value[u1ChannelIdx][u1RankIdx])
373 {
374 min_rx_value[u1ChannelIdx][u1RankIdx] = gFinalRXPerbitWin[u1ChannelIdx][u1RankIdx][u1BitIdx];
375 min_RX_DQ_bit[u1ChannelIdx][u1RankIdx] = u1BitIdx;
376 }
377 if (gFinalTXPerbitWin[u1ChannelIdx][u1RankIdx][u1BitIdx] < min_tx_value[u1ChannelIdx][u1RankIdx])
378 {
379 min_tx_value[u1ChannelIdx][u1RankIdx] = gFinalTXPerbitWin[u1ChannelIdx][u1RankIdx][u1BitIdx];
380 min_TX_DQ_bit[u1ChannelIdx][u1RankIdx] = u1BitIdx;
381 }
382 }
383 }
384 }
385
386
387 if (p->support_rank_num == RANK_DUAL)
388 {
389
390 if (!u1IsLP4Family(p->dram_type))
391 {
392 #ifndef LP3_DUAL_RANK_RX_K
393 min_rx_value[0][1] = min_rx_value[0][0];
394 min_RX_DQ_bit[0][1] = min_RX_DQ_bit[0][0];
395 #endif
396
397 #ifndef LP3_DUAL_RANK_TX_K
398 min_tx_value[0][1] = min_tx_value[0][0];
399 gFinalTXPerbitWin_min_max[0][1] = gFinalTXPerbitWin_min_max[0][0];
400 min_TX_DQ_bit[0][1] = min_TX_DQ_bit[0][0];
401 #endif
402
403 #if 0
404 gFinalTXPerbitWin_min_margin[0][1] = gFinalTXPerbitWin_min_margin[0][0];
405 gFinalTXPerbitWin_min_margin_bit[0][1] = gFinalTXPerbitWin_min_margin_bit[0][0];
406 #endif
407 }
408 }
409
410
411 #if defined(DRAM_HQA)
412 mcSHOW_DBG_MSG(("[Read Voltage]\n"));
413 read_voltage_value = vGetVoltage(p, 0);
414 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vcore_HQA = %d\n", read_voltage_value));
415
416 if (u1IsLP4Family(p->dram_type)) {
417
418 read_voltage_value = vGetVoltage(p, 1);
419 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vdram_HQA = %d\n", read_voltage_value));
420 read_voltage_value = vGetVoltage(p, 2);
421 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vddq_HQA = %d\n", read_voltage_value));
422 read_voltage_value = vGetVoltage(p, 3);
423 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vdd1_HQA = %d\n", read_voltage_value));
424 read_voltage_value = vGetVoltage(p, 4);
425 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vmddr_HQA = %d\n", read_voltage_value));
426 } else {
427
428 read_voltage_value = vGetVoltage(p, 1);
429 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vdram_HQA = %d\n", read_voltage_value));
430 }
431 mcSHOW_DBG_MSG(("\n"));
432 #endif
433
434 if (p->dram_type == TYPE_LPDDR4)
435 {
436 print_imp_option[1] = TRUE;
437 }
438 else if (p->dram_type == TYPE_LPDDR4X)
439 {
440 print_imp_option[0] = TRUE;
441 print_imp_option[1] = TRUE;
442 }
443 else
444 {
445
446 print_imp_option[0] = TRUE;
447 }
448
449 #ifdef FOR_HQA_REPORT_USED
450 if (gHQALog_flag == 1)
451 {
452 mcSHOW_DBG_MSG(("[Impedance Calibration]\n"));
453
454 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "Impedance freq_region=0 ", "DRVP", 0, gDramcImpedanceResult[0][DRVP], NULL);
455 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "Impedance freq_region=0 ", "DRVN", 0, gDramcImpedanceResult[0][DRVN], NULL);
456 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "Impedance freq_region=0 ", "ODTN", 0, gDramcImpedanceResult[0][ODTN], NULL);
457
458 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "Impedance freq_region=1 ", "DRVP", 0, gDramcImpedanceResult[1][DRVP], NULL);
459 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "Impedance freq_region=1 ", "DRVN", 0, gDramcImpedanceResult[1][DRVN], NULL);
460 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "Impedance freq_region=1 ", "ODTN", 0, gDramcImpedanceResult[1][ODTN], NULL);
461
462 mcSHOW_DBG_MSG(("\n"));
463 }
464 #endif
465
466
467
468
469
470 mcSHOW_DBG_MSG(("\n[Cmd Bus Training window]\n"));
471
472 if (u1IsLP4Family(p->dram_type))
473 {
474
475 mcSHOW_DBG_MSG(("VrefCA\n"));
476 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
477 {
478 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
479 {
480 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("VrefCA Channel%d "
481 "Rank%d %d\n",
482 u1ChannelIdx,
483 u1RankIdx,
484 gFinalCBTVrefCA[u1ChannelIdx][u1RankIdx]));
485 }
486 }
487 }
488
489 #if 0
490 if (p->femmc_Ready == 1 )
491 {
492 mcSHOW_DBG_MSG(("\n[Cmd Bus Training window bypass calibration]\n"));
493 }
494 else
495 #endif
496 {
497 mcSHOW_DBG_MSG(("CA_Window\n"));
498 #ifdef FOR_HQA_REPORT_USED
499 if (gHQALog_flag == 1)
500 {
501 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
502 {
503 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
504 {
505 HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "CA", "_Window", 0, min_ca_value[u1ChannelIdx][u1RankIdx], NULL);
506 HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "CA", "_Window_bit", 0, min_ca_bit[u1ChannelIdx][u1RankIdx], NULL);
507 }
508 }
509 mcSHOW_DBG_MSG(("\n"));
510 }
511 else
512 #endif
513 {
514 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
515 {
516 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
517 {
518 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("CA_Window Channel%d "
519 "Rank%d %d (bit %d)\n",
520 u1ChannelIdx,
521 u1RankIdx,
522 min_ca_value[u1ChannelIdx][u1RankIdx], min_ca_bit[u1ChannelIdx][u1RankIdx]));
523 }
524 }
525 }
526
527 mcSHOW_DBG_MSG(("CA Min Window(%%)\n"));
528 #ifdef FOR_HQA_REPORT_USED
529 if (gHQALog_flag == 1)
530 {
531 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
532 {
533 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
534 {
535 HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "CA", "_Window(%)", 0, ((min_ca_value[u1ChannelIdx][u1RankIdx] * 100 + (u1IsLP4Family(p->dram_type) == 1? 63: 31)) / (u1IsLP4Family(p->dram_type) == 1? 64: 32)), NULL);
536 HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT4, "CA", "_Window_PF", 0, 0, ((((min_ca_value[u1ChannelIdx][u1RankIdx] * 100 + (u1IsLP4Family(p->dram_type)==1?63:31)) / (u1IsLP4Family(p->dram_type)==1?64:32)) >= 30) ? "PASS" : "FAIL"));
537 }
538 }
539 mcSHOW_DBG_MSG(("\n"));
540 }
541 else
542 #endif
543 {
544 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
545 {
546 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
547 {
548 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("CA_Window(%%) Channel%d "
549 "Rank%d %d%% (%s)\n",
550 u1ChannelIdx,
551 u1RankIdx,
552 ((min_ca_value[u1ChannelIdx][u1RankIdx] * 100 + (u1IsLP4Family(p->dram_type) == 1? 63: 31)) / (u1IsLP4Family(p->dram_type) == 1? 64: 32)),
553 ((((min_ca_value[u1ChannelIdx][u1RankIdx] * 100 + (u1IsLP4Family(p->dram_type) == 1? 63: 31)) / (u1IsLP4Family(p->dram_type) == 1? 64: 32)) >= 30)? "PASS" : "FAIL")));
554 }
555 }
556 }
557 }
558 mcSHOW_DBG_MSG(("\n"));
559
560
561
562
563 mcSHOW_DBG_MSG(("\n[RX minimum per bit window]\n"));
564 mcSHOW_DBG_MSG(("Delaycell measurement(/100ps)\n"));
565
566 #if defined(FOR_HQA_REPORT_USED) && !defined(RELEASE) && (VENDER_JV_LOG == 0)
567 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("delaycell %d\n",
568 gHQALOG_RX_delay_cell_ps_075V));
569 #endif
570 #if defined(FOR_HQA_REPORT_USED)
571 if (gHQALog_flag == 1)
572 {
573 if ((gHQALOG_RX_delay_cell_ps_075V < 245) || (gHQALOG_RX_delay_cell_ps_075V > 300))
574 {
575 gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 2;
576 }
577 }
578 #endif
579
580
581 if (u1IsLP4Family(p->dram_type))
582 {
583 mcSHOW_DBG_MSG(("VrefRX\n"));
584 if (gRX_EYE_Scan_flag == 1)
585 {
586 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
587 {
588 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
589 {
590 for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
591 {
592 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("VrefRX Channel%d Rank%d Byte%d %d\n",
593 u1ChannelIdx,
594 u1RankIdx,
595 u1ByteIdx,
596 gFinalRXVrefDQ[u1ChannelIdx][u1RankIdx][u1ByteIdx]));
597 }
598 }
599 }
600 }
601 else
602 {
603 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
604 {
605 for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
606 {
607 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("VrefRX Channel%d Byte%d %d\n",
608 u1ChannelIdx,
609 u1ByteIdx,
610 gFinalRXVrefDQ[u1ChannelIdx][RANK_0][u1ByteIdx]));
611 }
612 }
613 }
614 }
615
616 #if 0//(SUPPORT_SAVE_TIME_FOR_CALIBRATION )
617 if (p->femmc_Ready == 1 && ( p->Bypass_RXWINDOW))
618 {
619 mcSHOW_DBG_MSG(("\n[RX minimum per bit window bypass calibration]\n"));
620 }
621 else
622 #endif
623 {
624
625 mcSHOW_DBG_MSG(("RX_Window\n"));
626 #ifdef FOR_HQA_REPORT_USED
627 if (gHQALog_flag == 1)
628 {
629 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
630 {
631 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
632 {
633 HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "RX", "_Window", 0, min_rx_value[u1ChannelIdx][u1RankIdx], NULL);
634 HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "RX", "_Window_bit", 0, min_RX_DQ_bit[u1ChannelIdx][u1RankIdx], NULL);
635 }
636 }
637 }
638 else
639 #endif
640 {
641 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
642 {
643 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
644 {
645 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("RX_Window Channel%d "
646 "Rank%d %d (bit %d)\n",
647 u1ChannelIdx,
648 u1RankIdx,
649 min_rx_value[u1ChannelIdx][u1RankIdx], min_RX_DQ_bit[u1ChannelIdx][u1RankIdx]));
650 }
651 }
652 }
653
654
655 mcSHOW_DBG_MSG(("RX Window(%%)\n"));
656 #ifdef FOR_HQA_REPORT_USED
657 if (gHQALog_flag == 1)
658 {
659 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
660 {
661 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
662 {
663 HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "RX", "_Window(%)", 0, ((min_rx_value[u1ChannelIdx][u1RankIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, NULL);
664 HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT4, "RX", "_Window_PF", 0, 0, (min_rx_value[u1ChannelIdx][u1RankIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) / 1000000 >= 40 ? "PASS" : "FAIL");
665
666 if ((((min_rx_value[u1ChannelIdx][u1RankIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000) < 55)
667 {
668 gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 4;
669 }
670 }
671 }
672 }
673 else
674 {
675 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
676 {
677 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
678 {
679 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("RX_Window(%%) Channel%d "
680 "Rank%d "
681 "%d/100ps (%d%%) (%s)\n",
682 u1ChannelIdx,
683 u1RankIdx,
684 min_rx_value[u1ChannelIdx][u1RankIdx] * gHQALOG_RX_delay_cell_ps_075V,
685 ((min_rx_value[u1ChannelIdx][u1RankIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000,
686 ((min_rx_value[u1ChannelIdx][u1RankIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000 >= 40? "PASS" : "FAIL"));
687 }
688 }
689 }
690 #endif
691 mcSHOW_DBG_MSG(("\n"));
692 }
693
694
695
696
697
698
699 mcSHOW_DBG_MSG(("\n[TX minimum per bit window]\n"));
700 if (u1IsLP4Family(p->dram_type))
701 {
702 if (Get_Vref_Calibration_OnOff(p) == VREF_CALI_ON)
703 {
704 mcSHOW_DBG_MSG(("VrefDQ Range : %d\n", (u1MR14Value[p->channel][p->rank][p->dram_fsp] >> 6) & 1));
705 mcSHOW_DBG_MSG(("VrefDQ\n"));
706 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
707 {
708 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
709 {
710 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("VrefDQ Channel%d "
711 "Rank%d %d\n",
712 u1ChannelIdx,
713 u1RankIdx,
714 gFinalTXVrefDQ[u1ChannelIdx][u1RankIdx]));
715 }
716 }
717 }
718 else
719 {
720 mcSHOW_DBG_MSG(("TX DQ Vref Scan : Disable\n"));
721 }
722 }
723 #if 0//(SUPPORT_SAVE_TIME_FOR_CALIBRATION )
724 if (p->femmc_Ready == 1 && (p->Bypass_TXWINDOW))
725 {
726 mcSHOW_DBG_MSG(("\n[TX minimum per bit window bypass calibration]\n"));
727 }
728 else
729 #endif
730 {
731
732 mcSHOW_DBG_MSG(("TX_Window\n"));
733 #ifdef FOR_HQA_REPORT_USED
734 if (gHQALog_flag == 1)
735 {
736 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
737 {
738 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
739 {
740 HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "TX", "_Window", 0, gFinalTXPerbitWin_min_max[u1ChannelIdx][u1RankIdx], NULL);
741 HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "TX", "_Window_bit", 0, min_TX_DQ_bit[u1ChannelIdx][u1RankIdx], NULL);
742 }
743 }
744 }
745 else
746 #endif
747 {
748 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
749 {
750 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
751 {
752 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("TX_Window Channel%d "
753 "Rank%d %d (bit %d)\n",
754 u1ChannelIdx,
755 u1RankIdx,
756 gFinalTXPerbitWin_min_max[u1ChannelIdx][u1RankIdx], min_TX_DQ_bit[u1ChannelIdx][u1RankIdx]));
757 }
758 }
759 }
760 #if 0//(TX_PER_BIT_DELAY_CELL==0)
761 mcSHOW_DBG_MSG(("min DQ margin\n"));
762 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
763 {
764 for (u1RankIdx = RANK_0; u1RankIdx < 2; u1RankIdx++)
765 {
766 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("min_DQ_margin Channel%d "
767 "Rank%d %d (bit %d)\n",
768 u1ChannelIdx,
769 u1RankIdx,
770 gFinalTXPerbitWin_min_margin[u1ChannelIdx][u1RankIdx], gFinalTXPerbitWin_min_margin_bit[u1ChannelIdx][u1RankIdx]));
771 }
772 }
773 #endif
774
775
776 mcSHOW_DBG_MSG(("TX Min Window(%%)\n"));
777 #ifdef FOR_HQA_REPORT_USED
778 if (gHQALog_flag == 1)
779 {
780 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
781 {
782 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
783 {
784
785 HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "TX", "_Window(%)", 0, (min_tx_value[u1ChannelIdx][u1RankIdx] * 100 + (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 63: 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 64: 32), NULL);
786 HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT4, "TX", "_Window_PF", 0, 0, (min_tx_value[u1ChannelIdx][u1RankIdx] * 100 + (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP ? 63 : 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP ? 64 : 32) >= 45 ? "PASS" : "FAIL");
787
788 if (((min_tx_value[u1ChannelIdx][u1RankIdx] * 100 + (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 63: 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 64: 32)) < 55)
789 {
790 gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 4;
791 }
792 }
793 }
794 }
795 else
796 #endif
797 {
798 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
799 {
800 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
801 {
802
803
804 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("TX_Window(%%) Channel%d "
805 "Rank%d %d%% (%s)\n",
806 u1ChannelIdx,
807 u1RankIdx,
808 (min_tx_value[u1ChannelIdx][u1RankIdx] * 100 + (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 63: 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 64: 32),
809 (min_tx_value[u1ChannelIdx][u1RankIdx] * 100 + (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 63: 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 64: 32) >= 45? "PASS" : "FAIL"));
810 }
811 }
812 }
813
814 mcSHOW_DBG_MSG(("\n"));
815 }
816
817
818
819
820 #if !defined(RELEASE) && (VENDER_JV_LOG == 0)
821 if (u1IsLP4Family(p->dram_type) && (Get_Duty_Calibration_Mode(p) != DUTY_DEFAULT))
822 {
823 mcSHOW_DBG_MSG(("[duty Calibration]\n"));
824 mcSHOW_DBG_MSG(("CLK Duty Final Delay Cell\n"));
825 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
826 {
827 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY CLK_Final_Delay Channel%d %d\n", u1ChannelIdx, gFinalClkDuty[u1ChannelIdx]));
828 }
829
830
831 mcSHOW_DBG_MSG(("CLK Duty MAX\n"));
832 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
833 {
834 #ifdef FOR_HQA_REPORT_USED
835 if (gHQALog_flag == 1)
836 {
837 HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT3, "DUTY CLK_", "MAX", 0, gFinalClkDutyMinMax[u1ChannelIdx][1], NULL);
838 }
839 else
840 #endif
841 {
842 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY CLK_MAX Channel%d %d%%(X100)\n", u1ChannelIdx, gFinalClkDutyMinMax[u1ChannelIdx][1]));
843 }
844 }
845
846
847 mcSHOW_DBG_MSG(("CLK Duty MIN\n"));
848 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
849 {
850 #ifdef FOR_HQA_REPORT_USED
851 if (gHQALog_flag == 1)
852 {
853 HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT3, "DUTY CLK_", "MIN", 0, gFinalClkDutyMinMax[u1ChannelIdx][0], NULL);
854 HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT3, "DUTY CLK_", "MAX-MIN", 0, gFinalClkDutyMinMax[u1ChannelIdx][1] - gFinalClkDutyMinMax[u1ChannelIdx][0], NULL);
855
856 if ((gFinalClkDutyMinMax[u1ChannelIdx][1] - gFinalClkDutyMinMax[u1ChannelIdx][0]) > 750)
857 {
858 gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 3;
859 }
860 }
861 else
862 #endif
863 {
864 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY CLK_MIN Channel%d %d%%(X100)\n", u1ChannelIdx, gFinalClkDutyMinMax[u1ChannelIdx][0]));
865 }
866 }
867
868 mcSHOW_DBG_MSG(("\n"));
869 }
870
871
872
873
874
875 if (u1IsLP4Family(p->dram_type) && (Get_Duty_Calibration_Mode(p) != DUTY_DEFAULT))
876 {
877 mcSHOW_DBG_MSG(("DQS Duty Final Delay Cell\n"));
878 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
879 {
880 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY DQS_Final_Delay Channel%d DQS0 %d\n", u1ChannelIdx, gFinalDQSDuty[u1ChannelIdx][0]));
881 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY DQS_Final_Delay Channel%d DQS1 %d\n", u1ChannelIdx, gFinalDQSDuty[u1ChannelIdx][1]));
882 }
883
884 mcSHOW_DBG_MSG(("DQS Duty MAX\n"));
885 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
886 {
887 #ifdef FOR_HQA_REPORT_USED
888 if (gHQALog_flag == 1)
889 {
890 HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT0, "", "DUTY DQS_MAX", 0, gFinalDQSDutyMinMax[u1ChannelIdx][0][1], NULL);
891 HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT0, "", "DUTY DQS_MAX", 1, gFinalDQSDutyMinMax[u1ChannelIdx][1][1], NULL);
892 }
893 else
894 #endif
895 {
896 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY DQS_MAX Channel%d DQS0 %d%%(X100)\n", u1ChannelIdx, gFinalDQSDutyMinMax[u1ChannelIdx][0][1]));
897 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY DQS_MAX Channel%d DQS1 %d%%(X100)\n", u1ChannelIdx, gFinalDQSDutyMinMax[u1ChannelIdx][1][1]));
898 }
899 }
900
901
902 mcSHOW_DBG_MSG(("DQS Duty MIN\n"));
903 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
904 {
905 #ifdef FOR_HQA_REPORT_USED
906 if (gHQALog_flag == 1)
907 {
908 HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT0, "DUTY DQS_", "MIN", 0, gFinalDQSDutyMinMax[u1ChannelIdx][0][0], NULL);
909 HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT0, "DUTY DQS_", "MIN", 1, gFinalDQSDutyMinMax[u1ChannelIdx][1][0], NULL);
910 HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT0, "DUTY DQS_", "MAX-MIN", 0, gFinalDQSDutyMinMax[u1ChannelIdx][0][1] - gFinalDQSDutyMinMax[u1ChannelIdx][0][0], NULL);
911 HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT0, "DUTY DQS_", "MAX-MIN", 1, gFinalDQSDutyMinMax[u1ChannelIdx][1][1] - gFinalDQSDutyMinMax[u1ChannelIdx][1][0], NULL);
912
913 if (((gFinalDQSDutyMinMax[u1ChannelIdx][0][1] - gFinalDQSDutyMinMax[u1ChannelIdx][0][0]) > 750) || ((gFinalDQSDutyMinMax[u1ChannelIdx][1][1] - gFinalDQSDutyMinMax[u1ChannelIdx][1][0]) > 750))
914 {
915 gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 3;
916 }
917 }
918 else
919 #endif
920 {
921 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY DQS_MIN Channel%d DQS0 %d%%(X100)\n", u1ChannelIdx, gFinalDQSDutyMinMax[u1ChannelIdx][0][0]));
922 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY DQS_MIN Channel%d DQS1 %d%%(X100)\n", u1ChannelIdx, gFinalDQSDutyMinMax[u1ChannelIdx][1][0]));
923 }
924 }
925
926 mcSHOW_DBG_MSG(("\n"));
927 }
928 #endif
929
930
931 #if defined(ENABLE_MIOCK_JMETER) && !defined(RELEASE)
932 mcSHOW_DBG_MSG(("\n[DramcMiockJmeter]\n"
933 "\t\t1 delay cell\t\t%d/100 ps\n", p->u2DelayCellTimex100));
934 #endif
935
936 mcSHOW_DBG_MSG(("\n\n\n"));
937
938
939
940 #if VENDER_JV_LOG
941 mcSHOW_JV_LOG_MSG(("\n\n\n[Summary] information for measurement\n"));
942 //mcSHOW_JV_LOG_MSG(("\tDram Data rate = ")); HQA_LOG_Print_Freq_String(p); mcSHOW_DBG_MSG(("\n"));
943 vPrintCalibrationBasicInfo_ForJV(p);
944
945 if (u1IsLP4Family(p->dram_type))
946 {
947 mcSHOW_JV_LOG_MSG(("[Cmd Bus Training window]\n"));
948
949 //mcSHOW_JV_LOG_MSG(("VrefCA Range : %d\n", gCBT_VREF_RANGE_SEL));
950 #if CHANNEL_NUM == 4
951 mcSHOW_JV_LOG_MSG(("CHA_VrefCA_Rank0 CHB_VrefCA_Rank0 CHC_VrefCA_Rank0 CHD_VrefCA_Rank0\n"));
952 mcSHOW_JV_LOG_MSG(("%d %d %d %d\n", gFinalCBTVrefCA[0][0], gFinalCBTVrefCA[1][0], gFinalCBTVrefCA[2][0], gFinalCBTVrefCA[3][0]));
953 #else
954 mcSHOW_JV_LOG_MSG(("CHA_VrefCA_Rank0 CHB_VrefCA_Rank0\n"));
955 mcSHOW_JV_LOG_MSG(("%d %d\n", gFinalCBTVrefCA[0][0], gFinalCBTVrefCA[1][0]));
956 #endif
957 mcSHOW_JV_LOG_MSG(("CHA_CA_window_Rank0 CHB_CA_winow_Rank0\n"));
958 mcSHOW_JV_LOG_MSG(("%d%%(bit %d) %d%%(bit %d) \n\n", (min_ca_value[0][0] * 100 + 63) / 64, min_ca_bit[0][0],
959 (min_ca_value[1][0] * 100 + 63) / 64, min_ca_bit[1][0]));
960 }
961 else
962 {
963 mcSHOW_JV_LOG_MSG(("[CA Training window]\n"));
964 mcSHOW_JV_LOG_MSG(("CHA_CA_win_Rank0\n"));
965 mcSHOW_JV_LOG_MSG(("%d%%(bit %d)\n\n", (min_ca_value[0][0] * 100 + 63) / 64, min_ca_bit[0][0]));
966 }
967
968 mcSHOW_JV_LOG_MSG(("[RX minimum per bit window]\n"));
969 if (Get_Vref_Calibration_OnOff(p) == VREF_CALI_ON)
970 {
971 #if CHANNEL_NUM == 4
972 mcSHOW_JV_LOG_MSG(("CHA_VrefDQ CHB_VrefDQ CHC_VrefDQ CHD_VrefDQ\n"));
973 mcSHOW_JV_LOG_MSG(("B0 %d %d %d %d \n", gFinalRXVrefDQ[CHANNEL_A][RANK_0][0], gFinalRXVrefDQ[CHANNEL_B][RANK_0][0], gFinalRXVrefDQ[CHANNEL_C][RANK_0][0], gFinalRXVrefDQ[CHANNEL_D][RANK_0][0]));
974 mcSHOW_JV_LOG_MSG(("B1 %d %d %d %d \n", gFinalRXVrefDQ[CHANNEL_A][RANK_0][1], gFinalRXVrefDQ[CHANNEL_B][RANK_0][1], gFinalRXVrefDQ[CHANNEL_C][RANK_0][1], gFinalRXVrefDQ[CHANNEL_D][RANK_0][1]));
975 #else
976 mcSHOW_JV_LOG_MSG(("CHA_VrefDQ CHB_VrefDQ\n"));
977 mcSHOW_JV_LOG_MSG(("B0 %d %d \n", gFinalRXVrefDQ[CHANNEL_A][RANK_0][0], gFinalRXVrefDQ[CHANNEL_B][RANK_0][0]));
978 mcSHOW_JV_LOG_MSG(("B1 %d %d \n", gFinalRXVrefDQ[CHANNEL_A][RANK_0][1], gFinalRXVrefDQ[CHANNEL_B][RANK_0][1]));
979 #endif
980 }
981 else
982 {
983 mcSHOW_JV_LOG_MSG(("RX DQ Vref Scan : Disable\n"));
984
985 }
986
987 if (u1IsLP4Family(p->dram_type))
988 {
989 #if CHANNEL_NUM == 4
990 mcSHOW_JV_LOG_MSG(("CHA_Rank0 CHA_Rank1 CHB_Rank0 CHB_Rank1 CHC_Rank0 CHC_Rank1 CHD_Rank0 CHD_Rank1\n"));
991 mcSHOW_JV_LOG_MSG(("%d%%(bit %d) %d%%(bit %d) %d%%(bit %d) %d%%(bit %d) %d%%(bit %d) %d%%(bit %d) %d%%(bit %d) %d%%(bit %d)\n\n",
992 ((min_rx_value[0][0] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[0][0],
993 ((min_rx_value[0][1] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[0][1],
994 ((min_rx_value[1][0] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[1][0],
995 ((min_rx_value[1][1] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[1][1],
996 ((min_rx_value[2][0] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[2][0],
997 ((min_rx_value[2][1] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[2][1],
998 ((min_rx_value[3][0] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[3][0],
999 ((min_rx_value[3][1] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[3][1]));
1000 #else
1001 mcSHOW_JV_LOG_MSG(("CHA_Rank0 CHA_Rank1 CHB_Rank0 CHB_Rank1\n"));
1002 mcSHOW_JV_LOG_MSG(("%d%%(bit %d) %d%%(bit %d) %d%%(bit %d) %d%%(bit %d)\n\n",
1003 ((min_rx_value[0][0] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[0][0],
1004 ((min_rx_value[0][1] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[0][1],
1005 ((min_rx_value[1][0] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[1][0],
1006 ((min_rx_value[1][1] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[1][1]));
1007 #endif
1008 }
1009 #if ENABLE_LP3_SW
1010 else
1011 {
1012 mcSHOW_JV_LOG_MSG(("CHA_Rank0 CHA_Rank1\n"));
1013 mcSHOW_JV_LOG_MSG(("%d%%(bit %d) %d%%(bit %d)\n\n",
1014 ((min_rx_value[0][0] * u2gdelay_cell_ps_all[SRAMIdx] * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[0][0],
1015 ((min_rx_value[0][1] * u2gdelay_cell_ps_all[SRAMIdx] * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[0][1]));
1016 }
1017 #endif
1018
1019 mcSHOW_JV_LOG_MSG(("[TX minimum per bit window]\n"));
1020 if (Get_Vref_Calibration_OnOff(p) == VREF_CALI_ON)
1021 {
1022 mcSHOW_JV_LOG_MSG(("VrefDQ Range : %d\n", (u1MR14Value[p->channel][p->rank][p->dram_fsp] >> 6) & 1));
1023 #if CHANNEL_NUM == 4
1024 mcSHOW_JV_LOG_MSG(("CHA_VrefDQ_Rank0 CHA_VrefDQ_Rank1 CHB_VrefDQ_Rank0 CHB_VrefDQ_Rank1 CHC_VrefDQ_Rank0 CHC_VrefDQ_Rank1 CHD_VrefDQ_Rank0 CHD_VrefDQ_Rank1\n"));
1025 mcSHOW_JV_LOG_MSG(("%d %d %d %d %d %d %d %d\n"
1026 , gFinalTXVrefDQ[0][0], gFinalTXVrefDQ[0][1], gFinalTXVrefDQ[1][0], gFinalTXVrefDQ[1][1]
1027 , gFinalTXVrefDQ[2][0], gFinalTXVrefDQ[2][1], gFinalTXVrefDQ[3][0], gFinalTXVrefDQ[3][1]
1028 ));
1029 #else
1030 mcSHOW_JV_LOG_MSG(("CHA_VrefDQ_Rank0 CHA_VrefDQ_Rank1 CHB_VrefDQ_Rank0 CHB_VrefDQ_Rank1\n"));
1031 mcSHOW_JV_LOG_MSG(("%d %d %d %d\n", gFinalTXVrefDQ[0][0], gFinalTXVrefDQ[0][1], gFinalTXVrefDQ[1][0], gFinalTXVrefDQ[1][1]));
1032 #endif
1033 }
1034 else
1035 {
1036 mcSHOW_JV_LOG_MSG(("TX DQ Vref Scan : Disable\n"));
1037 }
1038
1039 if (u1IsLP4Family(p->dram_type))
1040 {
1041 #if CHANNEL_NUM == 4
1042 mcSHOW_JV_LOG_MSG(("CHA_Rank0 CHA_Rank1 CHB_Rank0 CHB_Rank1 CHC_Rank0 CHC_Rank1 CHD_Rank0 CHD_Rank1\n"));
1043 mcSHOW_JV_LOG_MSG(("%d%% %d%% %d%% %d%% %d%% %d%% %d%% %d%%\n",
1044 (min_tx_value[0][0] * 100 + 31) / 32,
1045 (min_tx_value[0][1] * 100 + 31) / 32,
1046 (min_tx_value[1][0] * 100 + 31) / 32,
1047 (min_tx_value[1][1] * 100 + 31) / 32,
1048 (min_tx_value[2][0] * 100 + 31) / 32,
1049 (min_tx_value[2][1] * 100 + 31) / 32,
1050 (min_tx_value[3][0] * 100 + 31) / 32,
1051 (min_tx_value[3][1] * 100 + 31) / 32
1052 ));
1053 #else
1054 mcSHOW_JV_LOG_MSG(("CHA_Rank0 CHA_Rank1 CHB_Rank0 CHB_Rank1\n"));
1055 mcSHOW_JV_LOG_MSG(("%d%% %d%% %d%% %d%%\n",
1056 (min_tx_value[0][0] * 100 + 31) / 32,
1057 (min_tx_value[0][1] * 100 + 31) / 32,
1058 (min_tx_value[1][0] * 100 + 31) / 32,
1059 (min_tx_value[1][1] * 100 + 31) / 32));
1060 #endif
1061 }
1062 else
1063 {
1064 mcSHOW_JV_LOG_MSG(("CHA_Rank0 CHA_Rank1\n"));
1065 mcSHOW_JV_LOG_MSG(("%d%% %d%%\n",
1066 (min_tx_value[0][0] * 100 + 31) / 32,
1067 (min_tx_value[0][1] * 100 + 31) / 32));
1068 }
1069 #endif
1070
1071
1072
1073 HQA_measure_message_reset_all_data(p);
1074 }
1075 #ifdef RELEASE
1076 #undef mcSHOW_DBG_MSG
1077 #define mcSHOW_DBG_MSG(_x_)
1078 #endif
1079 #endif
1080
1081
1082 #ifdef FOR_HQA_REPORT_USED
print_EyeScanVcent_for_HQA_report_used(DRAMC_CTX_T * p,U8 print_type,U8 u1ChannelIdx,U8 u1RankIdx,U8 u1ByteIdx,U8 * EyeScanVcent,U8 EyeScanVcentUpperBound,U8 EyeScanVcentUpperBound_bit,U8 EyeScanVcentLowerBound,U8 EyeScanVcentLowerBound_bit)1083 static void print_EyeScanVcent_for_HQA_report_used(DRAMC_CTX_T *p, U8 print_type, U8 u1ChannelIdx, U8 u1RankIdx, U8 u1ByteIdx, U8 *EyeScanVcent, U8 EyeScanVcentUpperBound, U8 EyeScanVcentUpperBound_bit, U8 EyeScanVcentLowerBound, U8 EyeScanVcentLowerBound_bit)
1084 {
1085 U8 uiCA, u1BitIdx;
1086 U16 *pVref_Voltage_Table[VREF_VOLTAGE_TABLE_NUM_LP5] = {0};
1087 U8 VrefRange;
1088 U32 vddq = 0;
1089 U8 local_channel_num = 2;
1090 U8 SRAMIdx;
1091 U8 u1CBTEyeScanEnable, u1RXEyeScanEnable, u1TXEyeScanEnable;
1092 U16 Final_Vref_Vcent, VdlVWHigh_Upper_Vcent, VdlVWHigh_Lower_Vcent;
1093 U32 Vcent_UpperBound_Window_percent = 0, Vcent_LowerBound_Window_percent = 0;
1094 U32 Perbit_Window_percent, Perbit_BestWindow_percent, Perbit_Window_Upperbond_percent, Perbit_Window_Lowerbond_percent, Perbit_Eye_Height, Perbit_Eye_Area;
1095 U8 u1BitIndex_Begin = 0, u1BitIndex_End = p->data_width;
1096
1097 if (gHQALog_flag == 0)
1098 {
1099 mcSHOW_DBG_MSG(("\n"));
1100 return;
1101 }
1102
1103 if (u1IsLP4Family(p->dram_type))
1104 {
1105 local_channel_num = p->support_channel_num;
1106 }
1107 else
1108 {
1109
1110 local_channel_num = 1;
1111 }
1112
1113 u1CBTEyeScanEnable = GetEyeScanEnable(p, EYESCAN_TYPE_CBT);
1114 u1RXEyeScanEnable = GetEyeScanEnable(p, EYESCAN_TYPE_RX);
1115 u1TXEyeScanEnable = GetEyeScanEnable(p, EYESCAN_TYPE_TX);
1116
1117 SRAMIdx = vGet_Current_SRAMIdx(p);
1118
1119 if (print_type == EYESCAN_TYPE_RX)
1120 {
1121 if (p->odt_onoff==TRUE)
1122 {
1123 if (p->dram_type==TYPE_LPDDR5)
1124 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_T;
1125 else
1126 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_T;
1127 }
1128 else
1129 {
1130 if (p->dram_type==TYPE_LPDDR5)
1131 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_UT;
1132 else
1133 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_UT;
1134 }
1135
1136 u1BitIndex_Begin = u1ByteIdx * DQS_BIT_NUMBER;
1137 u1BitIndex_End = u1ByteIdx * DQS_BIT_NUMBER + DQS_BIT_NUMBER;
1138 }
1139 else
1140 {
1141 if (u1CBTEyeScanEnable || u1TXEyeScanEnable)
1142 {
1143 vddq = vGetVoltage(p, 2) / 1000;
1144
1145 if (p->dram_type == TYPE_LPDDR4)
1146 {
1147 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP4[VREF_RANGE_0];
1148 pVref_Voltage_Table[VREF_RANGE_1] = (U16 *)gVref_Voltage_Table_LP4[VREF_RANGE_1];
1149 }
1150 if (p->dram_type == TYPE_LPDDR4X)
1151 {
1152 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP4X[VREF_RANGE_0];
1153 pVref_Voltage_Table[VREF_RANGE_1] = (U16 *)gVref_Voltage_Table_LP4X[VREF_RANGE_1];
1154 }
1155 }
1156 }
1157
1158 if (print_type == EYESCAN_TYPE_CBT)
1159 {
1160 if (u1CBTEyeScanEnable)
1161 {
1162 VrefRange = (u1MR12Value[p->channel][p->rank][p->dram_fsp] >> 6) & 1;
1163
1164 Vcent_UpperBound_Window_percent = (EyeScanVcentUpperBound * 100 + (u1IsLP4Family(p->dram_type) == 1? 63: 31)) / (u1IsLP4Family(p->dram_type) == 1? 64: 32);
1165 Vcent_LowerBound_Window_percent = (EyeScanVcentLowerBound * 100 + (u1IsLP4Family(p->dram_type) == 1? 63: 31)) / (u1IsLP4Family(p->dram_type) == 1? 64: 32);
1166 }
1167 }
1168
1169 if (print_type == EYESCAN_TYPE_RX)
1170 {
1171 if (u1RXEyeScanEnable)
1172 {
1173 Final_Vref_Vcent = pVref_Voltage_Table[0][EyeScanVcent[1]];
1174 VdlVWHigh_Upper_Vcent = pVref_Voltage_Table[0][EyeScanVcent[3]];
1175 VdlVWHigh_Lower_Vcent = pVref_Voltage_Table[0][EyeScanVcent[5]];
1176
1177 Vcent_UpperBound_Window_percent = ((EyeScanVcentUpperBound * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000;
1178 Vcent_LowerBound_Window_percent = ((EyeScanVcentLowerBound * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000;
1179 }
1180 }
1181
1182 if (print_type == EYESCAN_TYPE_TX)
1183 {
1184 if (u1TXEyeScanEnable)
1185 {
1186 VrefRange = (u1MR14Value[p->channel][p->rank][p->dram_fsp] >> 6) & 1;
1187
1188 Final_Vref_Vcent = pVref_Voltage_Table[EyeScanVcent[0]][EyeScanVcent[1]] * vddq / 100;
1189 VdlVWHigh_Upper_Vcent = pVref_Voltage_Table[EyeScanVcent[2]][EyeScanVcent[3]] * vddq / 100;
1190 VdlVWHigh_Lower_Vcent = pVref_Voltage_Table[EyeScanVcent[4]][EyeScanVcent[5]] * vddq / 100;
1191
1192 Vcent_UpperBound_Window_percent = (EyeScanVcentUpperBound * 100 + (u1IsLP4Div4DDR800(p) == TRUE? 63: 31)) / (u1IsLP4Div4DDR800(p) == TRUE? 64: 32);
1193 Vcent_LowerBound_Window_percent = (EyeScanVcentLowerBound * 100 + (u1IsLP4Div4DDR800(p) == TRUE? 63: 31)) / (u1IsLP4Div4DDR800(p) == TRUE? 64: 32);
1194 }
1195 }
1196
1197 mcSHOW_DBG_MSG(("\n\n\n[HQA] information for measurement, "));
1198 mcSHOW_DBG_MSG(("\tDram Data rate = ")); HQA_LOG_Print_Freq_String(p); mcSHOW_DBG_MSG(("\n"));
1199
1200 #if ENABLE_EYESCAN_GRAPH
1201 mcSHOW_DBG_MSG(("%s Eye Scan Vcent Voltage\n", print_EYESCAN_LOG_type(print_type)));
1202 if (print_type == EYESCAN_TYPE_RX)
1203 {
1204 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2_1, print_EYESCAN_LOG_type(print_type), "_Final_Vref Vcent", u1ByteIdx, pVref_Voltage_Table[0][EyeScanVcent[1]], NULL);
1205 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2_1, print_EYESCAN_LOG_type(print_type), "_VdlVWHigh_Upper Vcent", u1ByteIdx, pVref_Voltage_Table[0][EyeScanVcent[3]], NULL);
1206 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2_1, print_EYESCAN_LOG_type(print_type), "_VdlVWHigh_Lower Vcent", u1ByteIdx, pVref_Voltage_Table[0][EyeScanVcent[5]], NULL);
1207 }
1208 else
1209 {
1210 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_Final_Vref Vcent", 0, pVref_Voltage_Table[EyeScanVcent[0]][EyeScanVcent[1]] * vddq / 100, NULL);
1211 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_VdlVWHigh_Upper Vcent", 0, pVref_Voltage_Table[EyeScanVcent[2]][EyeScanVcent[3]] * vddq / 100, NULL);
1212 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_VdlVWHigh_Lower Vcent", 0, pVref_Voltage_Table[EyeScanVcent[4]][EyeScanVcent[5]] * vddq / 100, NULL);
1213 }
1214
1215 mcSHOW_DBG_MSG(("\n"));
1216 #endif
1217
1218 mcSHOW_DBG_MSG(("%s Eye Scan Vcent_UpperBound window\n", print_EYESCAN_LOG_type(print_type)));
1219 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_Vcent_UpperBound_Window", 0, EyeScanVcentUpperBound, NULL);
1220 mcSHOW_DBG_MSG(("%s Eye Scan Vcent_UpperBound_Window worse bit\n", print_EYESCAN_LOG_type(print_type)));
1221 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_Vcent_UpperBound_Window_bit", 0, EyeScanVcentUpperBound_bit, NULL);
1222 mcSHOW_DBG_MSG(("%s Eye Scan Vcent_UpperBound Min Window(%%)\n", print_EYESCAN_LOG_type(print_type)));
1223 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_Vcent_UpperBound_Window(%)", 0, Vcent_UpperBound_Window_percent, NULL);
1224
1225 mcSHOW_DBG_MSG(("\n"));
1226
1227 mcSHOW_DBG_MSG(("%s Eye Scan Vcent_LowerBound window\n", print_EYESCAN_LOG_type(print_type)));
1228 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_Vcent_LowerBound_Window", 0, EyeScanVcentLowerBound, NULL);
1229 mcSHOW_DBG_MSG(("%s Eye Scan Vcent_LowerBound_Window worse bit\n", print_EYESCAN_LOG_type(print_type)));
1230 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_Vcent_LowerBound_Window_bit", 0, EyeScanVcentLowerBound_bit, NULL);
1231 mcSHOW_DBG_MSG(("%s Eye Scan Vcent_UpperBound Min Window(%%)\n", print_EYESCAN_LOG_type(print_type)));
1232 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_Vcent_LowerBound_Window(%)", 0, Vcent_LowerBound_Window_percent, NULL);
1233
1234 #if defined(FOR_HQA_REPORT_USED)
1235 if (gHQALog_flag == 1)
1236 {
1237 if ((Vcent_UpperBound_Window_percent < 30) || (Vcent_LowerBound_Window_percent < 30))
1238 {
1239 gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 4;
1240 }
1241 }
1242 #endif
1243
1244 if (print_type == EYESCAN_TYPE_RX || print_type == EYESCAN_TYPE_TX)
1245 {
1246 mcSHOW_DBG_MSG(("\n"));
1247 mcSHOW_DBG_MSG(("%s Eye Scan per_bit window(%%)\n", print_EYESCAN_LOG_type(print_type)));
1248 for (u1BitIdx = u1BitIndex_Begin; u1BitIdx < u1BitIndex_End; u1BitIdx++)
1249 {
1250 #if ENABLE_EYESCAN_GRAPH
1251 if (print_type == EYESCAN_TYPE_RX)
1252 {
1253 Perbit_Window_percent = ((gEyeScan_WinSize[EyeScanVcent[1] / EYESCAN_GRAPH_RX_VREF_STEP][u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000;
1254 Perbit_BestWindow_percent = ((gEyeScan_WinSize[EyeScanVcent[10 + u1BitIdx] / EYESCAN_GRAPH_RX_VREF_STEP][u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000;
1255 Perbit_Window_Upperbond_percent = ((gEyeScan_WinSize[EyeScanVcent[3] / EYESCAN_GRAPH_RX_VREF_STEP][u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000;
1256 Perbit_Window_Lowerbond_percent = ((gEyeScan_WinSize[EyeScanVcent[5] / EYESCAN_GRAPH_RX_VREF_STEP][u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000;
1257
1258 Perbit_Eye_Height = (pVref_Voltage_Table[VREF_RANGE_0][((gEyeScan_ContinueVrefHeight[u1BitIdx] >> 8) & 0xff)] - pVref_Voltage_Table[VREF_RANGE_0][(gEyeScan_ContinueVrefHeight[u1BitIdx] & 0xff)]) / 100;
1259 Perbit_Eye_Area = gEyeScan_TotalPassCount[u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V * (((pVref_Voltage_Table[VREF_RANGE_0][((gEyeScan_ContinueVrefHeight[u1BitIdx] >> 8) & 0xff)] - pVref_Voltage_Table[VREF_RANGE_0][(gEyeScan_ContinueVrefHeight[u1BitIdx] & 0xff)])) / ((((gEyeScan_ContinueVrefHeight[u1BitIdx] >> 8) & 0xff) - (gEyeScan_ContinueVrefHeight[u1BitIdx] & 0xff)) * 10)) / 1000;
1260 }
1261 else //if (print_type==2)
1262 {
1263 Perbit_Window_percent = ((gEyeScan_WinSize[(EyeScanVcent[0] * 30 + EyeScanVcent[1]) / EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx]) * 100 + 31) / 32;
1264 Perbit_BestWindow_percent = ((gEyeScan_WinSize[(EyeScanVcent[10 + u1BitIdx * 2] * 30 + EyeScanVcent[10 + u1BitIdx * 2 + 1]) / EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx]) * 100 + 31) / 32;
1265 Perbit_Window_Upperbond_percent = ((gEyeScan_WinSize[(EyeScanVcent[2] * 30 + EyeScanVcent[3]) / EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx]) * 100 + 31) / 32;
1266 Perbit_Window_Lowerbond_percent = ((gEyeScan_WinSize[(EyeScanVcent[4] * 30 + EyeScanVcent[5]) / EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx]) * 100 + 31) / 32;
1267 Perbit_Eye_Height = (gEyeScan_ContinueVrefHeight[u1BitIdx] - 1) * 6 * vddq / 1000;
1268 Perbit_Eye_Area = (gEyeScan_TotalPassCount[u1BitIdx] * 10 * 3 * vddq / (32 * DDRPhyGetRealFreq(p)))*100;
1269 }
1270
1271 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, print_EYESCAN_LOG_type(print_type), "_Perbit_Window(%)", u1BitIdx, Perbit_Window_percent, NULL);
1272 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, print_EYESCAN_LOG_type(print_type), "_Perbit_BestWindow(%)", u1BitIdx, Perbit_BestWindow_percent, NULL);
1273 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, print_EYESCAN_LOG_type(print_type), "_Perbit_Window_Upperbond(%)", u1BitIdx, Perbit_Window_Upperbond_percent, NULL);
1274 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, print_EYESCAN_LOG_type(print_type), "_Perbit_Window_Lowerbond(%) ", u1BitIdx, Perbit_Window_Lowerbond_percent, NULL);
1275 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, print_EYESCAN_LOG_type(print_type), "_Perbit_Eye_Height", u1BitIdx, Perbit_Eye_Height, NULL);
1276 HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, print_EYESCAN_LOG_type(print_type), "_Perbit_Eye_Area", u1BitIdx, Perbit_Eye_Area, NULL);
1277 #endif
1278 }
1279 }
1280 }
1281
HQA_Log_Message_for_Report(DRAMC_CTX_T * p,U8 u1ChannelIdx,U8 u1RankIdx,U32 who_am_I,U8 * main_str,U8 * main_str2,U8 byte_bit_idx,S32 value1,U8 * ans_str)1282 void HQA_Log_Message_for_Report(DRAMC_CTX_T *p, U8 u1ChannelIdx, U8 u1RankIdx, U32 who_am_I, U8 *main_str, U8 *main_str2, U8 byte_bit_idx, S32 value1, U8 *ans_str)
1283 {
1284
1285 if (gHQALog_flag == 1)
1286 {
1287 HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("%s%s", main_str, main_str2));
1288 switch (who_am_I)
1289 {
1290 case HQA_REPORT_FORMAT1:
1291 mcSHOW_DBG_MSG(("%d", byte_bit_idx));
1292 break;
1293 }
1294
1295 if (who_am_I == HQA_REPORT_FORMAT3)
1296 {
1297 mcSHOW_DBG_MSG((" Channel%d ", u1ChannelIdx));
1298 }
1299 else if (who_am_I != HQA_REPORT_FORMAT5 && who_am_I != HQA_REPORT_FORMAT6)
1300 {
1301 mcSHOW_DBG_MSG((" Channel%d Rank%d ", u1ChannelIdx, u1RankIdx));
1302 }
1303
1304 switch (who_am_I)
1305 {
1306 case HQA_REPORT_FORMAT2_1:
1307 case HQA_REPORT_FORMAT0:
1308 mcSHOW_DBG_MSG(("Byte%d %d\n", byte_bit_idx, value1));
1309 break;
1310 case HQA_REPORT_FORMAT0_1:
1311 mcSHOW_DBG_MSG(("Bit%x %d\n", byte_bit_idx, value1));
1312 break;
1313 case HQA_REPORT_FORMAT0_2:
1314 mcSHOW_DBG_MSG(("CA%x %d\n", byte_bit_idx, value1));
1315 break;
1316 case HQA_REPORT_FORMAT1:
1317 case HQA_REPORT_FORMAT2:
1318 case HQA_REPORT_FORMAT3:
1319 case HQA_REPORT_FORMAT6:
1320 mcSHOW_DBG_MSG(("%d\n", value1));
1321 break;
1322 case HQA_REPORT_FORMAT4:
1323 case HQA_REPORT_FORMAT5:
1324 mcSHOW_DBG_MSG((" %s\n", ans_str));
1325 break;
1326 }
1327 }
1328 }
1329
1330 #endif
1331
1332
1333 #ifdef RELEASE
1334 #undef mcSHOW_DBG_MSG
1335 #define mcSHOW_DBG_MSG(_x_) opt_print _x_
1336 #endif
1337
1338
1339 #if ENABLE_EYESCAN_GRAPH
1340 #define EyeScan_Pic_draw_line_Mirror 1
1341 #define EysScan_Pic_draw_1UI_line 1
EyeScan_Pic_draw_line(DRAMC_CTX_T * p,U8 draw_type,U8 u1VrefRange,U8 u1VrefIdx,U8 u1BitIdx,S16 u2DQDelayBegin,S16 u2DQDelayEnd,U8 u1FinalVrefRange,U16 Final_Vref_val,U8 VdlVWHigh_Upper_Vcent_Range,U32 VdlVWHigh_Upper_Vcent,U8 VdlVWHigh_Lower_Vcent_Range,U32 VdlVWHigh_Lower_Vcent,U16 FinalDQCaliDelay,S16 EyeScan_DelayCellPI_value,U16 delay_cell_ps,U16 Max_EyeScan_Min_val)1342 static void EyeScan_Pic_draw_line(DRAMC_CTX_T *p, U8 draw_type, U8 u1VrefRange, U8 u1VrefIdx, U8 u1BitIdx, S16 u2DQDelayBegin, S16 u2DQDelayEnd, U8 u1FinalVrefRange, U16 Final_Vref_val, U8 VdlVWHigh_Upper_Vcent_Range, U32 VdlVWHigh_Upper_Vcent, U8 VdlVWHigh_Lower_Vcent_Range, U32 VdlVWHigh_Lower_Vcent, U16 FinalDQCaliDelay, S16 EyeScan_DelayCellPI_value, U16 delay_cell_ps, U16 Max_EyeScan_Min_val)
1343 {
1344 int i;
1345 int local_VrefIdx, local_Upper_Vcent, local_Lower_Vcent, local_Final_VrefIdx;
1346 S8 EyeScan_Index = 0;
1347 S16 EyeScan_Min_val, EyeScan_Max_val, Final_EyeScan_Min_val = EYESCAN_DATA_INVALID, Final_EyeScan_Max_val = EYESCAN_DATA_INVALID, Final_EyeScan_winsize = 1;
1348 U16 *pVref_Voltage_Table[VREF_VOLTAGE_TABLE_NUM_LP5];
1349 U16 PI_of_1_UI;
1350 U16 u2DQDelayStep=1, u2VrefStep=1;
1351 U16 pass_region_h_value=3;
1352
1353 if (draw_type == EYESCAN_TYPE_RX)
1354 {
1355 u2DQDelayStep=4;
1356 u2VrefStep=EYESCAN_GRAPH_RX_VREF_STEP;
1357 if (p->odt_onoff==TRUE)
1358 {
1359 if (p->dram_type==TYPE_LPDDR5)
1360 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_T;
1361 else
1362 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_T;
1363 }
1364 else
1365 {
1366 if (p->dram_type==TYPE_LPDDR5)
1367 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_UT;
1368 else
1369 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_UT;
1370 }
1371
1372 if (p->u2DelayCellTimex100 != 0)
1373 {
1374 PI_of_1_UI = (50000000 / (DDRPhyGetRealFreq(p)* p->u2DelayCellTimex100));
1375
1376 FinalDQCaliDelay = (U16)EyeScan_DelayCellPI_value;
1377 EyeScan_DelayCellPI_value = 0;
1378
1379
1380 pass_region_h_value = PI_of_1_UI/10;
1381
1382 delay_cell_ps = p->u2DelayCellTimex100;
1383 }
1384 else
1385 {
1386 PI_of_1_UI = 0;
1387 //mcSHOW_ERR_MSG(("DelayCell is 0\n"));
1388 }
1389 }
1390 else
1391 {
1392 u2VrefStep = EYESCAN_GRAPH_CATX_VREF_STEP;
1393
1394
1395 pass_region_h_value = 3;
1396
1397 if (p->dram_type == TYPE_LPDDR4)
1398 {
1399 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP4[VREF_RANGE_0];
1400 pVref_Voltage_Table[VREF_RANGE_1] = (U16 *)gVref_Voltage_Table_LP4[VREF_RANGE_1];
1401 }
1402 else if (p->dram_type == TYPE_LPDDR4X)
1403 {
1404 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP4X[VREF_RANGE_0];
1405 pVref_Voltage_Table[VREF_RANGE_1] = (U16 *)gVref_Voltage_Table_LP4X[VREF_RANGE_1];
1406 }
1407 else if (p->dram_type == TYPE_LPDDR5)
1408 {
1409 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP5;
1410 }
1411
1412 PI_of_1_UI = 32;
1413 }
1414
1415 if (u1VrefRange == 1 && u1VrefIdx <= 20)
1416 {
1417 u1VrefRange = 0;
1418 u1VrefIdx += 30;
1419 }
1420 if (u1FinalVrefRange == 1 && Final_Vref_val <= 20)
1421 {
1422 u1FinalVrefRange = 0;
1423 Final_Vref_val += 30;
1424 }
1425 if (u1VrefRange != u1FinalVrefRange)
1426 {
1427 Final_Vref_val = 0xff;
1428 }
1429
1430 local_Upper_Vcent = VdlVWHigh_Upper_Vcent_Range * VREF_VOLTAGE_TABLE_NUM_LP4+ VdlVWHigh_Upper_Vcent;
1431 local_Lower_Vcent = VdlVWHigh_Lower_Vcent_Range * VREF_VOLTAGE_TABLE_NUM_LP4+ VdlVWHigh_Lower_Vcent;
1432 local_VrefIdx = u1VrefRange * VREF_VOLTAGE_TABLE_NUM_LP4+ u1VrefIdx;
1433 local_Final_VrefIdx = u1FinalVrefRange * VREF_VOLTAGE_TABLE_NUM_LP4+ Final_Vref_val;
1434
1435 if (VdlVWHigh_Upper_Vcent_Range == VREF_RANGE_1 && VdlVWHigh_Upper_Vcent <= 20) local_Upper_Vcent = VdlVWHigh_Upper_Vcent_Range * VREF_VOLTAGE_TABLE_NUM_LP4+ VdlVWHigh_Upper_Vcent - 20;
1436 if (VdlVWHigh_Lower_Vcent_Range == VREF_RANGE_1 && VdlVWHigh_Lower_Vcent <= 20) local_Lower_Vcent = VdlVWHigh_Lower_Vcent_Range * VREF_VOLTAGE_TABLE_NUM_LP4+ VdlVWHigh_Lower_Vcent - 20;
1437
1438 mcSHOW_EYESCAN_MSG(("Vref-"));
1439
1440 if (draw_type == EYESCAN_TYPE_RX && pVref_Voltage_Table[u1VrefRange][u1VrefIdx] <10000)
1441 {
1442 mcSHOW_EYESCAN_MSG((" "));
1443 }
1444
1445 mcSHOW_EYESCAN_MSG(("%d.%d%d", pVref_Voltage_Table[u1VrefRange][u1VrefIdx] / 100, ((pVref_Voltage_Table[u1VrefRange][u1VrefIdx] % 100) / 10), pVref_Voltage_Table[u1VrefRange][u1VrefIdx] % 10));
1446 if (draw_type == EYESCAN_TYPE_RX)
1447 {
1448 mcSHOW_EYESCAN_MSG(("m|"));
1449 }
1450 else
1451 {
1452 mcSHOW_EYESCAN_MSG(("%%|"));
1453 }
1454
1455
1456
1457
1458
1459 #if VENDER_JV_LOG || defined(RELEASE)
1460 #if EyeScan_Pic_draw_line_Mirror
1461 EyeScan_DelayCellPI_value = 0 - EyeScan_DelayCellPI_value;
1462 #endif
1463 #endif
1464
1465 #if EyeScan_Pic_draw_line_Mirror
1466 EyeScan_Index = EYESCAN_BROKEN_NUM - 1;
1467 EyeScan_Min_val = gEyeScan_Min[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
1468 EyeScan_Max_val = gEyeScan_Max[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
1469
1470 while (EyeScan_Min_val == EYESCAN_DATA_INVALID && EyeScan_Index > 0)
1471 {
1472 EyeScan_Index--;
1473 EyeScan_Min_val = gEyeScan_Min[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
1474 EyeScan_Max_val = gEyeScan_Max[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
1475 }
1476 #else
1477 EyeScan_Index = 0;
1478 EyeScan_Min_val = gEyeScan_Min[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
1479 EyeScan_Max_val = gEyeScan_Max[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
1480 #endif
1481
1482 if (draw_type == EYESCAN_TYPE_TX)
1483 {
1484 EyeScan_Min_val += gEyeScan_MinMax_store_delay[u1BitIdx / 8];
1485 EyeScan_Max_val += gEyeScan_MinMax_store_delay[u1BitIdx / 8];
1486 }
1487
1488 if ((EyeScan_Max_val - EyeScan_Min_val + 1) > Final_EyeScan_winsize)
1489 {
1490 #if EyeScan_Pic_draw_line_Mirror
1491 Final_EyeScan_Max_val = EyeScan_Max_val;
1492 Final_EyeScan_Min_val = EyeScan_Min_val;
1493 #else
1494 Final_EyeScan_Max_val = EyeScan_Max_val;
1495 Final_EyeScan_Min_val = EyeScan_Min_val;
1496 #endif
1497 Final_EyeScan_winsize = (EyeScan_Max_val - EyeScan_Min_val + 1);
1498 }
1499
1500 #if VENDER_JV_LOG || defined(RELEASE)
1501 #if EyeScan_Pic_draw_line_Mirror
1502 for (i = (Max_EyeScan_Min_val + PI_of_1_UI + EyeScan_DelayCellPI_value) * delay_cell_ps / 100; i > (Max_EyeScan_Min_val - PI_of_1_UI + EyeScan_DelayCellPI_value) * delay_cell_ps / 100; i -= 10)
1503 #else
1504 for (i = (Max_EyeScan_Min_val - PI_of_1_UI + EyeScan_DelayCellPI_value) * delay_cell_ps / 100; i < (Max_EyeScan_Min_val + PI_of_1_UI + EyeScan_DelayCellPI_value) * delay_cell_ps / 100; i += 10)
1505 #endif
1506 #else
1507 #if EyeScan_Pic_draw_line_Mirror
1508 for (i = u2DQDelayEnd; i >= u2DQDelayBegin; i-=u2DQDelayStep)
1509 #else
1510 for (i = u2DQDelayBegin; i <= u2DQDelayEnd; i+=u2DQDelayStep)
1511 #endif
1512 #endif
1513 {
1514
1515 #if VENDER_JV_LOG || defined(RELEASE)
1516 #if EyeScan_Pic_draw_line_Mirror
1517 if (i <= ((EyeScan_Min_val + EyeScan_DelayCellPI_value) * delay_cell_ps / 100) && EyeScan_Index != 0)
1518 {
1519 EyeScan_Index--;
1520 EyeScan_Min_val = gEyeScan_Min[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
1521 EyeScan_Max_val = gEyeScan_Max[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
1522
1523 if (draw_type == EYESCAN_TYPE_TX)
1524 {
1525 EyeScan_Min_val += gEyeScan_MinMax_store_delay[u1BitIdx / 8];
1526 EyeScan_Max_val += gEyeScan_MinMax_store_delay[u1BitIdx / 8];
1527 }
1528
1529 if ((EyeScan_Max_val - EyeScan_Min_val + 1) > Final_EyeScan_winsize)
1530 {
1531 Final_EyeScan_Max_val = EyeScan_Max_val;
1532 Final_EyeScan_Min_val = EyeScan_Min_val;
1533 Final_EyeScan_winsize = (EyeScan_Max_val - EyeScan_Min_val + 1);
1534 }
1535
1536 }
1537 #endif
1538 #else
1539 #if EyeScan_Pic_draw_line_Mirror
1540 if (i == (EyeScan_Min_val) && EyeScan_Index != 0)
1541 {
1542 EyeScan_Index--;
1543 EyeScan_Min_val = gEyeScan_Min[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
1544 EyeScan_Max_val = gEyeScan_Max[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
1545
1546 if (draw_type == EYESCAN_TYPE_TX)
1547 {
1548 EyeScan_Min_val += gEyeScan_MinMax_store_delay[u1BitIdx / 8];
1549 EyeScan_Max_val += gEyeScan_MinMax_store_delay[u1BitIdx / 8];
1550 }
1551
1552 if ((EyeScan_Max_val - EyeScan_Min_val + 1) > Final_EyeScan_winsize)
1553 {
1554 Final_EyeScan_Max_val = EyeScan_Max_val;
1555 Final_EyeScan_Min_val = EyeScan_Min_val;
1556 Final_EyeScan_winsize = (EyeScan_Max_val - EyeScan_Min_val + 1);
1557 }
1558
1559 }
1560 #endif
1561 #endif
1562
1563 #if VENDER_JV_LOG || defined(RELEASE)
1564 if (i >= ((EyeScan_Min_val + EyeScan_DelayCellPI_value) * delay_cell_ps / 100) && i <= ((EyeScan_Max_val + EyeScan_DelayCellPI_value) * delay_cell_ps / 100))
1565 #else
1566 if (i >= (EyeScan_Min_val) && i <= (EyeScan_Max_val))
1567 #endif
1568 {
1569 #if !VENDER_JV_LOG && !defined(RELEASE)
1570 if ((i>=(FinalDQCaliDelay+EyeScan_DelayCellPI_value-(u2DQDelayStep/2)))&&(i<=(FinalDQCaliDelay+EyeScan_DelayCellPI_value+(u2DQDelayStep/2))))
1571 {
1572 if (gEye_Scan_color_flag)
1573 {
1574 mcSHOW_EYESCAN_MSG(("\033[0;105mH\033[m"));
1575 }
1576 else
1577 {
1578 mcSHOW_EYESCAN_MSG(("H"));
1579 }
1580 }
1581 else
1582 if ((local_VrefIdx >= local_Final_VrefIdx-(u2VrefStep/2))&&(local_VrefIdx <= local_Final_VrefIdx+(u2VrefStep/2)))
1583 {
1584 if (gEye_Scan_color_flag)
1585 {
1586 mcSHOW_EYESCAN_MSG(("\033[0;105mV\033[m"));
1587 }
1588 else
1589 {
1590 mcSHOW_EYESCAN_MSG(("V"));
1591 }
1592 }
1593 else
1594 if (local_VrefIdx <= local_Upper_Vcent && local_VrefIdx >= local_Lower_Vcent && i >= (FinalDQCaliDelay + EyeScan_DelayCellPI_value - pass_region_h_value) && i <= (FinalDQCaliDelay + EyeScan_DelayCellPI_value + pass_region_h_value))
1595 {
1596 if (gEye_Scan_color_flag)
1597 {
1598 mcSHOW_EYESCAN_MSG(("\033[0;103mQ\033[m"));
1599 }
1600 else
1601 {
1602 mcSHOW_EYESCAN_MSG(("Q"));
1603 }
1604 }
1605 else
1606 #endif
1607 {
1608 #if VENDER_JV_LOG || defined(RELEASE)
1609 if (gEye_Scan_color_flag)
1610 {
1611 mcSHOW_EYESCAN_MSG(("\033[0;102mO\033[m"));
1612 }
1613 else
1614 {
1615 mcSHOW_EYESCAN_MSG(("O"));
1616 }
1617 #else
1618 if (gEye_Scan_color_flag)
1619 {
1620 mcSHOW_EYESCAN_MSG(("\033[0;102mO\033[m"));
1621 }
1622 else
1623 {
1624 mcSHOW_EYESCAN_MSG(("O"));
1625 }
1626 #endif
1627 }
1628 }
1629 else
1630 {
1631 #if !VENDER_JV_LOG && !defined(RELEASE)
1632 #if EysScan_Pic_draw_1UI_line
1633 if (i == (int)(Max_EyeScan_Min_val) || i == (int)(Max_EyeScan_Min_val + PI_of_1_UI))
1634 {
1635 if (gEye_Scan_color_flag)
1636 {
1637 if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1 && p->dram_fsp == FSP_0 && draw_type==0 && u1VrefIdx < EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF)
1638 {
1639 mcSHOW_EYESCAN_MSG(("\033[0;107m \033[m"));
1640 }
1641 else
1642 {
1643 mcSHOW_EYESCAN_MSG(("\033[0;107m.\033[m"));
1644 }
1645 }
1646 else
1647 {
1648 if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1 && p->dram_fsp == FSP_0 && draw_type==0 && u1VrefIdx < EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF)
1649 {
1650 mcSHOW_EYESCAN_MSG((" "));
1651 }
1652 else
1653 {
1654 mcSHOW_EYESCAN_MSG(("."));
1655 }
1656 }
1657 }
1658 else
1659 #endif
1660 #endif
1661 {
1662
1663 #if VENDER_JV_LOG || defined(RELEASE)
1664 if (gEye_Scan_color_flag)
1665 {
1666 if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1 && p->dram_fsp == FSP_0 && draw_type==0 && u1VrefIdx < EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF)
1667 {
1668 mcSHOW_EYESCAN_MSG(("\033[0;100m \033[m"));
1669 }
1670 else
1671 {
1672 mcSHOW_EYESCAN_MSG(("\033[0;100m.\033[m"));
1673 }
1674 }
1675 else
1676 {
1677 if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1 && p->dram_fsp == FSP_0 && draw_type==0 && u1VrefIdx < EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF)
1678 {
1679 mcSHOW_EYESCAN_MSG((" "));
1680 }
1681 else
1682 {
1683 mcSHOW_EYESCAN_MSG(("."));
1684 }
1685 }
1686 #else
1687 if (gEye_Scan_color_flag)
1688 {
1689 if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1 && p->dram_fsp == FSP_0 && draw_type==0 && u1VrefIdx < EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF)
1690 {
1691 mcSHOW_EYESCAN_MSG(("\033[0;100m \033[m"));
1692 }
1693 else
1694 {
1695 mcSHOW_EYESCAN_MSG(("\033[0;100m.\033[m"));
1696 }
1697 }
1698 else
1699 {
1700 if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1 && p->dram_fsp == FSP_0 && draw_type==0 && u1VrefIdx < EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF)
1701 {
1702 mcSHOW_EYESCAN_MSG((" "));
1703 }
1704 else
1705 {
1706 mcSHOW_EYESCAN_MSG(("."));
1707 }
1708 }
1709 #endif
1710
1711 }
1712 }
1713 }
1714
1715
1716 #if EyeScan_Pic_draw_line_Mirror
1717 if (Final_EyeScan_Min_val != EYESCAN_DATA_INVALID && Final_EyeScan_Max_val != EYESCAN_DATA_INVALID)
1718 {
1719 #if !VENDER_JV_LOG && !defined(RELEASE)
1720 if (Final_EyeScan_Max_val > (FinalDQCaliDelay + EyeScan_DelayCellPI_value) && (FinalDQCaliDelay + EyeScan_DelayCellPI_value) > Final_EyeScan_Min_val)
1721 {
1722 mcSHOW_EYESCAN_MSG((" -%d ", (Final_EyeScan_Max_val - (FinalDQCaliDelay + EyeScan_DelayCellPI_value))));
1723 mcSHOW_EYESCAN_MSG(("%d ", ((FinalDQCaliDelay + EyeScan_DelayCellPI_value) - Final_EyeScan_Min_val)));
1724 }
1725 else if (Final_EyeScan_Max_val > (FinalDQCaliDelay + EyeScan_DelayCellPI_value) && Final_EyeScan_Min_val > (FinalDQCaliDelay + EyeScan_DelayCellPI_value))
1726 {
1727 mcSHOW_EYESCAN_MSG((" -%d ", (Final_EyeScan_Max_val - Final_EyeScan_Min_val)));
1728 mcSHOW_EYESCAN_MSG((" --- "));
1729 }
1730 else if ((FinalDQCaliDelay + EyeScan_DelayCellPI_value) > Final_EyeScan_Max_val && (FinalDQCaliDelay + EyeScan_DelayCellPI_value) > Final_EyeScan_Min_val)
1731 {
1732 mcSHOW_EYESCAN_MSG((" --- "));
1733 mcSHOW_EYESCAN_MSG(("%d ", (Final_EyeScan_Max_val - Final_EyeScan_Min_val)));
1734 }
1735 else
1736 {
1737 mcSHOW_EYESCAN_MSG((" --- "));
1738 mcSHOW_EYESCAN_MSG((" --- "));
1739 }
1740 #endif
1741
1742 #if VENDER_JV_LOG || defined(RELEASE)
1743 mcSHOW_EYESCAN_MSG(("%dps", Final_EyeScan_winsize * delay_cell_ps / 100));
1744 #else
1745 mcSHOW_EYESCAN_MSG(("%d", Final_EyeScan_winsize));
1746 #endif
1747 }
1748 #else
1749 if (Final_EyeScan_Max_val != Final_EyeScan_Min_val && Final_EyeScan_Max_val != EYESCAN_DATA_INVALID)
1750 {
1751 #if !VENDER_JV_LOG && !defined(RELEASE)
1752 if (Final_EyeScan_Max_val > (FinalDQCaliDelay + EyeScan_DelayCellPI_value) && (FinalDQCaliDelay + EyeScan_DelayCellPI_value) > Final_EyeScan_Min_val)
1753 {
1754 mcSHOW_EYESCAN_MSG((" -%d ", ((FinalDQCaliDelay + EyeScan_DelayCellPI_value) - Final_EyeScan_Min_val)));
1755 mcSHOW_EYESCAN_MSG(("%d ", (Final_EyeScan_Max_val - (FinalDQCaliDelay + EyeScan_DelayCellPI_value))));
1756 }
1757 else if (Final_EyeScan_Max_val > (FinalDQCaliDelay + EyeScan_DelayCellPI_value) && Final_EyeScan_Min_val > (FinalDQCaliDelay + EyeScan_DelayCellPI_value))
1758 {
1759 mcSHOW_EYESCAN_MSG((" --- "));
1760 mcSHOW_EYESCAN_MSG(("%d ", (Final_EyeScan_Max_val - Final_EyeScan_Min_val)));
1761 }
1762 else if ((FinalDQCaliDelay + EyeScan_DelayCellPI_value) > Final_EyeScan_Max_val && (FinalDQCaliDelay + EyeScan_DelayCellPI_value) > Final_EyeScan_Min_val)
1763 {
1764 mcSHOW_EYESCAN_MSG((" -%d ", (Final_EyeScan_Max_val - Final_EyeScan_Min_val)));
1765 mcSHOW_EYESCAN_MSG((" --- "));
1766 }
1767 else
1768 {
1769 mcSHOW_EYESCAN_MSG((" --- "));
1770 mcSHOW_EYESCAN_MSG((" --- "));
1771 }
1772 #endif
1773
1774 #if VENDER_JV_LOG || defined(RELEASE)
1775 mcSHOW_EYESCAN_MSG(("%dps", Final_EyeScan_winsize * delay_cell_ps / 100));
1776 #else
1777 mcSHOW_EYESCAN_MSG(("%d", Final_EyeScan_winsize));
1778 #endif
1779 }
1780 #endif
1781
1782 mcSHOW_EYESCAN_MSG(("\n"));
1783
1784
1785 }
1786
print_EYESCAN_LOG_message(DRAMC_CTX_T * p,U8 print_type)1787 void print_EYESCAN_LOG_message(DRAMC_CTX_T *p, U8 print_type)
1788 {
1789 U32 u1ChannelIdx = p->channel, u1RankIdx = p->rank;
1790 S8 u1VrefIdx;
1791 U8 u1VrefRange;
1792 U8 u1BitIdx, u1CA;
1793 U32 VdlVWTotal, VdlVWLow, VdlVWHigh, Vcent_DQ;
1794 U32 VdlVWHigh_Upper_Vcent = VREF_VOLTAGE_TABLE_NUM_LP4- 1, VdlVWHigh_Lower_Vcent = 0, VdlVWBest_Vcent = 0;
1795 U32 VdlVWHigh_Upper_Vcent_Range = 1, VdlVWHigh_Lower_Vcent_Range = 0, VdlVWBest_Vcent_Range = 1; ;
1796 U8 Upper_Vcent_pass_flag = 0, Lower_Vcent_pass_flag = 0;
1797 S32 i, vrefrange_i;
1798 U8 local_channel_num = 2;
1799 U8 SRAMIdx;
1800 U8 TXVrefRange = 0, CBTVrefRange = 0;
1801 U16 finalVref = 0, finalVrefRange = 0;
1802 S32 scan_vref_number = 0;
1803 U32 vddq;
1804 U8 Min_Value_1UI_Line;
1805 S8 EyeScan_Index;
1806 U8 cal_length = 0;
1807 U16 *pVref_Voltage_Table[VREF_VOLTAGE_TABLE_NUM_LP5];
1808 S16 EyeScan_DelayCellPI_value;
1809 U8 EyeScanVcent[10 + DQ_DATA_WIDTH * 2], max_winsize;
1810 U8 minEyeScanVcentUpperBound = 0xff, minEyeScanVcentUpperBound_bit = 0;
1811 U8 minEyeScanVcentLowerBound = 0xff, minEyeScanVcentLowerBound_bit = 0;
1812 U16 one_pi_ps = 100000000 / (DDRPhyGetRealFreq(p)* 2 * 32);
1813 U8 u1CBTEyeScanEnable, u1RXEyeScanEnable, u1TXEyeScanEnable;
1814
1815 U32 u2DQDelayEnd=0, u2TX_DQ_PreCal_LP4_Samll;
1816 S32 u2DQDelayBegin=0;
1817
1818 U8 u1ByteIdx, u1ByteIdx_Begin = 0, u1ByteIdx_End = 0;
1819
1820 U16 u2VrefStep=1;
1821
1822 local_channel_num = p->support_channel_num;
1823
1824 if (print_type == EYESCAN_TYPE_RX)
1825 {
1826 u2VrefStep = EYESCAN_GRAPH_RX_VREF_STEP;
1827
1828 if (p->odt_onoff==TRUE)
1829 {
1830 if (p->dram_type==TYPE_LPDDR5)
1831 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_T;
1832 else
1833 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_T;
1834 }
1835 else
1836 {
1837 if (p->dram_type==TYPE_LPDDR5)
1838 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_UT;
1839 else
1840 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_UT;
1841 }
1842 }
1843 else
1844 {
1845 u2VrefStep = EYESCAN_GRAPH_CATX_VREF_STEP;
1846
1847 if (p->dram_type == TYPE_LPDDR4)
1848 {
1849 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP4[VREF_RANGE_0];
1850 pVref_Voltage_Table[VREF_RANGE_1] = (U16 *)gVref_Voltage_Table_LP4[VREF_RANGE_1];
1851 }
1852 if (p->dram_type == TYPE_LPDDR4X)
1853 {
1854 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP4X[VREF_RANGE_0];
1855 pVref_Voltage_Table[VREF_RANGE_1] = (U16 *)gVref_Voltage_Table_LP4X[VREF_RANGE_1];
1856 }
1857 if (p->dram_type == TYPE_LPDDR5)
1858 {
1859 pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP5;
1860 }
1861 }
1862
1863 u1CBTEyeScanEnable = GetEyeScanEnable(p, EYESCAN_TYPE_CBT);
1864 u1RXEyeScanEnable = GetEyeScanEnable(p, EYESCAN_TYPE_RX);
1865 u1TXEyeScanEnable = GetEyeScanEnable(p, EYESCAN_TYPE_TX);
1866
1867 #if 0
1868 u1CBTEyeScanEnable = u1CBTEyeScanEnable & (p->channel == 0 && p->rank == 0);
1869 #endif
1870
1871 if (print_type == EYESCAN_TYPE_CBT)
1872 {
1873 if (p->frequency <= 934) VdlVWTotal = 17500;
1874 else if (p->frequency <= 1600) VdlVWTotal = 15500;
1875 else VdlVWTotal = 14500;
1876 }
1877 else
1878 {
1879 #if 0
1880 if (p->frequency <= 1600) VdlVWTotal = 10000;
1881 else VdlVWTotal = 10000;
1882 #else
1883 VdlVWTotal = 10000;
1884 #endif
1885 }
1886
1887 if (p->dram_type!=TYPE_LPDDR5)
1888 {
1889 CBTVrefRange = (u1MR12Value[p->channel][p->rank][p->dram_fsp] >> 6) & 1;
1890 TXVrefRange = (u1MR14Value[p->channel][p->rank][p->dram_fsp] >> 6) & 1;
1891 }
1892
1893 if (print_type == EYESCAN_TYPE_RX)
1894 {
1895 u1ByteIdx_Begin = 0;
1896 u1ByteIdx_End = 1;
1897 }
1898
1899 for (u1ByteIdx = u1ByteIdx_Begin; u1ByteIdx <= u1ByteIdx_End; u1ByteIdx++)
1900 {
1901
1902 #if 1 //#if !VENDER_JV_LOG && !defined(RELEASE)
1903 if ((print_type == EYESCAN_TYPE_CBT && u1CBTEyeScanEnable) || (print_type == EYESCAN_TYPE_RX && u1RXEyeScanEnable) || (print_type == EYESCAN_TYPE_TX && u1TXEyeScanEnable))
1904 {
1905 vddq = vGetVoltage(p, 2) / 1000;
1906 EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("VDDQ=%dmV\n", vddq));
1907
1908 if (print_type == EYESCAN_TYPE_CBT)
1909 {
1910 if (p->dram_type==TYPE_LPDDR5)
1911 {
1912 finalVref = u1MR12Value[u1ChannelIdx][u1RankIdx][p->dram_fsp];
1913 }
1914 else
1915 {
1916 finalVrefRange = u1MR12Value[u1ChannelIdx][u1RankIdx][p->dram_fsp]>>6;
1917 finalVref = u1MR12Value[u1ChannelIdx][u1RankIdx][p->dram_fsp]&0x3f;
1918 }
1919 cal_length = CATRAINING_NUM_LP4;
1920 }
1921 else if (print_type == EYESCAN_TYPE_RX)
1922 {
1923 finalVrefRange = 0;
1924 finalVref = gFinalRXVrefDQ[u1ChannelIdx][u1RankIdx][u1ByteIdx];
1925
1926 cal_length = DQS_BIT_NUMBER;
1927 }
1928 else//if (print_type==2)
1929 {
1930 if (p->dram_type==TYPE_LPDDR5)
1931 {
1932 finalVref = u1MR14Value[u1ChannelIdx][u1RankIdx][p->dram_fsp];
1933 }
1934 else
1935 {
1936 finalVrefRange = u1MR14Value[u1ChannelIdx][u1RankIdx][p->dram_fsp]>>6;
1937 finalVref = u1MR14Value[u1ChannelIdx][u1RankIdx][p->dram_fsp]&0x3f;
1938 }
1939
1940 cal_length = p->data_width;
1941 }
1942
1943
1944 EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("%s Window\n", print_EYESCAN_LOG_type(print_type)));
1945
1946 EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("%s Channel%d ", print_EYESCAN_LOG_type(print_type), u1ChannelIdx));
1947 if (print_type == EYESCAN_TYPE_RX)
1948 {
1949 mcSHOW_DBG_MSG(("Final_Vref Byte%d Vcent %d(%dmV(X100))\n",
1950 u1ByteIdx,
1951 finalVref,
1952 pVref_Voltage_Table[finalVrefRange][finalVref]));
1953
1954 Vcent_DQ = pVref_Voltage_Table[finalVrefRange][finalVref];
1955 }
1956 else
1957 {
1958 mcSHOW_DBG_MSG(("Range %d Final_Vref Vcent=%d(%dmV(X100))\n",
1959 finalVrefRange,
1960 finalVref,
1961 pVref_Voltage_Table[finalVrefRange][finalVref] * vddq / 100));
1962
1963 Vcent_DQ = pVref_Voltage_Table[finalVrefRange][finalVref] * vddq / 100;
1964 }
1965
1966
1967
1968 if (print_type == EYESCAN_TYPE_RX)
1969 {
1970 VdlVWHigh_Upper_Vcent_Range = 0;
1971 VdlVWHigh_Upper_Vcent = RX_VREF_RANGE_END-1;
1972 vrefrange_i = 0;
1973 scan_vref_number = RX_VREF_RANGE_END;
1974 }
1975 else
1976 {
1977 if (p->dram_type==TYPE_LPDDR5)
1978 {
1979 VdlVWHigh_Upper_Vcent_Range = 0;
1980 VdlVWHigh_Upper_Vcent = VREF_VOLTAGE_TABLE_NUM_LP5-1;
1981 vrefrange_i = 0;
1982 scan_vref_number = VREF_VOLTAGE_TABLE_NUM_LP5;
1983 }
1984 else
1985 {
1986 VdlVWHigh_Upper_Vcent_Range = 1;
1987 VdlVWHigh_Upper_Vcent = VREF_VOLTAGE_TABLE_NUM_LP4-1;
1988 vrefrange_i = finalVrefRange;
1989 scan_vref_number = VREF_VOLTAGE_TABLE_NUM_LP4;
1990 }
1991 }
1992 for (i = finalVref; i < scan_vref_number; i += u2VrefStep)
1993 {
1994 if (print_type == EYESCAN_TYPE_RX||(print_type != EYESCAN_TYPE_RX&&p->dram_type==TYPE_LPDDR5))
1995 {
1996 if (pVref_Voltage_Table[vrefrange_i][i] - Vcent_DQ >= VdlVWTotal / 2)
1997 {
1998
1999 VdlVWHigh_Upper_Vcent = i;
2000 break;
2001 }
2002 }
2003 else
2004 {
2005 if (((pVref_Voltage_Table[vrefrange_i][i] * vddq / 100 - Vcent_DQ)) >= VdlVWTotal / 2)
2006 {
2007
2008 VdlVWHigh_Upper_Vcent = i;
2009 VdlVWHigh_Upper_Vcent_Range = vrefrange_i;
2010 break;
2011 }
2012 if (i == (VREF_VOLTAGE_TABLE_NUM_LP4- 1) && vrefrange_i == 0)
2013 {
2014 vrefrange_i = 1;
2015 i = 20;
2016 }
2017 }
2018 }
2019
2020 EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("%s VdlVWHigh_Upper ", print_EYESCAN_LOG_type(print_type)));
2021 if (print_type != EYESCAN_TYPE_RX)
2022 {
2023 mcSHOW_DBG_MSG(("Range=%d ", VdlVWHigh_Upper_Vcent_Range));
2024 mcSHOW_DBG_MSG(("Vcent=%d(%dmV(X100))\n",
2025 VdlVWHigh_Upper_Vcent,
2026 pVref_Voltage_Table[VdlVWHigh_Upper_Vcent_Range][VdlVWHigh_Upper_Vcent] * vddq / 100));
2027 }
2028 else
2029 {
2030 mcSHOW_DBG_MSG(("Byte%d ", u1ByteIdx));
2031 mcSHOW_DBG_MSG(("Vcent=%d(%dmV(X100))\n",
2032 VdlVWHigh_Upper_Vcent,
2033 pVref_Voltage_Table[VdlVWHigh_Upper_Vcent_Range][VdlVWHigh_Upper_Vcent]));
2034 }
2035
2036
2037
2038 VdlVWHigh_Lower_Vcent_Range = 0;
2039 VdlVWHigh_Lower_Vcent = 0;
2040 vrefrange_i = finalVrefRange;
2041 for (i = (finalVref); i >= 0; i -= u2VrefStep)
2042 {
2043 if (print_type == EYESCAN_TYPE_RX||(print_type != EYESCAN_TYPE_RX&&p->dram_type==TYPE_LPDDR5))
2044 {
2045 if (Vcent_DQ - pVref_Voltage_Table[vrefrange_i][i] >= VdlVWTotal / 2)
2046 {
2047
2048 VdlVWHigh_Lower_Vcent = i;
2049 break;
2050 }
2051 }
2052 else
2053 {
2054 if (((Vcent_DQ - pVref_Voltage_Table[vrefrange_i][i] * vddq / 100)) >= VdlVWTotal / 2)
2055 {
2056
2057 VdlVWHigh_Lower_Vcent = i;
2058 VdlVWHigh_Lower_Vcent_Range = vrefrange_i;
2059 break;
2060 }
2061 if (i <= 21 && vrefrange_i == 1)
2062 {
2063 vrefrange_i = 0;
2064 i = VREF_VOLTAGE_TABLE_NUM_LP4- (21 - i);
2065 }
2066 }
2067 }
2068
2069 EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("%s VdlVWHigh_Lower ", print_EYESCAN_LOG_type(print_type)));
2070 if (print_type != EYESCAN_TYPE_RX)
2071 {
2072 mcSHOW_DBG_MSG(("Range=%d ", VdlVWHigh_Lower_Vcent_Range));
2073 mcSHOW_DBG_MSG(("Vcent=%d(%dmV(X100))\n",
2074 VdlVWHigh_Lower_Vcent,
2075 pVref_Voltage_Table[VdlVWHigh_Lower_Vcent_Range][VdlVWHigh_Lower_Vcent] * vddq / 100));
2076 }
2077 else
2078 {
2079 mcSHOW_DBG_MSG(("Byte%d ", u1ByteIdx));
2080 mcSHOW_DBG_MSG(("Vcent=%d(%dmV(X100))\n",
2081 VdlVWHigh_Lower_Vcent,
2082 pVref_Voltage_Table[VdlVWHigh_Lower_Vcent_Range][VdlVWHigh_Lower_Vcent]));
2083 }
2084
2085
2086 #ifdef FOR_HQA_TEST_USED
2087 EyeScanVcent[0] = finalVrefRange;
2088 EyeScanVcent[1] = finalVref;
2089 EyeScanVcent[2] = VdlVWHigh_Upper_Vcent_Range;
2090 EyeScanVcent[3] = VdlVWHigh_Upper_Vcent;
2091 EyeScanVcent[4] = VdlVWHigh_Lower_Vcent_Range;
2092 EyeScanVcent[5] = VdlVWHigh_Lower_Vcent;
2093 #endif
2094
2095 SRAMIdx = vGet_Current_SRAMIdx(p);
2096
2097 #ifdef FOR_HQA_REPORT_USED
2098 if (print_type == EYESCAN_TYPE_RX)
2099 {
2100 EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("delay cell %d/100ps\n", gHQALOG_RX_delay_cell_ps_075V));
2101 }
2102 #endif
2103
2104 // EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("delay cell %d/100ps\n", u2gdelay_cell_ps_all[SRAMIdx][u1ChannelIdx]));
2105
2106 for (u1BitIdx = u1ByteIdx * DQS_BIT_NUMBER; u1BitIdx < (u1ByteIdx * DQS_BIT_NUMBER + cal_length); u1BitIdx++)
2107 {
2108 if (print_type != EYESCAN_TYPE_RX)
2109 {
2110
2111 for (u1VrefIdx = finalVref + finalVrefRange * 30; u1VrefIdx <= (S8)(VdlVWHigh_Upper_Vcent + VdlVWHigh_Upper_Vcent_Range * 30); u1VrefIdx += u2VrefStep)
2112 {
2113 Upper_Vcent_pass_flag = 0;
2114 for (EyeScan_Index = 0; EyeScan_Index < EYESCAN_BROKEN_NUM; EyeScan_Index++)
2115 {
2116 if (gEyeScan_Min[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] != EYESCAN_DATA_INVALID && gEyeScan_Max[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] != EYESCAN_DATA_INVALID)
2117 if ((print_type == EYESCAN_TYPE_CBT && ((((gEyeScan_CaliDelay[0] + gEyeScan_DelayCellPI[u1BitIdx]) - gEyeScan_Min[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index]) >= 3) && ((gEyeScan_Max[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] - (gEyeScan_CaliDelay[0] + gEyeScan_DelayCellPI[u1BitIdx])) >= 3))) ||
2118 (print_type == EYESCAN_TYPE_TX && ((((gEyeScan_CaliDelay[u1BitIdx / 8] + gEyeScan_DelayCellPI[u1BitIdx]) - (gEyeScan_Min[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] + gEyeScan_MinMax_store_delay[u1BitIdx / 8])) >= 3) && (((gEyeScan_Max[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] + gEyeScan_MinMax_store_delay[u1BitIdx / 8]) - (gEyeScan_CaliDelay[u1BitIdx / 8] + gEyeScan_DelayCellPI[u1BitIdx])) >= 3 ))))
2119 {
2120 Upper_Vcent_pass_flag = 1;
2121 }
2122 }
2123 if (Upper_Vcent_pass_flag == 0) break;
2124 }
2125 for (u1VrefIdx = VdlVWHigh_Lower_Vcent + VdlVWHigh_Lower_Vcent_Range * 30; u1VrefIdx <= (S8)(finalVref + finalVrefRange * 30); u1VrefIdx += u2VrefStep)
2126 {
2127 Lower_Vcent_pass_flag = 0;
2128 for (EyeScan_Index = 0; EyeScan_Index < EYESCAN_BROKEN_NUM; EyeScan_Index++)
2129 {
2130 if (gEyeScan_Min[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] != EYESCAN_DATA_INVALID && gEyeScan_Max[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] != EYESCAN_DATA_INVALID)
2131 if ((print_type == EYESCAN_TYPE_CBT && ((((gEyeScan_CaliDelay[0] + gEyeScan_DelayCellPI[u1BitIdx]) - gEyeScan_Min[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index]) >= 3) && ((gEyeScan_Max[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] - (gEyeScan_CaliDelay[0] + gEyeScan_DelayCellPI[u1BitIdx])) >= 3))) ||
2132 (print_type == EYESCAN_TYPE_TX && ((((gEyeScan_CaliDelay[u1BitIdx / 8] + gEyeScan_DelayCellPI[u1BitIdx]) - (gEyeScan_Min[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] + gEyeScan_MinMax_store_delay[u1BitIdx / 8])) >= 3) && (((gEyeScan_Max[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] + gEyeScan_MinMax_store_delay[u1BitIdx / 8]) - (gEyeScan_CaliDelay[u1BitIdx / 8] + gEyeScan_DelayCellPI[u1BitIdx])) >= 3 ))))
2133 {
2134 Lower_Vcent_pass_flag = 1;
2135 }
2136 }
2137 if (Lower_Vcent_pass_flag == 0) break;
2138 }
2139 }
2140
2141 #ifdef FOR_HQA_TEST_USED
2142
2143 VdlVWBest_Vcent_Range = 1;
2144 VdlVWBest_Vcent = VREF_VOLTAGE_TABLE_NUM_LP4- 1;
2145 if (print_type == EYESCAN_TYPE_RX||(print_type != EYESCAN_TYPE_RX&&p->dram_type==TYPE_LPDDR5)) vrefrange_i = 0;
2146 else vrefrange_i = 1;
2147 max_winsize = 0;
2148 for (i = ((scan_vref_number-1) - ((scan_vref_number-1)%u2VrefStep)); i >= 0; i -= u2VrefStep)
2149 {
2150 if (gEyeScan_WinSize[(i + vrefrange_i * 30) / u2VrefStep][u1BitIdx] > max_winsize)
2151 {
2152 max_winsize = gEyeScan_WinSize[(i + vrefrange_i * 30) / u2VrefStep][u1BitIdx];
2153 VdlVWBest_Vcent_Range = vrefrange_i;
2154 VdlVWBest_Vcent = i;
2155 }
2156 if (print_type != EYESCAN_TYPE_RX && i == 21 && vrefrange_i == 1)
2157 {
2158 vrefrange_i = 0;
2159 i = VREF_VOLTAGE_TABLE_NUM_LP4;
2160 }
2161 }
2162
2163 if (print_type == EYESCAN_TYPE_RX)
2164 {
2165 EyeScanVcent[10 + u1BitIdx] = VdlVWBest_Vcent;
2166 }
2167 else
2168 {
2169 EyeScanVcent[10 + u1BitIdx * 2] = VdlVWBest_Vcent_Range;
2170 EyeScanVcent[10 + u1BitIdx * 2 + 1] = VdlVWBest_Vcent;
2171 }
2172 #endif
2173
2174 if (print_type == EYESCAN_TYPE_RX)
2175 {
2176 #ifdef FOR_HQA_REPORT_USED
2177 EYESCAN_LOG_Print_Prefix_String(); HQA_LOG_Print_Freq_String(p); mcSHOW_DBG_MSG(("Channel%d Rank%d Bit%d(DRAM DQ%d)\tHigher VdlTW=%d/100ps\tLower VdlTW=%d/100ps\n",
2178 u1ChannelIdx,
2179 u1RankIdx,
2180 u1BitIdx,
2181 uiLPDDR4_O1_Mapping_POP[p->channel][u1BitIdx],
2182 gEyeScan_WinSize[VdlVWHigh_Upper_Vcent / u2VrefStep][u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V,
2183 gEyeScan_WinSize[VdlVWHigh_Lower_Vcent / u2VrefStep][u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V
2184 ));
2185 #endif
2186 }
2187 else
2188 {
2189 EYESCAN_LOG_Print_Prefix_String(); HQA_LOG_Print_Freq_String(p); mcSHOW_DBG_MSG(("Channel%d Rank%d %s%d",
2190 u1ChannelIdx,
2191 u1RankIdx,
2192 print_type == EYESCAN_TYPE_CBT? "CA" : "Bit",
2193 u1BitIdx
2194 ));
2195 if (print_type == EYESCAN_TYPE_TX)
2196 {
2197 mcSHOW_DBG_MSG(("(DRAM DQ%d)", uiLPDDR4_O1_Mapping_POP[p->channel][u1BitIdx]));
2198 }
2199 mcSHOW_DBG_MSG(("\tHigher VdlTW=%dPI(%d/100ps)(%s)\tLower VdlTW=%dpi(%d/100ps)(%s)\n",
2200 gEyeScan_WinSize[(VdlVWHigh_Upper_Vcent + VdlVWHigh_Upper_Vcent_Range * 30) / u2VrefStep][u1BitIdx],
2201 gEyeScan_WinSize[(VdlVWHigh_Upper_Vcent + VdlVWHigh_Upper_Vcent_Range * 30) / u2VrefStep][u1BitIdx] * one_pi_ps,
2202 Upper_Vcent_pass_flag == 1? "PASS" : "WARNING",
2203 gEyeScan_WinSize[(VdlVWHigh_Lower_Vcent + VdlVWHigh_Lower_Vcent_Range * 30) / u2VrefStep][u1BitIdx],
2204 gEyeScan_WinSize[(VdlVWHigh_Lower_Vcent + VdlVWHigh_Lower_Vcent_Range * 30) / u2VrefStep][u1BitIdx] * one_pi_ps,
2205 Lower_Vcent_pass_flag == 1? "PASS" : "WARNING"
2206 ));
2207 }
2208
2209 if (gEyeScan_WinSize[(VdlVWHigh_Upper_Vcent + VdlVWHigh_Upper_Vcent_Range * 30) / u2VrefStep][u1BitIdx] < minEyeScanVcentUpperBound)
2210 {
2211 minEyeScanVcentUpperBound = gEyeScan_WinSize[(VdlVWHigh_Upper_Vcent + VdlVWHigh_Upper_Vcent_Range * 30) / u2VrefStep][u1BitIdx];
2212 minEyeScanVcentUpperBound_bit = u1BitIdx;
2213 }
2214 if (gEyeScan_WinSize[(VdlVWHigh_Lower_Vcent + VdlVWHigh_Lower_Vcent_Range * 30) / u2VrefStep][u1BitIdx] < minEyeScanVcentLowerBound)
2215 {
2216 minEyeScanVcentLowerBound = gEyeScan_WinSize[(VdlVWHigh_Lower_Vcent + VdlVWHigh_Lower_Vcent_Range * 30) / u2VrefStep][u1BitIdx];
2217 minEyeScanVcentLowerBound_bit = u1BitIdx;
2218 }
2219 }
2220 #ifdef FOR_HQA_TEST_USED
2221 #ifdef FOR_HQA_REPORT_USED
2222 print_EyeScanVcent_for_HQA_report_used(p, print_type, u1ChannelIdx, u1RankIdx, u1ByteIdx, EyeScanVcent, minEyeScanVcentUpperBound, minEyeScanVcentUpperBound_bit, minEyeScanVcentLowerBound, minEyeScanVcentLowerBound_bit);
2223 #endif
2224 #endif
2225 }
2226
2227
2228 #endif
2229
2230
2231 if ((print_type == EYESCAN_TYPE_CBT && u1CBTEyeScanEnable) || (print_type == EYESCAN_TYPE_RX && u1RXEyeScanEnable) || (print_type == EYESCAN_TYPE_TX && u1TXEyeScanEnable))
2232 { U8 space_num;
2233
2234 mcSHOW_DBG_MSG(("\n\n"));
2235
2236 if (print_type == EYESCAN_TYPE_CBT )
2237 {
2238 u2DQDelayBegin = 0;
2239 u2DQDelayEnd = 64+20;
2240
2241 space_num = 8 + one_pi_ps * 32 / 1000;
2242 }
2243 else if (print_type == EYESCAN_TYPE_RX)
2244 {
2245 u2DQDelayBegin = gEyeScan_Min[(finalVref) / EYESCAN_GRAPH_RX_VREF_STEP][0][0]-32;
2246 u2DQDelayEnd = gEyeScan_Max[(finalVref) / EYESCAN_GRAPH_RX_VREF_STEP][0][0]+32;
2247
2248 space_num = 8 + one_pi_ps * 32 / 1000;
2249 }
2250 else// if (print_type==2)
2251 {
2252 if (gEyeScan_CaliDelay[0] < gEyeScan_CaliDelay[1])
2253 u2DQDelayBegin = gEyeScan_CaliDelay[0] - 24;
2254 else
2255 u2DQDelayBegin = gEyeScan_CaliDelay[1] - 24;
2256
2257 u2DQDelayEnd = u2DQDelayBegin + 64;
2258
2259 space_num = 15 + u2DQDelayEnd - u2DQDelayBegin + 2;
2260 }
2261
2262 for (u1BitIdx = u1ByteIdx * DQS_BIT_NUMBER; u1BitIdx < (u1ByteIdx * DQS_BIT_NUMBER + cal_length); u1BitIdx++)
2263 {
2264 EyeScan_Index = 0;
2265
2266 if (print_type == EYESCAN_TYPE_RX)
2267 {
2268 Min_Value_1UI_Line = gEyeScan_DelayCellPI[u1BitIdx] - 16;
2269
2270 EYESCAN_LOG_Print_Prefix_String(); mcSHOW_EYESCAN_MSG(("RX EYESCAN Channel%d, Rank%d, DQ%d ===\n", p->channel, p->rank, u1BitIdx));
2271 }
2272 else
2273 {
2274 #if EyeScan_Pic_draw_line_Mirror
2275 EyeScan_DelayCellPI_value = 0 - gEyeScan_DelayCellPI[u1BitIdx];
2276 #else
2277 EyeScan_DelayCellPI_value = gEyeScan_DelayCellPI[u1BitIdx];
2278 #endif
2279 Min_Value_1UI_Line = gEyeScan_CaliDelay[u1BitIdx / 8] - 16 - EyeScan_DelayCellPI_value;
2280
2281 EYESCAN_LOG_Print_Prefix_String(); mcSHOW_EYESCAN_MSG(("%s EYESCAN Channel%d, Rank%d, Bit%d", print_type==EYESCAN_TYPE_CBT ? "CBT" : "TX DQ", p->channel, p->rank, u1BitIdx));
2282 if (print_type == EYESCAN_TYPE_TX)
2283 {
2284 mcSHOW_EYESCAN_MSG(("(DRAM DQ%d)", uiLPDDR4_O1_Mapping_POP[p->channel][u1BitIdx]));
2285 }
2286 mcSHOW_EYESCAN_MSG((" ===\n"));
2287 }
2288
2289
2290 #if VENDER_JV_LOG
2291 for (i = 0; i < 8 + one_pi_ps * 32 / 1000; i++) mcSHOW_EYESCAN_MSG((" "));
2292 mcSHOW_EYESCAN_MSG(("window\n"));
2293 #else
2294 for (i = 0; i < space_num; i++) mcSHOW_EYESCAN_MSG((" "));
2295 mcSHOW_EYESCAN_MSG(("first last window\n"));
2296 mcSHOW_EYESCAN_MSG(("Vref Step: %d, Delay Step: %d\n",u2VrefStep, (print_type==EYESCAN_TYPE_RX)?4:1));
2297
2298 #endif
2299
2300 if (print_type == EYESCAN_TYPE_RX||(print_type != EYESCAN_TYPE_RX&&p->dram_type==TYPE_LPDDR5)) u1VrefRange = VREF_RANGE_0;
2301 else u1VrefRange = VREF_RANGE_1;
2302
2303 for (u1VrefIdx = ((scan_vref_number-1) - ((scan_vref_number-1)%u2VrefStep)); u1VrefIdx >= 0; u1VrefIdx -= u2VrefStep)
2304 {
2305 EyeScan_Pic_draw_line(p, print_type, u1VrefRange, u1VrefIdx, u1BitIdx, u2DQDelayBegin, u2DQDelayEnd, finalVrefRange, finalVref, VdlVWHigh_Upper_Vcent_Range, VdlVWHigh_Upper_Vcent, VdlVWHigh_Lower_Vcent_Range, VdlVWHigh_Lower_Vcent, gEyeScan_CaliDelay[u1BitIdx / 8], gEyeScan_DelayCellPI[u1BitIdx], one_pi_ps, Min_Value_1UI_Line);
2306
2307 if (print_type != EYESCAN_TYPE_RX && u1VrefRange == VREF_RANGE_1 && u1VrefIdx == 20)
2308 {
2309 u1VrefRange = VREF_RANGE_0;
2310 u1VrefIdx = VREF_VOLTAGE_TABLE_NUM_LP4-1;
2311 }
2312 }
2313
2314 mcSHOW_EYESCAN_MSG(("\n\n"));
2315
2316 }
2317 }
2318 }
2319 }
2320
2321
2322 #ifdef RELEASE
2323 #undef mcSHOW_DBG_MSG
2324 #define mcSHOW_DBG_MSG(_x_)
2325 #endif
2326 #endif
2327
2328 #if PIN_CHECK_TOOL
2329 #define CA_THRESHOLD 20
2330 #define RX_THRESHOLD 150
2331 #define TX_THRESHOLD 20
2332 #define PERCENTAGE_THRESHOLD 50
2333 #define PRINT_WIN_SIZE 0
2334 DEBUG_PIN_INF_FOR_FLASHTOOL_T PINInfo_flashtool;
print_Impedence_LOG_type(U8 print_type)2335 static U8* print_Impedence_LOG_type(U8 print_type)
2336 {
2337 switch (print_type)
2338 {
2339 case 0: return "DRVP";
2340 case 1: return "DRVN";
2341 case 2: return "ODTP";
2342 case 3: return "ODTN";
2343 default: return "ERROR";
2344 }
2345 }
vPrintPinInfoResult(DRAMC_CTX_T * p)2346 void vPrintPinInfoResult(DRAMC_CTX_T *p)
2347 {
2348 U8 u1CHIdx, u1RankIdx, u1CAIdx, u1ByteIdx, u1ByteIdx_DQ, u1BitIdx, u1BitIdx_DQ, u1FreqRegionIdx, u1ImpIdx;
2349 U8 u1PinError=0;
2350
2351 mcSHOW_DBG_MSG3(("\n\n[Pin Info Summary] Freqency %d\n", p->frequency));
2352
2353 for (u1FreqRegionIdx=0;u1FreqRegionIdx<2;u1FreqRegionIdx++)
2354 {
2355 for (u1ImpIdx=0;u1ImpIdx<IMP_DRV_MAX;u1ImpIdx++)
2356 {
2357 mcSHOW_DBG_MSG3(("IMP %s type:%s %s\n", u1FreqRegionIdx?"Region1":"Region0", print_Impedence_LOG_type(u1ImpIdx), ((PINInfo_flashtool.IMP_ERR_FLAG>>(u1FreqRegionIdx*4+u1ImpIdx)&0x1)?"ERROR":"PASS")));
2358 }
2359 }
2360
2361 //for(ucFreqIdx=SRAM_SHU0; ucFreqIdx<DRAM_DFS_SRAM_MAX; ucFreqIdx++)
2362 {
2363 //mcSHOW_DBG_MSG(("==Freqency = %d==\n", get_FreqTbl_by_SRAMIndex(p,ucFreqIdx)->frequency));
2364 for(u1CHIdx=0; u1CHIdx<p->support_channel_num; u1CHIdx++)
2365 {
2366 for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++)
2367 {
2368 mcSHOW_DBG_MSG3(("CH %d, Rank %d\n", u1CHIdx, u1RankIdx));
2369
2370
2371 for (u1CAIdx =0; u1CAIdx <CATRAINING_NUM_LP4; u1CAIdx++)
2372 {
2373 #if 1
2374 PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]= (PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]* 100 + 63) /64;
2375 if ((PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]==0)||(PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]<=PERCENTAGE_THRESHOLD))
2376 #else
2377 if ((PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]==0)||(PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]<=CA_THRESHOLD))
2378 #endif
2379 {
2380 PINInfo_flashtool.CA_ERR_FLAG[u1CHIdx][u1RankIdx] |= (1<<u1CAIdx);
2381 PINInfo_flashtool.TOTAL_ERR |= (0x1<<(u1CHIdx*4+u1RankIdx*2));
2382 }
2383 mcSHOW_DBG_MSG3(("CA %d: %s ", u1CAIdx, ((PINInfo_flashtool.CA_ERR_FLAG[u1CHIdx][u1RankIdx]>>u1CAIdx)&0x1)?"ERROR":"PASS"));
2384 #if PRINT_WIN_SIZE
2385 mcSHOW_DBG_MSG3(("(WIN_SIZE: %d %% )", (PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx])));
2386 #endif
2387 mcSHOW_DBG_MSG3(("\n"));
2388
2389 }
2390
2391
2392 for (u1BitIdx =0; u1BitIdx <DQ_DATA_WIDTH; u1BitIdx++)
2393 {
2394 u1ByteIdx = (u1BitIdx>=8?1:0);
2395 u1BitIdx_DQ = uiLPDDR4_O1_Mapping_POP[p->channel][u1BitIdx];
2396 u1ByteIdx_DQ = (u1BitIdx_DQ>=8?1:0);
2397
2398
2399 #if 1
2400 PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx] = ((PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]* gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p)* 2)+ (1000000 - 1)) / 1000000;
2401 if (PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=PERCENTAGE_THRESHOLD)
2402 #else
2403 if ((PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]==0)||(PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=RX_THRESHOLD)\
2404 ||(PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]==0)||(PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=TX_THRESHOLD))
2405 #endif
2406 {
2407 PINInfo_flashtool.DQ_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] |= (1<<(u1BitIdx-(u1ByteIdx==1?8:0)));
2408 PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ] |= (1<<(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0)));
2409 PINInfo_flashtool.TOTAL_ERR |= (0x1<<(u1CHIdx*4+u1RankIdx*2+1));
2410 }
2411
2412
2413 #if 1
2414 PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx] = (PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]* 100+ (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 63: 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 64: 32);
2415 if (PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=PERCENTAGE_THRESHOLD)
2416 #else
2417 if ((PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]==0)||(PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=RX_THRESHOLD)\
2418 ||(PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]==0)||(PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=TX_THRESHOLD))
2419 #endif
2420 {
2421 PINInfo_flashtool.DQ_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] |= (1<<(u1BitIdx-(u1ByteIdx==1?8:0)));
2422 PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ] |= (1<<(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0)));
2423 PINInfo_flashtool.TOTAL_ERR |= (0x1<<(u1CHIdx*4+u1RankIdx*2+1));
2424 }
2425
2426 //mcSHOW_DBG_MSG(("bit %d(DRAM DQ %d): %s ", u1BitIdx, uiLPDDR4_O1_Mapping_POP[p->channel][u1BitIdx], ((PINInfo_flashtool.DQ_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]>>u1BitIdx)&0x1)?"ERROR":"PASS"));
2427 //mcSHOW_DBG_MSG(("(RX WIN SIZE: %d, TX WIN SIZE: %d)", PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx], PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]));
2428 //mcSHOW_DBG_MSG(("\n"));
2429 }
2430 for (u1BitIdx_DQ=0; u1BitIdx_DQ<DQ_DATA_WIDTH; u1BitIdx_DQ++)
2431 {
2432 u1ByteIdx_DQ = (u1BitIdx_DQ>=8?1:0);
2433 mcSHOW_DBG_MSG3(("DRAM DQ %d: RX %s, TX %s ", u1BitIdx_DQ, (((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ]>>(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0)))&0x1)?"ERROR":"PASS"),\
2434 (((PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ]>>(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0)))&0x1)?"ERROR":"PASS")));
2435 #if PRINT_WIN_SIZE
2436 mcSHOW_DBG_MSG3(("(RX WIN SIZE: %d %%, TX WIN SIZE: %d %% )", PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][uiLPDDR4_O1_Mapping_POP[u1CHIdx][u1BitIdx_DQ]], PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][uiLPDDR4_O1_Mapping_POP[u1CHIdx][u1BitIdx_DQ]]));
2437 #endif
2438 mcSHOW_DBG_MSG3(("\n"));
2439 }
2440 }
2441 }
2442 }
2443 }
2444
vGetErrorTypeResult(DRAMC_CTX_T * p)2445 void vGetErrorTypeResult(DRAMC_CTX_T *p)
2446 {
2447 U8 u1CHIdx, u1CHIdx_EMI, u1RankIdx, u1CAIdx, u1ByteIdx, u1BitIdx, u1FreqRegionIdx, u1ImpIdx;
2448
2449
2450 mcSHOW_DBG_MSG3(("\n[Get Pin Error Type Result]\n"));
2451
2452
2453 if (PINInfo_flashtool.TOTAL_ERR==0 && PINInfo_flashtool.IMP_ERR_FLAG==0)
2454 {
2455 mcSHOW_DBG_MSG3(("ALL PASS\n"));
2456 }
2457
2458
2459 if (PINInfo_flashtool.IMP_ERR_FLAG)
2460 {
2461 mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: Impedance calibration fail\n"));
2462 mcSHOW_DBG_MSG3(("Suspect EXTR contact issue\n"));
2463 mcSHOW_DBG_MSG3(("Suspect EXTR related resistor contact issue\n"));
2464 }
2465
2466
2467 if ((PINInfo_flashtool.TOTAL_ERR == 0xffff) && (PINInfo_flashtool.WL_ERR_FLAG== 0xff))
2468 {
2469 mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: ALL calibration fail\n"));
2470 mcSHOW_DBG_MSG3(("Suspect RESET_N contact issue\n"));
2471 mcSHOW_DBG_MSG3(("Suspect DRAM Power (VDD1/VDD2/VDDQ) contact issue\n"));
2472 }
2473 else
2474 {
2475 for (u1CHIdx = 0; u1CHIdx < p->support_channel_num; u1CHIdx++)
2476 {
2477 #if (CHANNEL_NUM > 2)
2478 if (channel_num_auxadc > 2) {
2479 if(u1CHIdx == CHANNEL_B)
2480 u1CHIdx_EMI = CHANNEL_C;
2481 else if(u1CHIdx == CHANNEL_C)
2482 u1CHIdx_EMI = CHANNEL_B;
2483 else
2484 }
2485 #endif
2486 u1CHIdx_EMI = u1CHIdx;
2487
2488
2489 if ((PINInfo_flashtool.TOTAL_ERR>>(u1CHIdx*4) & 0xf) == 0xf)
2490 {
2491 mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: CH%d all calibration fail\n",u1CHIdx));
2492 mcSHOW_DBG_MSG3(("Suspect EMI%d_CK_T contact issue\n",u1CHIdx_EMI));
2493 mcSHOW_DBG_MSG3(("Suspect EMI%d_CK_C contact issue\n",u1CHIdx_EMI));
2494 for (u1CAIdx =0; u1CAIdx <CATRAINING_NUM_LP4; u1CAIdx++)
2495 {
2496 mcSHOW_DBG_MSG(("Suspect EMI%d_CA%d contact issue\n",u1CHIdx_EMI,u1CAIdx));
2497 }
2498 }
2499 else
2500 {
2501 for(u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)
2502 {
2503
2504 if ((((PINInfo_flashtool.TOTAL_ERR>>(u1CHIdx*4+u1RankIdx*2)) & 0x3)==0x3) && \
2505 (PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_0] == 0xff) && \
2506 (PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_1] == 0xff)&& \
2507 (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_0] == 0xff) && \
2508 (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_1] == 0xff))
2509 {
2510 mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: CH%d RK%d all calibration fail\n",u1CHIdx,u1RankIdx));
2511 mcSHOW_DBG_MSG3(("Suspect EMI%d_CKE_%d contact issue\n",u1CHIdx_EMI,u1RankIdx));
2512 mcSHOW_DBG_MSG3(("Suspect EMI%d_CS_%d contact issue\n",u1CHIdx_EMI,u1RankIdx));
2513 }
2514 else
2515 {
2516 for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
2517 {
2518
2519 if((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff) &&\
2520 (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff))
2521 {
2522 mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: CH%d RK%d Byte%d WL/Read/Write calibration fail\n",u1CHIdx,u1RankIdx,u1ByteIdx));
2523 mcSHOW_DBG_MSG3(("Suspect EMI%d_DQS%d_T contact issue\n",u1CHIdx_EMI,u1ByteIdx));
2524 mcSHOW_DBG_MSG3(("Suspect EMI%d_DQS%d_C contact issue\n",u1CHIdx_EMI,u1ByteIdx));
2525 }
2526
2527 else if (PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]&&\
2528 PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx])
2529 {
2530 for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++)
2531 {
2532 if (((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]>>u1BitIdx)&0x1)&&\
2533 ((PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]>>u1BitIdx)&0x1))
2534 {
2535 mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: CH%d RK%d DRAM DQ%d Read/Write fail\n",u1CHIdx,u1RankIdx,u1ByteIdx*8+u1BitIdx));
2536 mcSHOW_DBG_MSG3(("Suspect EMI%d_DQ%d contact issue\n",u1CHIdx_EMI,u1ByteIdx*8+u1BitIdx));
2537 }
2538 }
2539 }
2540
2541 else if((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff) ||\
2542 (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff))
2543 {
2544 mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: CH%d RK%d Byte%d Suspect other special contact or calibration issue\n",u1CHIdx_EMI,u1RankIdx,u1ByteIdx));
2545 }
2546 }
2547 }
2548 }
2549 }
2550 }
2551 }
2552 mcSHOW_DBG_MSG3(("\n"));
2553 return;
2554 }
2555 #endif
2556
2557
2558 #if GATING_ONLY_FOR_DEBUG
DramcGatingDebugRankSel(DRAMC_CTX_T * p,U8 u1Rank)2559 void DramcGatingDebugRankSel(DRAMC_CTX_T *p, U8 u1Rank)
2560 {
2561 if (p->support_rank_num == RANK_SINGLE)
2562 {
2563 u1Rank = 0;
2564 }
2565
2566 vIO32WriteFldAlign_All(DDRPHY_MISC_CTRL1, u1Rank, MISC_CTRL1_R_DMSTBENCMP_RK_OPT);
2567 }
2568
DramcGatingDebugInit(DRAMC_CTX_T * p)2569 void DramcGatingDebugInit(DRAMC_CTX_T *p)
2570 {
2571 U32 backupReg0x64[CHANNEL_NUM], backupReg0xC8[CHANNEL_NUM], backupReg0xD0[CHANNEL_NUM];
2572 U32 backupRegShu_SCINTV[DRAM_DFS_SRAM_MAX][CHANNEL_NUM];
2573 U32 channel_idx, backup_channel, shu_index;
2574
2575 backup_channel = vGetPHY2ChannelMapping(p);
2576
2577 for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
2578 {
2579 vSetPHY2ChannelMapping(p, channel_idx);
2580 backupReg0x64[channel_idx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL));
2581 backupReg0xC8[channel_idx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR));
2582 backupReg0xD0[channel_idx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD));
2583 for (shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++)
2584 backupRegShu_SCINTV[shu_index][channel_idx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCINTV) + SHU_GRP_DRAMC_OFFSET * shu_index);
2585 }
2586 vSetPHY2ChannelMapping(p, backup_channel);
2587
2588
2589 vIO32WriteFldAlign_All(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_REFRDIS);
2590 vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS);
2591 for (shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++)
2592 vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCINTV + SHU_GRP_DRAMC_OFFSET * shu_index, 0x1, SHU_SCINTV_DQSOSCENDIS);
2593 vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN)
2594 | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN)
2595 | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN)
2596 | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG));
2597 mcDELAY_US(4);
2598
2599 DramPhyReset(p);
2600
2601
2602 for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
2603 {
2604 vSetPHY2ChannelMapping(p, channel_idx);
2605 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), backupReg0x64[channel_idx]);
2606 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), backupReg0xC8[channel_idx]);
2607 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), backupReg0xD0[channel_idx]);
2608 for (shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++)
2609 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCINTV) + SHU_GRP_DRAMC_OFFSET * shu_index, backupRegShu_SCINTV[shu_index][channel_idx]);
2610 }
2611 vSetPHY2ChannelMapping(p, backup_channel);
2612
2613
2614
2615 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 1, SPCMD_DQSGCNTEN);
2616 mcDELAY_US(4);
2617
2618 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 1, SPCMD_DQSGCNTRST);
2619 mcDELAY_US(1);
2620 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 0, SPCMD_DQSGCNTRST);
2621 //mcSHOW_DBG_MSG(("DramcGatingDebugInit done\n" ));
2622 }
2623
DramcGatingDebugExit(DRAMC_CTX_T * p)2624 void DramcGatingDebugExit(DRAMC_CTX_T *p)
2625 {
2626
2627 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 0, SPCMD_DQSGCNTEN);
2628 vIO32WriteFldAlign_All(DDRPHY_MISC_CTRL1, 0, MISC_CTRL1_R_DMSTBENCMP_RK_OPT);
2629 }
2630
DramcGatingDebug(DRAMC_CTX_T * p,U8 u1Channel)2631 static void DramcGatingDebug(DRAMC_CTX_T *p, U8 u1Channel)
2632 {
2633 U32 LP3_DataPerByte[DQS_BYTE_NUMBER];
2634 U32 u4DebugCnt[DQS_BYTE_NUMBER];
2635 U16 u2DebugCntPerByte;
2636
2637 U32 u4value, u4all_result_R, u4all_result_F, u4err_value;
2638 U8 backup_channel;
2639
2640 backup_channel = p->channel;
2641 vSetPHY2ChannelMapping(p, u1Channel);
2642
2643 mcDELAY_MS(10);
2644
2645 LP3_DataPerByte[0] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_STBERR_RK0_R), MISC_STBERR_RK0_R_STBERR_RK0_R));
2646 LP3_DataPerByte[2] = (LP3_DataPerByte[0] >> 8) & 0xff;
2647 LP3_DataPerByte[0] &= 0xff;
2648
2649 u4all_result_R = LP3_DataPerByte[0] | (LP3_DataPerByte[2] << 8);
2650
2651
2652 LP3_DataPerByte[0] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_STBERR_RK0_F), MISC_STBERR_RK0_F_STBERR_RK0_F));
2653 LP3_DataPerByte[2] = (LP3_DataPerByte[0] >> 8) & 0xff;
2654 LP3_DataPerByte[0] &= 0xff;
2655
2656 u4all_result_F = LP3_DataPerByte[0] | (LP3_DataPerByte[2] << 8);
2657
2658
2659 u4DebugCnt[0] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DQSGNWCNT0));
2660 u4DebugCnt[1] = (u4DebugCnt[0] >> 16) & 0xffff;
2661 u4DebugCnt[0] &= 0xffff;
2662
2663 u4DebugCnt[2] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DQSGNWCNT1));
2664 u4DebugCnt[3] = (u4DebugCnt[2] >> 16) & 0xffff;
2665 u4DebugCnt[2] &= 0xffff;
2666
2667 mcSHOW_DBG_MSG2(("\n[GatingDebug] CH %d, DQS count (B3->B0) 0x%H, 0x%H, 0x%H, 0x%H \nError flag Rank0 (B3->B0) %B %B %B %B %B %B %B %B\n", \
2668 u1Channel, u4DebugCnt[3], u4DebugCnt[2], u4DebugCnt[1], u4DebugCnt[0], \
2669 (u4all_result_F >> 24) & 0xff, (u4all_result_R >> 24) & 0xff, \
2670 (u4all_result_F >> 16) & 0xff, (u4all_result_R >> 16) & 0xff, \
2671 (u4all_result_F >> 8) & 0xff, (u4all_result_R >> 8) & 0xff, \
2672 (u4all_result_F) & 0xff, (u4all_result_R) & 0xff));
2673
2674 if (p->support_rank_num == RANK_DUAL)
2675 {
2676 LP3_DataPerByte[0] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_STBERR_RK1_R), MISC_STBERR_RK1_R_STBERR_RK1_R));
2677 LP3_DataPerByte[2] = (LP3_DataPerByte[0] >> 8) & 0xff;
2678 LP3_DataPerByte[0] &= 0xff;
2679
2680 u4all_result_R = LP3_DataPerByte[0] | (LP3_DataPerByte[2] << 8);
2681
2682
2683 LP3_DataPerByte[0] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_STBERR_RK1_F), MISC_STBERR_RK1_F_STBERR_RK1_F));
2684 LP3_DataPerByte[2] = (LP3_DataPerByte[0] >> 8) & 0xff;
2685 LP3_DataPerByte[0] &= 0xff;
2686
2687 u4all_result_F = LP3_DataPerByte[0];
2688
2689 mcSHOW_DBG_MSG2(("Error flag Rank1 (B3->B0) %B %B %B %B %B %B %B %B\n", \
2690 (u4all_result_F >> 24) & 0xff, (u4all_result_R >> 24) & 0xff, \
2691 (u4all_result_F >> 16) & 0xff, (u4all_result_R >> 16) & 0xff, \
2692 (u4all_result_F >> 8) & 0xff, (u4all_result_R >> 8) & 0xff, \
2693 (u4all_result_F) & 0xff, (u4all_result_R) & 0xff));
2694 }
2695 else
2696 {
2697 mcSHOW_DBG_MSG2(("\n"));
2698 }
2699
2700 //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 1, SPCMD_DQSGCNTRST);
2701 //mcDELAY_US(1);//delay 2T
2702 //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 0, SPCMD_DQSGCNTRST);
2703
2704 vSetPHY2ChannelMapping(p, backup_channel);
2705 }
2706 #endif
2707
2708 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
2709 #if (__ETT__ || CPU_RW_TEST_AFTER_K)
DramcDumpDebugInfo(DRAMC_CTX_T * p)2710 void DramcDumpDebugInfo(DRAMC_CTX_T *p)
2711 {
2712
2713 U8 u1RefreshRate;
2714 DRAM_CHANNEL_T channelIdx;
2715
2716
2717 #ifdef TEMP_SENSOR_ENABLE
2718 for (channelIdx = CHANNEL_A; channelIdx < (int)p->support_channel_num; channelIdx++)
2719 {
2720 u1RefreshRate = u1GetMR4RefreshRate(p, channelIdx);
2721 mcSHOW_DBG_MSG2(("[CH%d] MRR(MR4) [10:8]=%x\n", channelIdx, u1RefreshRate));
2722 }
2723 #endif
2724
2725 #if ENABLE_REFRESH_RATE_DEBOUNCE
2726 {
2727 U8 pre_refresh_rate[4];
2728 for (channelIdx = CHANNEL_A; channelIdx < (int)p->support_channel_num; channelIdx++)
2729 {
2730 vSetPHY2ChannelMapping(p, channelIdx);
2731
2732 pre_refresh_rate[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_IRQ_INFO1A), DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK0_FOR_INT_X0);
2733 pre_refresh_rate[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_IRQ_INFO1A), DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK1_FOR_INT_X0);
2734 pre_refresh_rate[2] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_IRQ_INFO1A), DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK0_B1_FOR_INT_X0);
2735 pre_refresh_rate[3] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_IRQ_INFO1A), DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK1_B1_FOR_INT_X0);
2736
2737 mcSHOW_DBG_MSG2(("\t[CH%d] RK0 B0 Int Status=0x%x\n", channelIdx, pre_refresh_rate[0]));
2738 mcSHOW_DBG_MSG2(("\t[CH%d] RK1 B0 Int Status=0x%x\n", channelIdx, pre_refresh_rate[1]));
2739 mcSHOW_DBG_MSG2(("\t[CH%d] RK0 B1 Int Status=0x%x\n", channelIdx, pre_refresh_rate[2]));
2740 mcSHOW_DBG_MSG2(("\t[CH%d] RK1 B1 Int Status=0x%x\n", channelIdx, pre_refresh_rate[3]));
2741
2742 mcSHOW_DBG_MSG2(("\t[CH%d] MISC_STATUSA_REFRESH_RATE=%d\n", channelIdx, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REFRESH_RATE)));
2743 }
2744 vSetPHY2ChannelMapping(p, CHANNEL_A);
2745 }
2746 #endif
2747
2748
2749
2750 #if __A60868_TO_BE_PORTING__
2751 U8 mpdivInSel, cali_shu_sel, mpdiv_shu_sel, u1RefreshRate;
2752 DRAM_CHANNEL_T channelIdx;
2753
2754 mpdivInSel = u4IO32ReadFldAlign(DDRPHY_MISC_CTRL2, MISC_CTRL2_CLRPLL_SHU_GP);
2755 cali_shu_sel = u4IO32ReadFldAlign(DRAMC_REG_SHUCTRL, SHUCTRL_R_OTHER_SHU_GP);
2756 mpdiv_shu_sel = u4IO32ReadFldAlign(DRAMC_REG_SHUCTRL, SHUCTRL_R_MPDIV_SHU_GP);
2757
2758
2759 mcSHOW_DBG_MSG2(("\n\n[DumpDebugInfo]\n"
2760 "\tmpdivInSel %d, cali_shu_sel %d, mpdiv_shu_sel %d\n",
2761 mpdivInSel, cali_shu_sel, mpdiv_shu_sel));
2762
2763 #if GATING_ONLY_FOR_DEBUG
2764
2765 //DramcGatingDebugInit(p);
2766 for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
2767 {
2768 DramcGatingDebug(p, channelIdx);
2769 }
2770 #endif
2771
2772 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
2773
2774 #ifdef HW_GATING
2775 for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
2776 {
2777 DramcPrintHWGatingStatus(p, channelIdx);
2778 }
2779 #endif
2780
2781 DramcPrintRXFIFODebugStatus(p);
2782
2783 #if (ENABLE_RX_TRACKING && RX_DLY_TRACK_ONLY_FOR_DEBUG && defined(DUMMY_READ_FOR_TRACKING))
2784 DramcPrintRxDlyTrackDebugStatus(p);
2785 #endif
2786
2787 #if ENABLE_RX_TRACKING
2788 for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
2789 {
2790 DramcPrintRXDQDQSStatus(p, channelIdx);
2791 }
2792 #endif
2793
2794 #ifdef IMPEDANCE_TRACKING_ENABLE
2795 if (u1IsLP4Family(p->dram_type))
2796 {
2797 for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
2798 {
2799 DramcPrintIMPTrackingStatus(p, channelIdx);
2800 }
2801
2802 }
2803 #endif
2804
2805 #ifdef TEMP_SENSOR_ENABLE
2806 for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
2807 {
2808 u1RefreshRate = u1GetMR4RefreshRate(p, channelIdx);
2809 mcSHOW_DBG_MSG2(("[CH%d] MRR(MR4) [10:8]=%x\n", channelIdx, u1RefreshRate));
2810 }
2811 #endif
2812 #endif//(FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
2813 #endif
2814 }
2815 #endif
2816 #endif
2817
2818 #if ((fcFOR_CHIP_ID == fcA60868) || (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0))
2819 #if __ETT__
2820 #if DUMP_ALLSUH_RG
DramcRegDumpRange(DRAMC_CTX_T * p,U32 u4StartAddr,U32 u4EndAddr)2821 static void DramcRegDumpRange(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr)
2822 {
2823 U32 ii;
2824 for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4)
2825 {
2826 mcSHOW_DBG_MSG(("Reg(0x%xh) Address 0x%X = 0x%X\n", (ii & 0xfff) >> 2, ii, u4Dram_Register_Read(p, DRAMC_REG_ADDR(ii))));
2827 mcDELAY_US(20000);
2828 }
2829 }
2830 #if 0
2831 #define DRAMC_NAO_DUMP_RANGE (DRAMC_REG_RK2_B23_STB_DBG_INFO_15 - DRAMC_NAO_BASE_ADDRESS)
2832 #define DDRPHY_NAO_DUMP_RANGE (DDRPHY_MISC_MBIST_STATUS2 - DDRPHY_NAO_BASE_ADDR)
2833 #define DRAMC_AO_NONSHU_DUMP_RANGE (DRAMC_REG_RK1_PRE_TDQSCK27 - DRAMC_AO_BASE_ADDRESS)
2834 #define DRAMC_AO_SHU_BASE (DRAMC_REG_SHU_ACTIM0 - DRAMC_AO_BASE_ADDRESS)
2835 #define DRAMC_AO_SHU_DUMP_RANGE (DRAMC_REG_SHURK1_DQS2DQ_CAL5 - DRAMC_REG_SHU_ACTIM0)
2836 #define DDRPHY_AO_NONSHU_DUMP_RANGE (DDRPHY_RFU_0XB2C - DDRPHY_AO_BASE_ADDR)
2837 #define DDRPHY_AO_SHU_BASE (DDRPHY_SHU_B0_DQ0 - DDRPHY_AO_BASE_ADDR)
2838 #define DDRPHY_AO_SHU_DUMP_RANGE (DDRPHY_SHU_R2_CA_CMD9 - DDRPHY_SHU_B0_DQ0)
2839 #endif
DumpAoNonShuNoRkReg(DRAMC_CTX_T * p)2840 void DumpAoNonShuNoRkReg(DRAMC_CTX_T *p)
2841 {
2842 mcSHOW_DBG_MSG(("\n\tCHA_DRAMC_AO_NONSHU_NORK_BASE\n"));
2843 DramcRegDumpRange(p, DRAMC_REG_DDRCOMMON0, DRAMC_REG_SA_RESERVE);
2844 DramcRegDumpRange(p, DRAMC_REG_NONSHU_RSV, DRAMC_REG_SCRAMBLE_CFGF);
2845 DramcRegDumpRange(p, DRAMC_REG_WDT_DBG_SIGNAL, DRAMC_REG_SELFREF_HWSAVE_FLAG);
2846 DramcRegDumpRange(p, DRAMC_REG_DRAMC_IRQ_STATUS1, DRAMC_REG_DRAMC_IRQ_INFO5);
2847 mcSHOW_DBG_MSG(("\n\tCHA_PHY_AO_NONSHU_NORK_BASE\n"));
2848 DramcRegDumpRange(p, DDRPHY_REG_PHYPLL0, DDRPHY_REG_CLRPLL0);
2849 DramcRegDumpRange(p, DDRPHY_REG_B0_LP_CTRL0, DDRPHY_REG_B0_PHY4);
2850 DramcRegDumpRange(p, DDRPHY_REG_B1_LP_CTRL0, DDRPHY_REG_B1_TX_CKE_CTRL);
2851 DramcRegDumpRange(p, DDRPHY_REG_CA_LP_CTRL0, DDRPHY_REG_CA_TX_ARDQ_CTRL);
2852 DramcRegDumpRange(p, DDRPHY_REG_MISC_STBCAL, DDRPHY_REG_MISC_BIST_LPBK_CTRL0);
2853 mcSHOW_DBG_MSG(("\n\tDDRPHY_MD32_BASE_ADDRESS\n"));
2854 DramcRegDumpRange(p, DDRPHY_MD32_REG_SSPM_CFGREG_SW_RSTN, DDRPHY_MD32_REG_SSPM_CFGREG_TBUFH);
2855 DramcRegDumpRange(p, DDRPHY_MD32_REG_SSPM_TIMER0_CON, DDRPHY_MD32_REG_SSPM_OS_TIMER_IRQ_ACK);
2856 DramcRegDumpRange(p, DDRPHY_MD32_REG_SSPM_INTC_IRQ_RAW_STA0, DDRPHY_MD32_REG_SSPM_INTC_UART_RX_IRQ);
2857 DramcRegDumpRange(p, DDRPHY_MD32_REG_SSPM_MCLK_DIV, DDRPHY_MD32_REG_SSPM_UART_CTRL);
2858 DramcRegDumpRange(p, DDRPHY_MD32_REG_SSPM_DMA_GLBSTA, DDRPHY_MD32_REG_SSPM_DMA4_LIMITER);
2859 DramcRegDumpRange(p, DDRPHY_MD32_REG_SSPM_UART_RBR_THR_DLL_ADDR, DDRPHY_MD32_REG_SSPM_UART_SPM_SEL);
2860 DramcRegDumpRange(p, DDRPHY_MD32_REG_SSPM_TWAM_CTRL, DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT15);
2861 DramcRegDumpRange(p, DDRPHY_MD32_REG_LPIF_FSM_CFG, DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_3);
2862 return;
2863 }
DumpAoNonShuRkReg(DRAMC_CTX_T * p)2864 void DumpAoNonShuRkReg(DRAMC_CTX_T *p)
2865 {
2866 mcSHOW_DBG_MSG(("\n\tCHA_DRAMC_AO_NONSHU_RK_BASE\n"));
2867 DramcRegDumpRange(p, DRAMC_REG_RK_TEST2_A1, DRAMC_REG_RK_DQSOSC);
2868 mcSHOW_DBG_MSG(("\n\tCHA_PHY_AO_NONSHU_RK_BASE\n"));
2869 DramcRegDumpRange(p, DDRPHY_REG_RK_B0_RXDVS0, DDRPHY_REG_RK_B0_RXDVS4);
2870 DramcRegDumpRange(p, DDRPHY_REG_RK_B1_RXDVS0, DDRPHY_REG_RK_B1_RXDVS4);
2871 DramcRegDumpRange(p, DDRPHY_REG_RK_CA_RXDVS0, DDRPHY_REG_RK_CA_RXDVS4);
2872 return;
2873 }
DumpAoShuNoRkReg(DRAMC_CTX_T * p)2874 void DumpAoShuNoRkReg(DRAMC_CTX_T *p)
2875 {
2876 mcSHOW_DBG_MSG(("\n\tCHA_DRAMC_AO_SHU_NORK_BASE\n"));
2877 DramcRegDumpRange(p, DRAMC_REG_SHU_MATYPE, DRAMC_REG_SHU_ACTIM7);
2878 mcSHOW_DBG_MSG(("\n\tCHA_PHY_AO_SHU_NORK_BASE\n"));
2879 DramcRegDumpRange(p, DDRPHY_REG_SHU_PHYPLL0, DDRPHY_REG_SHU_PLL2);
2880 DramcRegDumpRange(p, DDRPHY_REG_SHU_B0_DQ0, DDRPHY_REG_SHU_B0_DQSIEN_CFG);
2881 DramcRegDumpRange(p, DDRPHY_REG_SHU_B1_DQ0, DDRPHY_REG_SHU_B1_CKE_DLY_CTRL);
2882 DramcRegDumpRange(p, DDRPHY_REG_SHU_CA_CMD0, DDRPHY_REG_SHU_CA_DQ_DLY);
2883 DramcRegDumpRange(p, DDRPHY_REG_MISC_SHU_DRVING7, DDRPHY_REG_MISC_SHU_CG_CTRL0);
2884 DramcRegDumpRange(p, DDRPHY_REG_MISC_STBERR_ALL, DDRPHY_REG_MISC_DBG_DB_MESSAGE7);
2885 return;
2886 }
DumpAoShuRkReg(DRAMC_CTX_T * p)2887 void DumpAoShuRkReg(DRAMC_CTX_T *p)
2888 {
2889 mcSHOW_DBG_MSG(("\n\tCHA_DRAMC_AO_SHU_RK_BASE\n"));
2890 DramcRegDumpRange(p, DRAMC_REG_SHURK_SELPH_DQ0, DRAMC_REG_SHURK_CKE_CTRL);
2891 mcSHOW_DBG_MSG(("\n\tCHA_PHY_AO_SHU_RK_BASE\n"));
2892 DramcRegDumpRange(p, DDRPHY_REG_SHU_R0_B0_TXDLY0, DDRPHY_REG_SHU_RK_B0_BIST_CTRL);
2893 DramcRegDumpRange(p, DDRPHY_REG_SHU_R0_B1_TXDLY0, DDRPHY_REG_SHU_RK_B1_CKE_DLY);
2894 DramcRegDumpRange(p, DDRPHY_REG_SHU_R0_CA_TXDLY0, DDRPHY_REG_SHU_RK_CA_DQ_DLY);
2895 DramcRegDumpRange(p, DDRPHY_REG_MISC_SHU_RK_DQSCTL, DDRPHY_REG_MISC_SHU_RK_DQSCAL);
2896 return;
2897 }
DumpNaoReg(DRAMC_CTX_T * p)2898 void DumpNaoReg(DRAMC_CTX_T *p)
2899 {
2900 mcSHOW_DBG_MSG(("\n\n\tCHA_DRAMC_NAO_BASE\n"));
2901 DramcRegDumpRange(p, DRAMC_REG_TESTMODE, DRAMC_REG_CBT_WLEV_ATK_RESULT13);
2902 DramcRegDumpRange(p, DRAMC_REG_HWMRR_PUSH2POP_CNT, DRAMC_REG_SREF_DLY_CNT);
2903 DramcRegDumpRange(p, DRAMC_REG_TX_ATK_SET0, DRAMC_REG_TX_ATK_DBG_BIT_STATUS4);
2904 DramcRegDumpRange(p, DRAMC_REG_LP5_PDX_PDE_MON, DRAMC_REG_LAT_COUNTER_BLOCK_ALE);
2905 DramcRegDumpRange(p, DRAMC_REG_DRAMC_LOOP_BAK_ADR, DRAMC_REG_DRAMC_LOOP_BAK_WDAT7);
2906 DramcRegDumpRange(p, DRAMC_REG_RK0_DQSOSC_STATUS, DRAMC_REG_RK0_DUMMY_RD_DATA7);
2907 DramcRegDumpRange(p, DRAMC_REG_RK0_PI_DQ_CAL, DRAMC_REG_RK0_PI_DQM_CAL);
2908 DramcRegDumpRange(p, DRAMC_REG_RK1_DQSOSC_STATUS, DRAMC_REG_RK1_DUMMY_RD_DATA7);
2909 DramcRegDumpRange(p, DRAMC_REG_RK1_PI_DQ_CAL, DRAMC_REG_RK1_PI_DQM_CAL);
2910 DramcRegDumpRange(p, DRAMC_REG_MR_BACKUP_00_RK0_FSP0, DRAMC_REG_MR_BACKUP_03_RK0_FSP2);
2911 DramcRegDumpRange(p, DRAMC_REG_MR_BACKUP_00_RK1_FSP0, DRAMC_REG_MR_BACKUP_03_RK1_FSP2);
2912 mcSHOW_DBG_MSG(("\n\tCHA_PHY_NAO_BASE\n"));
2913 DramcRegDumpRange(p, DDRPHY_REG_MISC_STA_EXTLB0, DDRPHY_REG_MISC_RDSEL_TRACK_DBG);
2914 DramcRegDumpRange(p, DDRPHY_REG_MISC_DQ_RXDLY_TRRO0, DDRPHY_REG_MISC_DQ_RXDLY_TRRO31);
2915 DramcRegDumpRange(p, DDRPHY_REG_MISC_CA_RXDLY_TRRO20, DDRPHY_REG_MISC_STA_TOGLB1);
2916 DramcRegDumpRange(p, DDRPHY_REG_MISC_STA_EXTLB_DBG0, DDRPHY_REG_MISC_STA_EXTLB5);
2917 DramcRegDumpRange(p, DDRPHY_REG_DEBUG_APHY_RX_CTL, DDRPHY_REG_DEBUG_RODT_CTL);
2918 DramcRegDumpRange(p, DDRPHY_REG_CAL_DQSG_CNT_B0, DDRPHY_REG_RX_AUTOK_STATUS20);
2919 DramcRegDumpRange(p, DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0, DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS5);
2920 DramcRegDumpRange(p, DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_STATUS0, DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE11);
2921 DramcRegDumpRange(p, DDRPHY_REG_MISC_DMA_SRAM_MBIST, DDRPHY_REG_MISC_STA_EXTLB9);
2922 return;
2923 }
DumpAllRkRG(DRAMC_CTX_T * p,U8 u1ShuType)2924 void DumpAllRkRG(DRAMC_CTX_T *p, U8 u1ShuType)
2925 {
2926 U8 u1RankIdx, u1rk_backup=u1GetRank(p);
2927 if (u1ShuType == NONSHUFFLE_RG||u1ShuType == BOTH_SHU_NONSHU_RG)
2928 {
2929 mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=NON, SHU=NON, FREQ=NON, AORG, start \n", vGetPHY2ChannelMapping(p)));
2930 DumpAoNonShuNoRkReg(p);
2931 mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=NON, SHU=NON, FREQ=NON, AORG, end \n", vGetPHY2ChannelMapping(p)));
2932 }
2933 if (u1ShuType == SHUFFLE_RG||u1ShuType == BOTH_SHU_NONSHU_RG)
2934 {
2935 mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=NON, SHU=SRAM%d, FREQ=%d, AORG, start \n", vGetPHY2ChannelMapping(p), vGet_Current_SRAMIdx(p), GetFreqBySel(p, vGet_PLL_FreqSel(p))));
2936 DumpAoShuNoRkReg(p);
2937 mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=NON, SHU=SRAM%d, FREQ=%d, AORG, end \n", vGetPHY2ChannelMapping(p), vGet_Current_SRAMIdx(p), GetFreqBySel(p, vGet_PLL_FreqSel(p))));
2938 }
2939 for (u1RankIdx=RANK_0; u1RankIdx<p->support_rank_num; u1RankIdx++)
2940 {
2941 vSetRank(p, u1RankIdx);
2942 if (u1ShuType == NONSHUFFLE_RG||u1ShuType == BOTH_SHU_NONSHU_RG)
2943 {
2944 mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=%d, SHU=NON, FREQ=NON, AORG, start \n", vGetPHY2ChannelMapping(p), u1GetRank(p)));
2945 DumpAoNonShuRkReg(p);
2946 mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=%d, SHU=NON, FREQ=NON, AORG, end \n", vGetPHY2ChannelMapping(p), u1GetRank(p)));
2947 }
2948 if (u1ShuType == SHUFFLE_RG||u1ShuType == BOTH_SHU_NONSHU_RG)
2949 {
2950 mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=%d, SHU=SRAM%d, FREQ=%d, AORG, start \n", vGetPHY2ChannelMapping(p), u1GetRank(p), vGet_Current_SRAMIdx(p), GetFreqBySel(p, vGet_PLL_FreqSel(p))));
2951 DumpAoShuRkReg(p);
2952 mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=%d, SHU=SRAM%d, FREQ=%d, AORG, end \n", vGetPHY2ChannelMapping(p), u1GetRank(p), vGet_Current_SRAMIdx(p), GetFreqBySel(p, vGet_PLL_FreqSel(p))));
2953 }
2954 }
2955 vSetRank(p, u1rk_backup);
2956 }
DumpAllChAllShuAllRkRG(DRAMC_CTX_T * p)2957 void DumpAllChAllShuAllRkRG(DRAMC_CTX_T *p)
2958 {
2959 U8 u1ChannelIdx, u1Ch_backup=vGetPHY2ChannelMapping(p);
2960 U8 u1ShuffleIdx, u1Shu_backup=p->ShuRGAccessIdx;
2961 for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++)
2962 {
2963 vSetPHY2ChannelMapping(p, u1ChannelIdx);
2964 DumpAllRkRG(p,NONSHUFFLE_RG);
2965 for(u1ShuffleIdx=DRAM_DFS_REG_SHU0; u1ShuffleIdx<DRAM_DFS_REG_MAX; u1ShuffleIdx++)
2966 {
2967 p->ShuRGAccessIdx = u1ShuffleIdx;
2968 DumpAllRkRG(p,SHUFFLE_RG);
2969 }
2970 }
2971 p->ShuRGAccessIdx=u1Shu_backup;
2972 vSetPHY2ChannelMapping(p, u1Ch_backup);
2973 }
DumpShuRG(DRAMC_CTX_T * p)2974 static void DumpShuRG(DRAMC_CTX_T *p)
2975 {
2976 DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable = p->pDFSTable;
2977 U8 u1ShuffleIdx;
2978 U32 u4DramcShuOffset = 0;
2979 U32 u4DDRPhyShuOffset = 0;
2980 U32 u4RegBackupAddress[] =
2981 {
2982 (DDRPHY_REG_MISC_SRAM_DMA0),
2983 (DDRPHY_REG_MISC_SRAM_DMA1),
2984 #if (CHANNEL_NUM>1)
2985 (DDRPHY_REG_MISC_SRAM_DMA0+SHIFT_TO_CHB_ADDR),
2986 (DDRPHY_REG_MISC_SRAM_DMA1+SHIFT_TO_CHB_ADDR),
2987 #endif
2988 #if (CHANNEL_NUM>2)
2989 (DDRPHY_REG_MISC_SRAM_DMA0+SHIFT_TO_CHC_ADDR),
2990 (DDRPHY_REG_MISC_SRAM_DMA1+SHIFT_TO_CHC_ADDR),
2991 (DDRPHY_REG_MISC_SRAM_DMA0+SHIFT_TO_CHD_ADDR),
2992 (DDRPHY_REG_MISC_SRAM_DMA1+SHIFT_TO_CHD_ADDR),
2993 #endif
2994 };
2995 DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
2996 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);
2997 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS);
2998 DumpAllRkRG(p,NONSHUFFLE_RG);
2999 for (u1ShuffleIdx = 0; u1ShuffleIdx <= DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
3000 {
3001 if (u1ShuffleIdx == DRAM_DFS_SRAM_MAX)
3002 {
3003 vSetDFSTable(p, pFreqTable);
3004 u4DramcShuOffset = 0;
3005 u4DDRPhyShuOffset = 0;
3006 DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
3007 }
3008 else
3009 {
3010 vSetDFSTable(p, get_FreqTbl_by_SRAMIndex(p, u1ShuffleIdx));
3011 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);
3012 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, u1ShuffleIdx, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL);
3013 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL);
3014 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
3015 DumpAllRkRG(p,SHUFFLE_RG);
3016 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
3017 }
3018 }
3019 }
DumpAllChAllShuRG(DRAMC_CTX_T * p)3020 void DumpAllChAllShuRG(DRAMC_CTX_T *p)
3021 {
3022 U8 u1ChannelIdx, u1Channel_backup;
3023 u1Channel_backup = p->channel;
3024 for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++)
3025 {
3026 vSetPHY2ChannelMapping(p, u1ChannelIdx);
3027 mcSHOW_DBG_MSG(("\n[DUMPLOG]AllChannelAllShu-start Channel=%d\n", p->channel));
3028 DumpShuRG(p);
3029 }
3030 vSetPHY2ChannelMapping(p, u1Channel_backup);
3031 }
3032 #endif
3033 #if ETT_NO_DRAM
NoDramDramcRegDumpRange(U32 u4StartAddr,U32 u4EndAddr)3034 static void NoDramDramcRegDumpRange(U32 u4StartAddr, U32 u4EndAddr)
3035 {
3036 U32 ii;
3037 for (ii = u4StartAddr; ii < u4EndAddr; ii += 4)
3038 {
3039 mcSHOW_DBG_MSG(("*(volatile unsigned int *)0x%X = 0x%X;\n", ii, (*(volatile unsigned int *)(ii))));
3040 }
3041 }
NoDramDramcRegDump(DRAMC_CTX_T * p)3042 DRAM_STATUS_T NoDramDramcRegDump(DRAMC_CTX_T *p)
3043 {
3044 mcSHOW_DBG_MSG(("\n\n\tCHA_DRAMC_AO_BASE\n"));
3045 NoDramDramcRegDumpRange(Channel_A_DRAMC_AO_BASE_ADDRESS, Channel_A_DRAMC_AO_BASE_ADDRESS + 0x1E58);
3046 mcSHOW_DBG_MSG(("\n\tCHB_DRAMC_AO_BASE\n"));
3047 NoDramDramcRegDumpRange(Channel_B_DRAMC_AO_BASE_ADDRESS, Channel_B_DRAMC_AO_BASE_ADDRESS + 0x1E58);
3048 mcSHOW_DBG_MSG(("\n\tPHY_A_BASE\n"));
3049 NoDramDramcRegDumpRange(Channel_A_DDRPHY_BASE_ADDRESS, Channel_A_DDRPHY_BASE_ADDRESS + 0x1FC8);
3050 mcSHOW_DBG_MSG(("\n\tPHY_B_BASE\n"));
3051 NoDramDramcRegDumpRange(Channel_B_PHY_BASE_ADDRESS, Channel_B_PHY_BASE_ADDRESS + 0x1FC8);
3052 return DRAM_OK;
3053 }
NoDramRegFill(void)3054 DRAM_STATUS_T NoDramRegFill(void)
3055 {
3056 }
3057 #endif
3058 #endif
3059 #endif
3060 #if DRAMC_MODEREG_CHECK
3061 #if defined(RELEASE) && defined(DEVIATION)
3062 #undef mcSHOW_JV_LOG_MSG
3063 #define mcSHOW_JV_LOG_MSG(_x_) opt_print _x_
3064 #endif
DramcModeReg_Check(DRAMC_CTX_T * p)3065 void DramcModeReg_Check(DRAMC_CTX_T *p)
3066 {
3067 U8 backup_channel, backup_rank;
3068 U8 u1ChannelIdx, u1RankIdx;
3069 U8 u1MRFsp;
3070 U8 ii, u1MR[] = {5, 12, 14, 4, 18, 19};
3071 U16 u2MRValue = 0, u2Value = 0;
3072 U8 u1match = 0;
3073 U8 backup_u1MR13Value[RANK_MAX] = {0};
3074 #if MRW_CHECK_ONLY || MRW_BACKUP
3075 U8 FSPWR_FlagBak[RANK_MAX];
3076 #endif
3077
3078 mcSHOW_DBG_MSG2(("\n\n[DramcModeReg_Check] Freq_%d, FSP_%d\n", p->frequency, p->dram_fsp));
3079
3080 backup_channel = vGetPHY2ChannelMapping(p);
3081 backup_rank = u1GetRank(p);
3082
3083 #if MRW_CHECK_ONLY || MRW_BACKUP
3084 for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
3085 {
3086 FSPWR_FlagBak[u1RankIdx] = gFSPWR_Flag[u1RankIdx];
3087 }
3088 #endif
3089
3090 if (u1IsLP4Family(p->dram_type))
3091 {
3092 #if VENDER_JV_LOG && defined(DEVIATION)
3093 mcSHOW_JV_LOG_MSG(("\n\n[DramcModeReg_Check] Freq_%d, FSP_%d\n",p->frequency,p->dram_fsp));
3094 #else
3095 mcSHOW_DBG_MSG2(("\n\n[DramcModeReg_Check] Freq_%d, FSP_%d\n",p->frequency,p->dram_fsp));
3096 #endif
3097
3098 #if MRW_CHECK_ONLY
3099 mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
3100 #endif
3101
3102 for (u1MRFsp = FSP_0; u1MRFsp < p->support_fsp_num; u1MRFsp++)
3103 {
3104 for (u1ChannelIdx = 0; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++)
3105 {
3106 vSetPHY2ChannelMapping(p, u1ChannelIdx);
3107
3108 for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
3109 {
3110 #if MRW_CHECK_ONLY || MRW_BACKUP
3111 if (u1MRFsp == FSP_0)
3112 {
3113 gFSPWR_Flag[u1RankIdx] = FSPWR_FlagBak[u1RankIdx];
3114 }
3115 else
3116 {
3117 gFSPWR_Flag[u1RankIdx] = u1MRFsp - 1;
3118 }
3119 #endif
3120
3121 backup_u1MR13Value[u1RankIdx] = u1MR13Value[u1RankIdx];
3122 #if VENDER_JV_LOG && defined(DEVIATION)
3123 mcSHOW_JV_LOG_MSG(("FSP_%d, CH_%d, RK%d\n",u1MRFsp,u1ChannelIdx,u1RankIdx));
3124 #else
3125 mcSHOW_DBG_MSG2(("FSP_%d, CH_%d, RK%d\n",u1MRFsp,u1ChannelIdx,u1RankIdx));
3126 #endif
3127
3128 if (u1MRFsp == FSP_1)
3129 u1MR13Value[u1RankIdx] |= 0x40;
3130 else
3131 u1MR13Value[u1RankIdx] &= (~0x40);
3132
3133 DramcModeRegWriteByRank(p, u1RankIdx, 13, u1MR13Value[u1RankIdx]);
3134
3135 for (ii = 0; ii < sizeof(u1MR); ii++)
3136 {
3137 DramcModeRegReadByRank(p, u1RankIdx, u1MR[ii], &u2Value);
3138 u2Value &= 0xFF;
3139
3140 if ((u1MR[ii] == 12) || (u1MR[ii] == 14))
3141 {
3142 if (u1MR[ii] == 12)
3143 {
3144 u2MRValue = u1MR12Value[u1ChannelIdx][u1RankIdx][u1MRFsp];
3145 }
3146 else if (u1MR[ii] == 14)
3147 {
3148 u2MRValue = u1MR14Value[u1ChannelIdx][u1RankIdx][u1MRFsp];
3149 }
3150 u1match = (u2Value == u2MRValue)? 1: 0;
3151
3152 #ifdef FOR_HQA_REPORT_USED
3153 if (gHQALog_flag == 1)
3154 {
3155 HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT1, "DramcModeReg_Read_FSP_", u1MRFsp==0?"0_MR":"1_MR", u1MR[ii], u2Value, NULL);
3156 }
3157 else
3158 #endif
3159 {
3160 mcSHOW_DBG_MSG2(("\t\tMR%d = 0x%x (global = 0x%x)\t%smatch\n",u1MR[ii],u2Value,u2MRValue, (u1match==1)?"":"mis"));
3161 #if VENDER_JV_LOG && defined(DEVIATION)
3162 mcSHOW_JV_LOG_MSG(("[Vref Range = %d, Vref Value = %d]\n",(u2Value>>6)&1, u2Value&0x3f));
3163 #else
3164 mcSHOW_DBG_MSG2(("[Vref Range = %d, Vref Value = %d]\n",(u2Value>>6)&1, u2Value&0x3f));
3165 #endif
3166
3167 }
3168 }
3169 else
3170 {
3171 #ifdef FOR_HQA_REPORT_USED
3172 if (gHQALog_flag == 1)
3173 {
3174 HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT1, "DramcModeReg_Read_FSP_", u1MRFsp==0?"0_MR":"1_MR", u1MR[ii], u2Value, NULL);
3175 }
3176 else
3177 #endif
3178 {
3179 const char *str_vender = "";
3180 if (u1MR[ii] == 5)
3181 {
3182
3183 str_vender = (u2Value == 1)? "Samsung":(u2Value==0xff)?"Micron":(u2Value==0x5)?"Nanya":(u2Value==0x6)?"Hynix":"mismatch";
3184 }
3185 mcSHOW_DBG_MSG2(("\t\tMR%d = 0x%x %s\n", u1MR[ii], u2Value, str_vender));
3186 }
3187 }
3188
3189 }
3190
3191
3192 u1MR13Value[u1RankIdx] = backup_u1MR13Value[u1RankIdx];
3193 }
3194 }
3195 }
3196
3197 #if MRW_CHECK_ONLY || MRW_BACKUP
3198 for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
3199 {
3200 FSPWR_FlagBak[u1RankIdx] = gFSPWR_Flag[u1RankIdx];
3201 }
3202 #endif
3203
3204 for (u1ChannelIdx = 0; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++)
3205 {
3206 vSetPHY2ChannelMapping(p, u1ChannelIdx);
3207 for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
3208 {
3209 #if MRW_CHECK_ONLY || MRW_BACKUP
3210 gFSPWR_Flag[u1RankIdx] = FSPWR_FlagBak[u1RankIdx];
3211 #endif
3212
3213 DramcModeRegWriteByRank(p, u1RankIdx, 13, backup_u1MR13Value[u1RankIdx]);
3214 }
3215 }
3216 }
3217
3218 vSetPHY2ChannelMapping(p, backup_channel);
3219 vSetRank(p, backup_rank);
3220 return;
3221 }
3222 #if defined(RELEASE) && defined(DEVIATION)
3223 #undef mcSHOW_JV_LOG_MSG
3224 #define mcSHOW_JV_LOG_MSG(_x_)
3225 #endif
3226 #endif
3227
3228 #if MRW_CHECK_ONLY
vPrintFinalModeRegisterSetting(DRAMC_CTX_T * p)3229 void vPrintFinalModeRegisterSetting(DRAMC_CTX_T * p)
3230 {
3231 U8 u1CHIdx, u1RankIdx, u1FSPIdx, u1MRIdx;
3232 U16 u2MRValue;
3233 U8 u1Backup_Channel, u1Backup_Rank, u1Backup_Fsp;
3234
3235 mcSHOW_MRW_MSG(("\n\n\n==vPrintFinalModeRegisterSetting====\n"));
3236
3237 u1Backup_Channel = vGetPHY2ChannelMapping(p);
3238 u1Backup_Rank = u1GetRank (p);
3239
3240 for (u1CHIdx = 0; u1CHIdx < p->support_channel_num; u1CHIdx++)
3241 {
3242 vSetPHY2ChannelMapping(p, u1CHIdx);
3243 for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)
3244 {
3245 vSetRank(p, u1RankIdx);
3246 u1Backup_Fsp = gFSPWR_Flag[p->rank];
3247 for (u1FSPIdx = 0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++)
3248 {
3249 gFSPWR_Flag[p->rank]=u1FSPIdx;
3250 mcSHOW_MRW_MSG(("==[MR Dump] CH%d Rank%d Fsp%d ==\n", p->channel, p->rank, gFSPWR_Flag[p->rank]));
3251 for (u1MRIdx = 0; u1MRIdx < MR_NUM; u1MRIdx++)
3252 {
3253 u2MRValue = u2MRRecord[u1CHIdx][u1RankIdx][u1FSPIdx][u1MRIdx];
3254 if (u2MRValue != 0xffff)
3255 {
3256 mcSHOW_MRW_MSG(("[MR Dump] CH%d Rank%d Fsp%d MR%d =0x%x\n", p->channel, p->rank, gFSPWR_Flag[p->rank], u1MRIdx, u2MRValue));
3257 #if MRW_BACKUP
3258
3259 {
3260 if (u1MRIdx==13)
3261 gFSPWR_Flag[p->rank]=u1Backup_Fsp;
3262 }
3263
3264 DramcMRWriteBackup(p, u1MRIdx, u1RankIdx);
3265
3266 {
3267 if (u1MRIdx==13)
3268 gFSPWR_Flag[p->rank]=u1FSPIdx;
3269 }
3270 #endif
3271 }
3272 }
3273 mcSHOW_MRW_MSG(("\n"));
3274 }
3275 gFSPWR_Flag[p->rank] = u1Backup_Fsp;
3276 }
3277 }
3278 vSetRank(p, u1Backup_Rank);
3279 vSetPHY2ChannelMapping(p, u1Backup_Channel);
3280 }
3281 #endif
3282
3283 #if defined(TEST_MODE_MRS) || SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER
3284 const U8 PME_Key[4][6] =
3285 {
3286 { 2, 5, 5, 2, 4, 8},
3287 { 2, 5, 5, 2, 4, 8},
3288 { 2, 5, 5, 2, 4, 8},
3289 { 10, 13, 13, 10, 12, 13}
3290 };
3291
3292
3293 static U32 u4TestModeV0[2] = {};
3294 static U32 u4TestModeV1[2] = {};
3295 static U32 u4TestModeV2[2] = {};
3296 static U32 u4TestModeV3[2] = {};
3297 static U32 u4TestModeV4[2] = {};
3298 static U32 u4TestModeV5[2] = {};
3299 static U32 u4TestModeV6[2] = {};
3300
BackupRGBeforeTestMode(DRAMC_CTX_T * p)3301 static void BackupRGBeforeTestMode(DRAMC_CTX_T *p)
3302 {
3303 DRAM_CHANNEL_T eOriChannel = p->channel;
3304 int i = 0;
3305 p->channel = CHANNEL_A;
3306 for (i = 0; i < 2; i++)
3307 {
3308 if (i == 0)
3309 {
3310 mcSHOW_DBG_MSG(("***CHA\n"));
3311 }
3312 else
3313 {
3314 mcSHOW_DBG_MSG(("***CHB\n"));
3315 }
3316
3317 u4TestModeV0[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0));
3318 mcSHOW_DBG_MSG5(("DRAMC_REG_MRS[0x%x]\n", u4TestModeV0[i]));
3319 u4TestModeV1[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
3320 mcSHOW_DBG_MSG5(("DRAMC_REG_DRAMC_PD_CTRL[0x%x]\n", u4TestModeV1[i]));
3321 u4TestModeV2[i] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL));
3322 mcSHOW_DBG_MSG5(("DRAMC_REG_STBCAL[0x%x]\n", u4TestModeV2[i]));
3323 u4TestModeV3[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0));
3324 mcSHOW_DBG_MSG5(("DRAMC_REG_REFCTRL0[0x%x]\n", u4TestModeV3[i]));
3325 u4TestModeV4[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_HMR4));
3326 mcSHOW_DBG_MSG5(("DRAMC_REG_SPCMDCTRL[0x%x]\n", u4TestModeV4[i]));
3327 u4TestModeV5[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
3328 mcSHOW_DBG_MSG5(("DRAMC_REG_CKECTRL[0x%x]\n", u4TestModeV5[i]));
3329 u4TestModeV6[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE));
3330 mcSHOW_DBG_MSG5(("DRAMC_REG_SLP4_TESTMODE[0x%x]\n", u4TestModeV6[i]));
3331 p->channel = CHANNEL_B;
3332 }
3333 p->channel = eOriChannel;
3334 return;
3335
3336 }
3337
RestoreRGBeforeTestMode(DRAMC_CTX_T * p)3338 static void RestoreRGBeforeTestMode(DRAMC_CTX_T *p)
3339 {
3340 DRAM_CHANNEL_T eOriChannel = p->channel;
3341 int i = 0;
3342 p->channel = CHANNEL_A;
3343 for (i = 0; i < 2; i++)
3344 {
3345 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u4TestModeV0[i]);
3346 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4TestModeV1[i]);
3347 vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), u4TestModeV2[i]);
3348 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), u4TestModeV3[i]);
3349 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_HMR4), u4TestModeV4[i]);
3350 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4TestModeV5[i]);
3351 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), u4TestModeV6[i]);
3352
3353 p->channel = CHANNEL_B;
3354 }
3355 p->channel = eOriChannel;
3356 return;
3357 }
3358
ProgramModeEnter(DRAMC_CTX_T * p)3359 void ProgramModeEnter(DRAMC_CTX_T *p)
3360 {
3361 DRAM_CHANNEL_T eOriChannel = p->channel;
3362 U8 i = 0;
3363 U8 j = 0;
3364 U8 k = 0;
3365 U8 u1Rank = 0;
3366
3367 BackupRGBeforeTestMode(p);
3368 p->channel = CHANNEL_A;
3369 mcSHOW_DBG_MSG3(("ProgramModeEnter [Begin]\n"));
3370
3371 for (i = 0; i < 4; i++)
3372 {
3373 for (j = 0; j < 6; j++)
3374 {
3375 mcSHOW_DBG_MSG3(("Key[%d] CA[%d] => [%d]\n", i, j, PME_Key[i][j]));
3376 }
3377 mcSHOW_DBG_MSG3(("\n"));
3378 }
3379
3380 for (i = 0; i < p->support_channel_num; i++)
3381 {
3382 if (i == 0)
3383 {
3384 mcSHOW_DBG_MSG3(("***CHA\n"));
3385 }
3386 else
3387 {
3388 mcSHOW_DBG_MSG3(("***CHB\n"));
3389 }
3390 for (j = 0; j < p->support_rank_num; j++)
3391 {
3392 if (j == 0)
3393 {
3394 u1Rank = 0;
3395 mcSHOW_DBG_MSG3(("***R0\n"));
3396 }
3397 else
3398 {
3399 u1Rank = 1;
3400 mcSHOW_DBG_MSG3(("***R1\n"));
3401 }
3402 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK);
3403
3404
3405 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_DCMEN);
3406 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_PHYCLKDYNGEN);
3407 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_DQSIENCG_NORMAL_EN);
3408
3409
3410 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 1, REFCTRL0_REFDIS);
3411 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_REFRDIS);
3412 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), 1, CKECTRL_CKEFIXON);
3413
3414 for (k = 0; k < 4; k++)
3415 {
3416 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PME_Key[k][0], SLP4_TESTMODE_CA0_TEST);
3417 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PME_Key[k][1], SLP4_TESTMODE_CA1_TEST);
3418 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PME_Key[k][2], SLP4_TESTMODE_CA2_TEST);
3419 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PME_Key[k][3], SLP4_TESTMODE_CA3_TEST);
3420 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PME_Key[k][4], SLP4_TESTMODE_CA4_TEST);
3421 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PME_Key[k][5], SLP4_TESTMODE_CA5_TEST);
3422
3423 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_STESTEN);
3424 while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_STEST_RESPONSE))
3425 {
3426 mcSHOW_DBG_MSG3(("status[%d]: %d\n", k, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_STEST_RESPONSE)));
3427 break;
3428 }
3429 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_STESTEN);
3430 }
3431 }
3432 p->channel = CHANNEL_B;
3433 }
3434 mcSHOW_DBG_MSG3(("ProgramModeEnter [Stop]\n"));
3435 p->channel = eOriChannel;
3436 RestoreRGBeforeTestMode(p);
3437 return;
3438 }
3439
ProgramCodeInput(DRAMC_CTX_T * p,U16 u2A_value,U16 u2B_value,U16 u2C_value)3440 void ProgramCodeInput(DRAMC_CTX_T *p, U16 u2A_value, U16 u2B_value, U16 u2C_value)
3441 {
3442 DRAM_CHANNEL_T eOriChannel = p->channel;
3443 U8 i = 0;
3444 U8 j = 0;
3445 U8 k = 0;
3446 int keyNumber = 0;
3447 U16 u2Value = 0;
3448 U8 u1Rank = 0;
3449
3450 BackupRGBeforeTestMode(p);
3451 p->channel = CHANNEL_A;
3452
3453 U8 PCI_Key[5][6] =
3454 {
3455 { 0, 0, 0, 0, 0, 0},
3456 { 0, 0, 0, 0, 0, 0},
3457 { 0, 0, 0, 0, 0, 0},
3458 { 2, 5, 1, 2, 0, 0},
3459 { 2, 5, 1, 2, 0, 0}
3460 };
3461
3462 mcSHOW_DBG_MSG3(("ProgramCodeInput [Begin]\n"));
3463
3464 for (keyNumber = 0; keyNumber < 3; keyNumber++)
3465 {
3466 if (keyNumber == 0)
3467 u2Value = u2A_value;
3468 else if (keyNumber == 1)
3469 u2Value = u2B_value;
3470 else
3471 u2Value = u2C_value;
3472
3473 PCI_Key[keyNumber][0] = (u2Value == 0)? (10): (2);
3474 PCI_Key[keyNumber][1] = (u2Value == 1)? (13): (5);
3475 PCI_Key[keyNumber][2] = (u2Value == 10)? (5): ((u2Value == 2)? (9): (1));
3476 PCI_Key[keyNumber][3] = (u2Value == 9)? (6): ((u2Value == 3)? (10): (2));
3477 PCI_Key[keyNumber][4] = (u2Value == 8)? (4): ((u2Value == 4)? (8): (0));
3478 PCI_Key[keyNumber][5] = (u2Value == 7)? (1): ((u2Value == 6)? (4): ((u2Value == 5)? (8): (0)));
3479 }
3480
3481 for (i = 0; i < 5; i++)
3482 {
3483 for (j = 0; j < 6; j++)
3484 {
3485 mcSHOW_DBG_MSG3(("Key[%d] CA[%d] => [%d]\n", i, j, PCI_Key[i][j]));
3486 }
3487 mcSHOW_DBG_MSG3(("\n"));
3488 }
3489
3490 for (i = 0; i < p->support_channel_num; i++)
3491 {
3492 if (i == 0)
3493 {
3494 mcSHOW_DBG_MSG3(("***CHA\n"));
3495 }
3496 else
3497 {
3498 mcSHOW_DBG_MSG3(("***CHB\n"));
3499 }
3500 for (j = 0; j < p->support_rank_num; j++)
3501 {
3502 if (j == 0)
3503 {
3504 u1Rank = 0;
3505 mcSHOW_DBG_MSG3(("***R0\n"));
3506 }
3507 else
3508 {
3509 u1Rank = 1;
3510 mcSHOW_DBG_MSG3(("***R1\n"));
3511 }
3512 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK);
3513
3514
3515 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_DCMEN);
3516 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_PHYCLKDYNGEN);
3517 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_DQSIENCG_NORMAL_EN);
3518
3519
3520 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 1, REFCTRL0_REFDIS);
3521 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_REFRDIS);
3522 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), 1, CKECTRL_CKEFIXON);
3523
3524 for (k = 0; k < 5; k++)
3525 {
3526 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PCI_Key[k][0], SLP4_TESTMODE_CA0_TEST);
3527 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PCI_Key[k][1], SLP4_TESTMODE_CA1_TEST);
3528 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PCI_Key[k][2], SLP4_TESTMODE_CA2_TEST);
3529 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PCI_Key[k][3], SLP4_TESTMODE_CA3_TEST);
3530 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PCI_Key[k][4], SLP4_TESTMODE_CA4_TEST);
3531 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PCI_Key[k][5], SLP4_TESTMODE_CA5_TEST);
3532
3533 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_STESTEN);
3534 while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_STEST_RESPONSE))
3535 {
3536 mcSHOW_DBG_MSG3(("status[%d]: %d\n", k, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_STEST_RESPONSE)));
3537 break;
3538 }
3539 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_STESTEN);
3540 }
3541 }
3542 p->channel = CHANNEL_B;
3543 }
3544 mcSHOW_DBG_MSG3(("ProgramCodeInput [Stop]\n"));
3545 p->channel = eOriChannel;
3546 RestoreRGBeforeTestMode(p);
3547 return;
3548 }
3549
vApplyProgramSequence(DRAMC_CTX_T * p)3550 void vApplyProgramSequence(DRAMC_CTX_T *p)
3551 {
3552 #if SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER == 1
3553
3554 ProgramModeEnter(p);
3555 ProgramCodeInput(p, 0, 0, 0);
3556 ProgramCodeInput(p, 3, 9, 0);
3557 ProgramCodeInput(p, 1, 2, 0);
3558 ProgramCodeInput(p, 8, 0xa, 7);
3559 ProgramCodeInput(p, 2, 5, 8);
3560 mcSHOW_DBG_MSG3(("Buffer sensitivity decrease1: TMRS enter -> 000 -> 390 -> 120 -> 8A7 -> 258\n"));
3561
3562 #elif SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER == 2
3563
3564 ProgramModeEnter(p);
3565 ProgramCodeInput(p, 0, 0, 0);
3566 ProgramCodeInput(p, 3, 9, 0);
3567 ProgramCodeInput(p, 1, 2, 0);
3568 ProgramCodeInput(p, 8, 0, 3);
3569 ProgramCodeInput(p, 2, 5, 8);
3570 mcSHOW_DBG_MSG3(("Buffer sensitivity decrease1: TMRS enter -> 000 -> 390 -> 120 -> 803 -> 258\n"));
3571
3572 #elif SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER == 3
3573
3574 ProgramModeEnter(p);
3575 ProgramCodeInput(p, 0, 0, 0);
3576 ProgramCodeInput(p, 3, 9, 0);
3577 ProgramCodeInput(p, 1, 2, 0);
3578 ProgramCodeInput(p, 0, 1, 4);
3579 ProgramCodeInput(p, 8, 6, 3);
3580 ProgramCodeInput(p, 2, 5, 8);
3581 mcSHOW_DBG_MSG3(("2014 + 2863: test 4.TMRS enter -> 000 -> 390 -> 120 -> 014 -> 863 -> 258\n"));
3582
3583 #elif SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER == 4
3584
3585 ProgramModeEnter(p);
3586 ProgramCodeInput(p, 0, 0, 0);
3587 ProgramCodeInput(p, 3, 9, 0);
3588 ProgramCodeInput(p, 1, 2, 0);
3589 ProgramCodeInput(p, 5, 2, 0xa);
3590 ProgramCodeInput(p, 2, 5, 8);
3591 mcSHOW_DBG_MSG3(("252A: test 5. TMRS enter -> 000 -> 390 -> 120 -> 52A -> 258\n"));
3592
3593 #elif SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER == 5
3594 mcSHOW_DBG_MSG3(("Trigger Samsung Test mode after 5 sec\n"));
3595 mcDELAY_MS(5000);
3596 while(1)
3597 {
3598 ProgramModeEnter(p);
3599 }
3600
3601 #else
3602
3603 ProgramModeEnter(p);
3604 ProgramCodeInput(p, 0, 0, 0);
3605 ProgramCodeInput(p, 3, 9, 0);
3606 ProgramCodeInput(p, 0, 2, 1);
3607 ProgramCodeInput(p, 2, 5, 8);
3608 mcSHOW_DBG_MSG3(("Buffer sensitivity decrease1: TMRS enter -> 000 -> 390 -> 021\n"));
3609 #endif
3610 }
3611 #endif
3612
3613 #if 0
3614 void Hynix_Test_Mode(DRAMC_CTX_T *p)
3615 {
3616 #if MRW_CHECK_ONLY
3617 mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
3618 #endif
3619
3620 DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xb8);
3621 DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xe8);
3622 DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0x98);
3623 DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xbf);
3624 DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xef);
3625 DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0x9f);
3626 DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xb9);
3627 DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xe9);
3628 DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0x99);
3629 DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xd8);
3630 DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0x88);
3631 DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xa3);
3632 DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xe0);
3633 }
3634 #endif
3635
3636 #if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION
DramcRunTimeShmooRG_BackupRestore(DRAMC_CTX_T * p)3637 void DramcRunTimeShmooRG_BackupRestore(DRAMC_CTX_T *p)
3638 {
3639 U8 channel_idx, channel_backup;
3640 U32 ii, u4RgBackupNum, *u4RG_Backup = 0;
3641
3642 channel_backup = vGetPHY2ChannelMapping(p);
3643
3644 for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
3645 {
3646 vSetPHY2ChannelMapping(p, channel_idx);
3647
3648 U32 u4RegBackupAddress[] =
3649 {
3650
3651 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ5)),
3652 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ5)),
3653
3654 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0)),
3655 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY1)),
3656 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY2)),
3657 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY3)),
3658 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4)),
3659 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5)),
3660 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0)),
3661 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY1)),
3662 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY2)),
3663 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY3)),
3664 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4)),
3665 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5)),
3666
3667 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0+DDRPHY_AO_RANK_OFFSET)),
3668 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY1+DDRPHY_AO_RANK_OFFSET)),
3669 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY2+DDRPHY_AO_RANK_OFFSET)),
3670 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY3+DDRPHY_AO_RANK_OFFSET)),
3671 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4+DDRPHY_AO_RANK_OFFSET)),
3672 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5+DDRPHY_AO_RANK_OFFSET)),
3673 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0+DDRPHY_AO_RANK_OFFSET)),
3674 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY1+DDRPHY_AO_RANK_OFFSET)),
3675 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY2+DDRPHY_AO_RANK_OFFSET)),
3676 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY3+DDRPHY_AO_RANK_OFFSET)),
3677 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4+DDRPHY_AO_RANK_OFFSET)),
3678 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5+DDRPHY_AO_RANK_OFFSET)),
3679
3680
3681
3682
3683 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI)),
3684 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0)),
3685 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1)),
3686 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2)),
3687 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3)),
3688 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL1)),
3689 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL2)),
3690 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL5)),
3691
3692 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0)),
3693 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1)),
3694 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0)),
3695 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1)),
3696 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3)),
3697 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3)),
3698 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)),
3699 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)),
3700
3701
3702
3703 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI+DRAMC_REG_AO_RANK_OFFSET )),
3704 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0+DRAMC_REG_AO_RANK_OFFSET)),
3705 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1+DRAMC_REG_AO_RANK_OFFSET)),
3706 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2+DRAMC_REG_AO_RANK_OFFSET)),
3707 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3+DRAMC_REG_AO_RANK_OFFSET)),
3708 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL1+DRAMC_REG_AO_RANK_OFFSET)),
3709 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL2+DRAMC_REG_AO_RANK_OFFSET)),
3710 (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL5+DRAMC_REG_AO_RANK_OFFSET)),
3711
3712 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0+DDRPHY_AO_RANK_OFFSET)),
3713 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1+DDRPHY_AO_RANK_OFFSET)),
3714 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0+DDRPHY_AO_RANK_OFFSET)),
3715 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1+DDRPHY_AO_RANK_OFFSET)),
3716 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3+DDRPHY_AO_RANK_OFFSET)),
3717 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3+DDRPHY_AO_RANK_OFFSET)),
3718 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0+DDRPHY_AO_RANK_OFFSET)),
3719 (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0+DDRPHY_AO_RANK_OFFSET)),
3720 //(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0+DDRPHY_AO_RANK_OFFSET)),
3721 };
3722 u4RgBackupNum = sizeof(u4RegBackupAddress) >> 2;
3723 u4RG_Backup = (U32*)(p->pSavetimeData->u4RG_Backup[channel_idx]);
3724
3725 for (ii = 0; ii < u4RgBackupNum; ii++)
3726 {
3727 if (ii >= RUNTIME_SHMOO_RG_BACKUP_NUM)
3728 {
3729 mcSHOW_DBG_MSG(("\nRuntime Shmoo Backup/Restore buffer(%d) empty!!\n", RUNTIME_SHMOO_RG_BACKUP_NUM));
3730 while (1);
3731 }
3732 if (u1IsLP4Family(p->dram_type) && (p->femmc_Ready == 0))
3733 {
3734 *(U32*)(u4RG_Backup + ii) = u4IO32Read4B(u4RegBackupAddress[ii]);
3735 mcSHOW_DBG_MSG(("=== run time shmoo backup : *(U32*)(0x%x) = 0x%x\n", u4RegBackupAddress[ii], *(U32*)(u4RG_Backup + ii)));
3736 }
3737 else
3738 {
3739 vIO32Write4B(u4RegBackupAddress[ii], *(U32*)(u4RG_Backup + ii));
3740 mcSHOW_DBG_MSG(("=== run time shmoo restore: *(U32*)(0x%x) = 0x%x\n", u4RegBackupAddress[ii], *(U32*)(u4RG_Backup + ii)));
3741 }
3742 }
3743 }
3744 vSetPHY2ChannelMapping(p, channel_backup);
3745
3746 //DramcRegDump(p);
3747 }
3748 #endif
3749
3750 #if VERIFY_CKE_PWR_DOWN_FLOW
CKEFixOnOff_dbg(DRAMC_CTX_T * p,U8 u1RankIdx,CKE_FIX_OPTION option,CHANNEL_RANK_SEL_T WriteChannelNUM)3751 void CKEFixOnOff_dbg(DRAMC_CTX_T *p, U8 u1RankIdx, CKE_FIX_OPTION option, CHANNEL_RANK_SEL_T WriteChannelNUM)
3752 {
3753 U8 u1CKEOn, u1CKEOff, u1setChannel, u1BackupChannel;
3754
3755 if (option == CKE_DYNAMIC)
3756 {
3757 u1CKEOn = u1CKEOff = 0;
3758 }
3759 else
3760 {
3761 u1CKEOn = option;
3762 u1CKEOff = (1 - option);
3763 }
3764
3765 if (WriteChannelNUM == TO_ALL_CHANNEL)
3766 {
3767 if((u1RankIdx == RANK_0)||(u1RankIdx == TO_ALL_RANK))
3768 {
3769 vIO32WriteFldMulti_All(DRAMC_REG_DCM_CTRL0, P_Fld(u1CKEOff, DCM_CTRL0_DBG_CKEFIXOFF)
3770 | P_Fld(u1CKEOn, DCM_CTRL0_DBG_CKEFIXON));
3771 }
3772
3773 if(u1RankIdx == RANK_1||((u1RankIdx == TO_ALL_RANK) && (p->support_rank_num == RANK_DUAL)))
3774 {
3775 vIO32WriteFldMulti_All(DRAMC_REG_DCM_CTRL0, P_Fld(u1CKEOff, DCM_CTRL0_DBG_CKE1FIXOFF)
3776 | P_Fld(u1CKEOn, DCM_CTRL0_DBG_CKE1FIXON));
3777 }
3778 }
3779 else
3780 {
3781 if((u1RankIdx == RANK_0) || (u1RankIdx == TO_ALL_RANK))
3782 {
3783 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DCM_CTRL0), P_Fld(u1CKEOff, DCM_CTRL0_DBG_CKEFIXOFF)
3784 | P_Fld(u1CKEOn, DCM_CTRL0_DBG_CKEFIXON));
3785 }
3786
3787 if((u1RankIdx == RANK_1) ||((u1RankIdx == TO_ALL_RANK) && (p->support_rank_num == RANK_DUAL)))
3788 {
3789 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DCM_CTRL0), P_Fld(u1CKEOff, DCM_CTRL0_DBG_CKE1FIXOFF)
3790 | P_Fld(u1CKEOn, DCM_CTRL0_DBG_CKE1FIXON));
3791 }
3792 }
3793 }
3794
DramcModeRegWrite_DcmOff(DRAMC_CTX_T * p,U8 u1MRIdx,U8 u1Value)3795 void DramcModeRegWrite_DcmOff(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Value)
3796 {
3797 U32 u4register_dcm;
3798 mcSHOW_DBG_MSG3(("### Write_lewis ###\n"));
3799
3800 u4register_dcm = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
3801
3802 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_MIOCKCTRLOFF);
3803 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_DCMEN2);
3804 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_PHYCLKDYNGEN);
3805
3806 DramcModeRegWrite_111(p, u1MRIdx, u1Value);
3807
3808 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4register_dcm);
3809 }
3810 #endif
3811
3812
3813 #if 0
3814 void Get_TA2_ST(DRAMC_CTX_T *p)
3815 {
3816 U32 u4Value = 0;
3817
3818 u4Value = u4IO32Read4B(DRAMC_REG_TESTRPT);
3819 mcSHOW_DBG_MSG(("DRAMC_REG_TESTRPT: 0x%x \n", u4Value));
3820 }
3821
3822 void Get_TA2_ErrCnt(DRAMC_CTX_T *p)
3823 {
3824 U32 u4Value = 0xffffffff;
3825 DRAM_CHANNEL_T channelIdx;
3826 DRAM_CHANNEL_T bkchannel = p->channel;
3827
3828 for(channelIdx=CHANNEL_A; channelIdx<(p->support_channel_num); channelIdx++)
3829 {
3830 vSetPHY2ChannelMapping(p, channelIdx);
3831 mcSHOW_DBG_MSG(("CH[%d]\n", channelIdx));
3832
3833 u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_FLAG0));
3834 mcSHOW_DBG_MSG(("flag 148:0x%x ", u4Value));
3835
3836 u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_FLAG1));
3837 mcSHOW_DBG_MSG(("flag 14C:0x%x\n", u4Value));
3838
3839 {
3840
3841 //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), iByte, TEST2_A3_ERRFLAG_BYTE_SEL);
3842
3843
3844 u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT1));
3845 mcSHOW_DBG_MSG(("150:0x%x ", u4Value));
3846
3847 u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT2));
3848 mcSHOW_DBG_MSG(("154:0x%x ", u4Value));
3849
3850 u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT3));
3851 mcSHOW_DBG_MSG(("158:0x%x ", u4Value));
3852
3853 u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT4));
3854 mcSHOW_DBG_MSG(("15C:0x%x ", u4Value));
3855
3856 u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT5));
3857 mcSHOW_DBG_MSG(("160:0x%x ", u4Value));
3858
3859 u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT6));
3860 mcSHOW_DBG_MSG(("164:0x%x ", u4Value));
3861
3862 u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT7));
3863 mcSHOW_DBG_MSG(("168:0x%x ", u4Value));
3864
3865 u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT8));
3866 mcSHOW_DBG_MSG(("16C:0x%x\n", u4Value));
3867 }
3868 }
3869 vSetPHY2ChannelMapping(p, bkchannel);
3870 }
3871
3872 void Modify_TX_Delay_Cell(DRAMC_CTX_T *p, int i)
3873 {
3874 U16 u2DelayCellOfst[16] = {0};
3875 U32 u4value = (i<8) ? 0 : 1;
3876
3877 if(i<16)
3878 {
3879 u2DelayCellOfst[i] = 0xffff;
3880 }
3881 else
3882 {
3883 mcSHOW_DBG_MSG(("!Error input, hang....\n"));
3884 while(1);
3885 }
3886
3887
3888 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), u4value, TEST2_A3_ERRFLAG_BYTE_SEL);
3889 mcSHOW_DBG_MSG(("********** Modify_TX_Delay_Cell %d **********\n", i));
3890
3891 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0),
3892 P_Fld(u2DelayCellOfst[3], SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)
3893 | P_Fld(u2DelayCellOfst[2], SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0)
3894 | P_Fld(u2DelayCellOfst[1], SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0)
3895 | P_Fld(u2DelayCellOfst[0], SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0));
3896 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1),
3897 P_Fld(u2DelayCellOfst[7], SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)
3898 | P_Fld(u2DelayCellOfst[6], SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0)
3899 | P_Fld(u2DelayCellOfst[5], SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0)
3900 | P_Fld(u2DelayCellOfst[4], SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0));
3901 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0),
3902 P_Fld(u2DelayCellOfst[11], SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)
3903 | P_Fld(u2DelayCellOfst[10], SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1)
3904 | P_Fld(u2DelayCellOfst[9], SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1)
3905 | P_Fld(u2DelayCellOfst[8], SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1));
3906 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1),
3907 P_Fld(u2DelayCellOfst[15], SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)
3908 | P_Fld(u2DelayCellOfst[14], SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1)
3909 | P_Fld(u2DelayCellOfst[13], SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1)
3910 | P_Fld(u2DelayCellOfst[12], SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1));
3911
3912 //Read_TX_Delay_Cell(p);
3913
3914 return;
3915 }
3916 #endif
3917
3918 #if 0
3919 void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)
3920 {
3921 int i=0;
3922 U32 u4BackupDQSOSCENDIS = 0;
3923 U8 u1ShuLevel = 0;
3924 U8 channelIdx, channelBak;
3925 U8 rankIdx, rankBak;
3926 U32 u4RegBackupAddress[] =
3927 {
3928 (DRAMC_REG_HMR4),
3929 (DRAMC_REG_DQSOSCR),
3930 (DRAMC_REG_DUMMY_RD),
3931 #if CHANNEL_NUM > 1
3932 (DRAMC_REG_HMR4+SHIFT_TO_CHB_ADDR),
3933 (DRAMC_REG_DQSOSCR+SHIFT_TO_CHB_ADDR),
3934 (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHB_ADDR),
3935 #endif
3936 #if CHANNEL_NUM > 2
3937 (DRAMC_REG_HMR4+SHIFT_TO_CHC_ADDR),
3938 (DRAMC_REG_DQSOSCR+SHIFT_TO_CHC_ADDR),
3939 (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHC_ADDR),
3940 (DRAMC_REG_HMR4+SHIFT_TO_CHD_ADDR),
3941 (DRAMC_REG_DQSOSCR+SHIFT_TO_CHD_ADDR),
3942 (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHD_ADDR),
3943 #endif
3944 };
3945
3946 #ifdef FAKE_ENGINE_STRESS
3947 if(u1IsLP4Family(p->dram_type))
3948 {
3949 Fake_Engine_Presetting(p, 0);
3950 }
3951 #endif
3952
3953 //DramcEngine2SetPat(p, TEST_XTALK_PATTERN, p->support_rank_num - 1, 0);//bug only one channel
3954 TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF);
3955 do {
3956 while(u1StopMiniStress){mcDELAY_MS(1000);}
3957
3958 #ifdef TA2_STRESS
3959
3960
3961 TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_HW);
3962 TA2_Test_Run_Time_HW_Write(p, ENABLE);
3963 #endif
3964
3965 #ifdef FAKE_ENGINE_STRESS
3966 if(u1IsLP4Family(p->dram_type))
3967 {
3968 static U8 trans_type = W;
3969 Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 3);
3970 }
3971 #endif
3972 Get_TA2_ErrCnt(p);
3973
3974 #ifdef TA2_STRESS
3975 TA2_Test_Run_Time_HW_Status(p);
3976 #endif
3977
3978
3979 vSetPHY2ChannelMapping(p, (i++) % p->support_channel_num);
3980 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \
3981 P_Fld(7, SHURK_SELPH_DQ0_TXDLY_DQ0))
3982 //vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2),
3983 // P_Fld(6, SHURK_SELPH_DQ2_DLY_DQ0));
3984
3985 //vSetRank(p, RANK_1);
3986 //Modify_TX_Delay_Cell(p, (i++)%16); //Delay cell
3987 //vSetRank(p, RANK_0);
3988 } while(1);
3989 return;
3990 }
3991 #endif
3992
3993 #if 0
3994 void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)
3995 {
3996 U32 u4BackupDQSOSCENDIS = 0;
3997 U8 u1ShuLevel = 0;
3998 U8 channelIdx, channelBak;
3999 U8 rankIdx, rankBak;
4000 U32 u4RegBackupAddress[] =
4001 {
4002 (DRAMC_REG_HMR4),
4003 (DRAMC_REG_DQSOSCR),
4004 (DRAMC_REG_DUMMY_RD),
4005 #if CHANNEL_NUM > 1
4006 (DRAMC_REG_HMR4+SHIFT_TO_CHB_ADDR),
4007 (DRAMC_REG_DQSOSCR+SHIFT_TO_CHB_ADDR),
4008 (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHB_ADDR),
4009 #endif
4010 #if CHANNEL_NUM > 2
4011 (DRAMC_REG_HMR4+SHIFT_TO_CHC_ADDR),
4012 (DRAMC_REG_DQSOSCR+SHIFT_TO_CHC_ADDR),
4013 (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHC_ADDR),
4014 (DRAMC_REG_HMR4+SHIFT_TO_CHD_ADDR),
4015 (DRAMC_REG_DQSOSCR+SHIFT_TO_CHD_ADDR),
4016 (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHD_ADDR),
4017 #endif
4018 };
4019
4020 #ifdef FAKE_ENGINE_STRESS
4021 if(u1IsLP4Family(p->dram_type))
4022 {
4023 Fake_Engine_Presetting(p, 0);
4024 }
4025 #endif
4026
4027 TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF);
4028
4029 do {
4030 while(u1StopMiniStress){mcDELAY_MS(1000);}
4031
4032 #ifdef TA2_STRESS
4033 if (p->support_rank_num==RANK_DUAL)
4034 {
4035 DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
4036
4037
4038 vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0x1, HMR4_REFRDIS);
4039 u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_MISC_DVFSCTL, MISC_DVFSCTL_R_OTHER_SHU_GP);
4040 u4BackupDQSOSCENDIS = u4IO32Read4B(DRAMC_REG_SHU_DQSOSC_SET0 + (SHU_GRP_DRAMC_OFFSET * u1ShuLevel));
4041 vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS);
4042 vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0+(SHU_GRP_DRAMC_OFFSET*u1ShuLevel), 0x1, SHU_DQSOSC_SET0_DQSOSCENDIS);
4043 vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN)
4044 | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN)
4045 | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN)
4046 | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG));
4047
4048 //TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON);
4049 TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_XRT);
4050 TA2_Test_Run_Time_HW_Write(p, ENABLE);
4051 TA2_Test_Run_Time_HW_Status(p);
4052 }
4053 #endif
4054
4055 #ifdef TA2_STRESS
4056
4057 //TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON);
4058 TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_HW);
4059 //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x10, TEST2_A2_TEST2_OFF);
4060
4061
4062 if (p->support_rank_num==RANK_DUAL)
4063 {
4064
4065 vIO32Write4B_All(DRAMC_REG_SHU_DQSOSC_SET0+(SHU_GRP_DRAMC_OFFSET*u1ShuLevel), u4BackupDQSOSCENDIS);
4066 DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
4067 }
4068 TA2_Test_Run_Time_HW_Write(p, ENABLE);
4069 #endif
4070
4071 #ifdef FAKE_ENGINE_STRESS
4072 if(u1IsLP4Family(p->dram_type))
4073 {
4074
4075 //Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 2);
4076 static U8 trans_type = W;
4077 Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 3);
4078 //Do_Memory_Test_Fake_Engine_Presetting(p, W);
4079 }
4080 #endif
4081
4082 #if (DRAMC_DFS_MODE != 3)
4083 DFSTestProgram(p, 0);
4084 #else
4085 GetPhyPllFrequency(p);
4086 #endif
4087
4088 #ifdef TA2_STRESS
4089 TA2_Test_Run_Time_HW_Status(p);
4090 #endif
4091
4092 #ifdef FAKE_ENGINE_STRESS
4093 if(u1IsLP4Family(p->dram_type))
4094 {
4095 Disable_Fake_Engine();
4096 }
4097 #endif
4098
4099 #ifdef ENABLE_SW_RUN_TIME_ZQ_WA
4100 DramcRunTimeSWZQ(p);
4101 #endif
4102
4103 static int cnt=0;
4104 //if ((++cnt&0x7F)==0)
4105 if (1)
4106 {
4107 MR_periodic_check(p);
4108 #ifdef COMPLEX_STRESS
4109 int s4value, num;
4110 U32 ii, addr[] = {
4111 0x40024000,
4112 0x56000000,
4113 0x80000000,
4114 };
4115 num = sizeof(addr)>>2;
4116 for(ii=0;ii<(U32)num;ii++)
4117 {
4118 s4value = dramc_complex_mem_test (addr[ii], 0x20000);
4119 mcSHOW_DBG_MSG(("complex R/W mem 0x%x test %s: %d\n",addr[ii],s4value?"fail":"pass",-s4value));
4120 }
4121 #endif
4122 }
4123
4124
4125 #if ENABLE_SW_TX_TRACKING
4126 channelBak = vGetPHY2ChannelMapping(p);
4127 rankBak = u1GetRank(p);
4128 for(channelIdx=CHANNEL_A; channelIdx<(p->support_channel_num); channelIdx++)
4129 {
4130 vSetPHY2ChannelMapping(p, channelIdx);
4131 DramcSWTxTracking(p);
4132 }
4133 vSetRank(p, rankBak);
4134 vSetPHY2ChannelMapping(p, channelBak);
4135 #endif
4136 //DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
4137 } while(1);
4138 return;
4139
4140 }
4141 #endif
4142
4143 #if 0
4144 void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)
4145 {
4146 int i=0;
4147
4148 #ifdef FAKE_ENGINE_STRESS
4149 if(u1IsLP4Family(p->dram_type))
4150 {
4151 Fake_Engine_Presetting(p, 0);
4152 }
4153 #endif
4154
4155 TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF);
4156 TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_HW);
4157
4158 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_TA2_LOOP_EN);
4159 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_LOOP_NV_END);
4160 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_ERR_BREAK_EN);
4161 TA2_Test_Run_Time_HW_Write(p, ENABLE);
4162 do {
4163 while(u1StopMiniStress){mcDELAY_MS(1000);}
4164
4165 #ifdef FAKE_ENGINE_STRESS
4166 if(u1IsLP4Family(p->dram_type))
4167 {
4168 static U8 trans_type = W;
4169 Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 3);
4170 }
4171 #endif
4172 //Get_TA2_ErrCnt(p);
4173 Get_TA2_ST(p);
4174
4175
4176 if(i==20)
4177 {
4178 mcSHOW_DBG_MSG(("!!! Error Injection in CHA\n"));
4179
4180 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \
4181 P_Fld(7, SHURK_SELPH_DQ0_TXDLY_DQ0))
4182 }
4183 i++;
4184 } while(1);
4185 return;
4186 }
4187 #endif
4188
4189 #if 0
4190 typedef enum
4191 {
4192 SIDLE_SR_S1_S0 = 0,
4193 SIDLE_SR_S1,
4194 } ETT_STRESS_LPS;
4195 void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)
4196 {
4197 U32 u4BackupDQSOSCENDIS = 0;
4198 U8 u1ShuLevel = 0;
4199 bool bTa2_stress_enable = FALSE;
4200 ETT_STRESS_LPS bLowPwrState = SIDLE_SR_S1_S0;
4201 int iTestCnt = 0;
4202
4203 U32 u4RegBackupAddress[] =
4204 {
4205 (DRAMC_REG_HMR4),
4206 (DRAMC_REG_DQSOSCR),
4207 (DRAMC_REG_DUMMY_RD),
4208 #if CHANNEL_NUM > 1
4209 (DRAMC_REG_HMR4+SHIFT_TO_CHB_ADDR),
4210 (DRAMC_REG_DQSOSCR+SHIFT_TO_CHB_ADDR),
4211 (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHB_ADDR),
4212 #endif
4213 #if CHANNEL_NUM > 2
4214 (DRAMC_REG_HMR4+SHIFT_TO_CHC_ADDR),
4215 (DRAMC_REG_DQSOSCR+SHIFT_TO_CHC_ADDR),
4216 (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHC_ADDR),
4217 (DRAMC_REG_HMR4+SHIFT_TO_CHD_ADDR),
4218 (DRAMC_REG_DQSOSCR+SHIFT_TO_CHD_ADDR),
4219 (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHD_ADDR),
4220 #endif
4221 };
4222
4223 #ifdef FAKE_ENGINE_STRESS
4224 if(u1IsLP4Family(p->dram_type))
4225 {
4226 Fake_Engine_Presetting(p, 0);
4227 }
4228 #endif
4229
4230 do {
4231 while(u1StopMiniStress){mcDELAY_MS(1000);}
4232 #if 1
4233 if(iTestCnt % 10 == 0)
4234 {
4235 bLowPwrState = (bLowPwrState == SIDLE_SR_S1_S0) ? (SIDLE_SR_S1) : (SIDLE_SR_S1_S0);
4236
4237 mcSHOW_DBG_MSG(("*** Stop delay then start\n"));
4238 Reg_Sync_Writel(0x10940020, 0x00000000);
4239 Reg_Sync_Writel(0x10A40020, 0x00000000);
4240
4241 Reg_Sync_Writel(0x10940028, 0x00000003);
4242 Reg_Sync_Writel(0x10A40028, 0x00000003);
4243
4244 Reg_Sync_Writel(0x109400A0, 1);
4245 Reg_Sync_Writel(0x10A400A0, 1);
4246
4247 mcDELAY_MS(100);
4248
4249 if(bLowPwrState == SIDLE_SR_S1_S0)
4250 {
4251 mcSHOW_DBG_MSG(("*** SIDLE_SR_S1_S0\n"));
4252
4253 Reg_Sync_Writel(0x10940020, 0x00010203);
4254 Reg_Sync_Writel(0x10A40020, 0x00010203);
4255
4256 Reg_Sync_Writel(0x10940028, 0x80000004);
4257 Reg_Sync_Writel(0x10A40028, 0x80000004);
4258 bTa2_stress_enable = 0;
4259 }
4260 else
4261 {
4262 mcSHOW_DBG_MSG(("*** SIDLE_SR_S1 stop then start\n"));
4263
4264 Reg_Sync_Writel(0x10940020, 0x00010200);
4265 Reg_Sync_Writel(0x10A40020, 0x00010200);
4266
4267 Reg_Sync_Writel(0x10940028, 0x80000003);
4268 Reg_Sync_Writel(0x10A40028, 0x80000003);
4269 bTa2_stress_enable = 1;
4270 }
4271 Reg_Sync_Writel(0x109400A0, 1);
4272 Reg_Sync_Writel(0x10A400A0, 1);
4273 }
4274 iTestCnt++;
4275 #endif
4276 #if 0
4277 if(iTestCnt % 10 == 0)
4278 {
4279 bLowPwrState = (bLowPwrState == SIDLE_SR_S1_S0) ? (SIDLE_SR_S1) : (SIDLE_SR_S1_S0);
4280
4281 mcSHOW_DBG_MSG(("*** Stop delay then start\n"));
4282 Reg_Sync_Writel(0x10940020, 0x00000000);
4283 Reg_Sync_Writel(0x10A40020, 0x00000000);
4284
4285 Reg_Sync_Writel(0x10940028, 0x00000003);
4286 Reg_Sync_Writel(0x10A40028, 0x00000003);
4287
4288 Reg_Sync_Writel(0x109400A0, 1);
4289 Reg_Sync_Writel(0x10A400A0, 1);
4290
4291 if(bLowPwrState == SIDLE_SR_S1_S0)
4292 {
4293 mcSHOW_DBG_MSG(("*** SIDLE_SR_S1_S0\n"));
4294
4295 Reg_Sync_Writel(0x10940020, 0x00010300);
4296 Reg_Sync_Writel(0x10A40020, 0x00010300);
4297
4298 Reg_Sync_Writel(0x10940024, 0x13121110);
4299 Reg_Sync_Writel(0x10A40024, 0x13121110);
4300
4301 Reg_Sync_Writel(0x10940028, 0x80000008);
4302 Reg_Sync_Writel(0x10A40028, 0x80000008);
4303 bTa2_stress_enable = 0;
4304 }
4305 else
4306 {
4307 mcSHOW_DBG_MSG(("*** SIDLE_SR_S1\n"));
4308
4309 Reg_Sync_Writel(0x10940020, 0x00010200);
4310 Reg_Sync_Writel(0x10A40020, 0x00010200);
4311
4312 Reg_Sync_Writel(0x10940024, 0x13121110);
4313 Reg_Sync_Writel(0x10A40024, 0x13121110);
4314
4315 Reg_Sync_Writel(0x10940028, 0x80000008);
4316 Reg_Sync_Writel(0x10A40028, 0x80000008);
4317 bTa2_stress_enable = 1;
4318 }
4319 Reg_Sync_Writel(0x109400A0, 1);
4320 Reg_Sync_Writel(0x10A400A0, 1);
4321 }
4322 iTestCnt++;
4323 #endif
4324
4325
4326 #if 0
4327 if(iTestCnt % 10 == 0)
4328 {
4329 bLowPwrState = (bLowPwrState == SIDLE_SR_S1_S0) ? (SIDLE_SR_S1) : (SIDLE_SR_S1_S0);
4330 if(bLowPwrState == SIDLE_SR_S1_S0)
4331 {
4332 mcSHOW_DBG_MSG(("*** SIDLE_SR_S1_S0\n"));
4333
4334 Reg_Sync_Writel(0x10940020, 0x12111000);
4335 Reg_Sync_Writel(0x10A40020, 0x12111000);
4336
4337 Reg_Sync_Writel(0x10940024, 0x16151413);
4338 Reg_Sync_Writel(0x10A40024, 0x16151413);
4339
4340 Reg_Sync_Writel(0x10940028, 0x80000008);
4341 Reg_Sync_Writel(0x10A40028, 0x80000008);
4342 bTa2_stress_enable = 0;
4343 }
4344 else
4345 {
4346 mcSHOW_DBG_MSG(("*** SIDLE_SR_S1\n"));
4347
4348 Reg_Sync_Writel(0x10940020, 0x12111000);
4349 Reg_Sync_Writel(0x10A40020, 0x12111000);
4350
4351 Reg_Sync_Writel(0x10940024, 0x16151413);
4352 Reg_Sync_Writel(0x10A40024, 0x16151413);
4353
4354 Reg_Sync_Writel(0x10940028, 0x80000008);
4355 Reg_Sync_Writel(0x10A40028, 0x80000008);
4356 bTa2_stress_enable = 1;
4357 }
4358 Reg_Sync_Writel(0x109400A0, 1);
4359 Reg_Sync_Writel(0x10A400A0, 1);
4360 }
4361 iTestCnt++;
4362 #endif
4363
4364
4365
4366 #ifdef TA2_STRESS
4367 if(bTa2_stress_enable)
4368 {
4369 if (p->support_rank_num==RANK_DUAL)
4370 {
4371 DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
4372
4373
4374 vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0x1, HMR4_REFRDIS);
4375 u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_MISC_DVFSCTL, MISC_DVFSCTL_R_OTHER_SHU_GP);
4376 u4BackupDQSOSCENDIS = u4IO32Read4B(DRAMC_REG_SHU_DQSOSC_SET0 + (SHU_GRP_DRAMC_OFFSET * u1ShuLevel));
4377 vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS);
4378 vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0+(SHU_GRP_DRAMC_OFFSET*u1ShuLevel), 0x1, SHU_DQSOSC_SET0_DQSOSCENDIS);
4379 vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN)
4380 | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN)
4381 | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN)
4382 | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG));
4383
4384 TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON);
4385 TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_XRT);
4386 TA2_Test_Run_Time_HW_Write(p, ENABLE);
4387 TA2_Test_Run_Time_HW_Status(p);
4388 }
4389
4390
4391
4392 TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON);
4393 TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_HW);
4394 //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x10, TEST2_A2_TEST2_OFF);//TODO: Need to find out the reason
4395
4396
4397 if (p->support_rank_num==RANK_DUAL)
4398 {
4399
4400 vIO32Write4B_All(DRAMC_REG_SHU_DQSOSC_SET0+(SHU_GRP_DRAMC_OFFSET*u1ShuLevel), u4BackupDQSOSCENDIS);
4401 DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
4402 }
4403 TA2_Test_Run_Time_HW_Write(p, ENABLE);
4404 }
4405 #endif
4406
4407 #ifdef FAKE_ENGINE_STRESS
4408 if(u1IsLP4Family(p->dram_type))
4409 {
4410 //static U8 trans_type = W;
4411 //Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 2);
4412 static U8 trans_type = W;
4413 Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 3);
4414 //Do_Memory_Test_Fake_Engine_Presetting(p, W);
4415 }
4416 #endif
4417
4418
4419 #ifdef TA2_STRESS
4420 if(bTa2_stress_enable)
4421 {
4422 TA2_Test_Run_Time_HW_Status(p);
4423 }
4424 #endif
4425
4426 #ifdef FAKE_ENGINE_STRESS
4427 if(u1IsLP4Family(p->dram_type))
4428 {
4429 Disable_Fake_Engine();
4430 }
4431 #endif
4432
4433 static int cnt=0;
4434 //if ((++cnt&0x7F)==0)
4435 if (1)
4436 {
4437 MR_periodic_check(p);
4438 #ifdef COMPLEX_STRESS
4439 int s4value, num;
4440 U32 ii, addr[] = {
4441 0x40024000,
4442 0x56000000,
4443 0x80000000,
4444 };
4445 num = sizeof(addr)>>2;
4446 for(ii=0;ii<(U32)num;ii++)
4447 {
4448 s4value = dramc_complex_mem_test (addr[ii], 0x20000);
4449 mcSHOW_DBG_MSG(("[%d]complex R/W mem 0x%x test %s: %d\n",iTestCnt, addr[ii],s4value?"fail":"pass",-s4value));
4450 }
4451 #endif
4452 }
4453 //DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
4454 } while(1);
4455 return;
4456 }
4457 #endif
4458
4459
4460 //#ifdef ETT_MINI_STRESS_TEST
4461 #if 0
4462 //err |= aTA2_Test_Run_Time_HW_Status(p);
4463 unsigned int DPMIsAlive(DRAMC_CTX_T *p);
4464 void Ett_Mini_Strss_Test_DPM(DRAMC_CTX_T *p, int iTestCnt, bool *bTa2_stress_enable);
4465
4466 void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)
4467 {
4468 static int sTestCnt = 0;
4469 U8 channelIdx, channelBak;
4470 U8 rankIdx, rankBak;
4471 bool bTa2_stress_enable = TRUE;
4472 int err = 0;
4473
4474 #ifdef FAKE_ENGINE_STRESS
4475 if(u1IsLP4Family(p->dram_type))
4476 {
4477 Fake_Engine_Presetting(p, 0);
4478 }
4479 #endif
4480
4481 TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF);
4482 TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_HW);
4483 TA2_Test_Run_Time_HW_Write(p, ENABLE);
4484
4485 do {
4486 while(u1StopMiniStress){mcDELAY_MS(1000);}
4487 mcSHOW_DBG_MSG(("Stress test.................\n"));
4488
4489 #ifdef TA2_STRESS
4490 if(bTa2_stress_enable)
4491 {
4492 if(sTestCnt)
4493 {
4494 TA2_Test_Run_Time_HW_Read(p, ENABLE);
4495 }
4496 }
4497 #endif
4498
4499 #ifdef FAKE_ENGINE_STRESS
4500 if(u1IsLP4Family(p->dram_type))
4501 {
4502 static U8 trans_type = W;
4503 Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 3);
4504 }
4505 #endif
4506
4507 DFSTestProgram(p, 0);
4508
4509 #ifdef TA2_STRESS
4510 if(bTa2_stress_enable)
4511 {
4512 err |= TA2_Test_Run_Time_HW_Status(p);
4513 }
4514 #endif
4515 sTestCnt ++;
4516
4517 if (1)
4518 {
4519 MR_periodic_check(p);
4520 #ifdef COMPLEX_STRESS
4521 int s4value, num;
4522 U32 ii, addr[] = {
4523 0x40024000,
4524 0x56000000,
4525 0x80000000,
4526 };
4527 num = sizeof(addr)>>2;
4528 for(ii=0;ii<(U32)num;ii++)
4529 {
4530 s4value = dramc_complex_mem_test (addr[ii], 0x20000);
4531 mcSHOW_DBG_MSG(("complex R/W mem 0x%x test %s: %d\n",addr[ii],s4value?"fail":"pass",-s4value));
4532
4533 err |= s4value;
4534 }
4535 #endif
4536 }
4537 } while(1);
4538 return;
4539 }
4540 #endif
4541
4542