1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /*************************************************************************** 4 * copyright : (C) 2002 by Frank Mori Hess 5 ***************************************************************************/ 6 7 #ifndef _NEC7210_REGISTERS_H 8 #define _NEC7210_REGISTERS_H 9 10 enum nec7210_chipset { 11 NEC7210, // The original 12 TNT4882, // NI 13 NAT4882, // NI 14 CB7210, // measurement computing 15 IOT7210, // iotech 16 IGPIB7210, // Ines 17 TNT5004, // NI (minor differences to TNT4882) 18 }; 19 20 /* nec7210 register numbers (might need to be multiplied by 21 * a board-dependent offset to get actually io address offset) 22 */ 23 // write registers 24 enum nec7210_write_regs { 25 CDOR, // command/data out 26 IMR1, // interrupt mask 1 27 IMR2, // interrupt mask 2 28 SPMR, // serial poll mode 29 ADMR, // address mode 30 AUXMR, // auxiliary mode 31 ADR, // address 32 EOSR, // end-of-string 33 34 // nec7210 has 8 registers 35 nec7210_num_registers = 8, 36 }; 37 38 // read registers 39 enum nec7210_read_regs { 40 DIR, // data in 41 ISR1, // interrupt status 1 42 ISR2, // interrupt status 2 43 SPSR, // serial poll status 44 ADSR, // address status 45 CPTR, // command pass though 46 ADR0, // address 1 47 ADR1, // address 2 48 }; 49 50 //bit definitions common to nec-7210 compatible registers 51 52 // ISR1: interrupt status register 1 53 enum isr1_bits { 54 HR_DI = (1 << 0), 55 HR_DO = (1 << 1), 56 HR_ERR = (1 << 2), 57 HR_DEC = (1 << 3), 58 HR_END = (1 << 4), 59 HR_DET = (1 << 5), 60 HR_APT = (1 << 6), 61 HR_CPT = (1 << 7), 62 }; 63 64 // IMR1: interrupt mask register 1 65 enum imr1_bits { 66 HR_DIIE = (1 << 0), 67 HR_DOIE = (1 << 1), 68 HR_ERRIE = (1 << 2), 69 HR_DECIE = (1 << 3), 70 HR_ENDIE = (1 << 4), 71 HR_DETIE = (1 << 5), 72 HR_APTIE = (1 << 6), 73 HR_CPTIE = (1 << 7), 74 }; 75 76 // ISR2, interrupt status register 2 77 enum isr2_bits { 78 HR_ADSC = (1 << 0), 79 HR_REMC = (1 << 1), 80 HR_LOKC = (1 << 2), 81 HR_CO = (1 << 3), 82 HR_REM = (1 << 4), 83 HR_LOK = (1 << 5), 84 HR_SRQI = (1 << 6), 85 HR_INT = (1 << 7), 86 }; 87 88 // IMR2, interrupt mask register 2 89 enum imr2_bits { 90 // all the bits in this register that enable interrupts 91 IMR2_ENABLE_INTR_MASK = 0x4f, 92 HR_ACIE = (1 << 0), 93 HR_REMIE = (1 << 1), 94 HR_LOKIE = (1 << 2), 95 HR_COIE = (1 << 3), 96 HR_DMAI = (1 << 4), 97 HR_DMAO = (1 << 5), 98 HR_SRQIE = (1 << 6), 99 }; 100 101 // SPSR, serial poll status register 102 enum spsr_bits { 103 HR_PEND = (1 << 6), 104 }; 105 106 // SPMR, serial poll mode register 107 enum spmr_bits { 108 HR_RSV = (1 << 6), 109 }; 110 111 // ADSR, address status register 112 enum adsr_bits { 113 HR_MJMN = (1 << 0), 114 HR_TA = (1 << 1), 115 HR_LA = (1 << 2), 116 HR_TPAS = (1 << 3), 117 HR_LPAS = (1 << 4), 118 HR_SPMS = (1 << 5), 119 HR_NATN = (1 << 6), 120 HR_CIC = (1 << 7), 121 }; 122 123 // ADMR, address mode register 124 enum admr_bits { 125 HR_ADM0 = (1 << 0), 126 HR_ADM1 = (1 << 1), 127 HR_TRM0 = (1 << 4), 128 HR_TRM1 = (1 << 5), 129 HR_TRM_EOIOE_TRIG = 0, 130 HR_TRM_CIC_TRIG = HR_TRM0, 131 HR_TRM_CIC_EOIOE = HR_TRM1, 132 HR_TRM_CIC_PE = HR_TRM0 | HR_TRM1, 133 HR_LON = (1 << 6), 134 HR_TON = (1 << 7), 135 }; 136 137 // ADR, bits used in address0, address1 and address0/1 registers 138 enum adr_bits { 139 ADDRESS_MASK = 0x1f, /* mask to specify lower 5 bits */ 140 HR_DL = (1 << 5), 141 HR_DT = (1 << 6), 142 HR_ARS = (1 << 7), 143 }; 144 145 // ADR1, address1 register 146 enum adr1_bits { 147 HR_EOI = (1 << 7), 148 }; 149 150 // AUXMR, auxiliary mode register 151 enum auxmr_bits { 152 ICR = 0x20, 153 PPR = 0x60, 154 AUXRA = 0x80, 155 AUXRB = 0xa0, 156 AUXRE = 0xc0, 157 }; 158 159 // auxra, auxiliary register A 160 enum auxra_bits { 161 HR_HANDSHAKE_MASK = 0x3, 162 HR_HLDA = 0x1, 163 HR_HLDE = 0x2, 164 HR_LCM = 0x3, /* auxra listen continuous */ 165 HR_REOS = 0x4, 166 HR_XEOS = 0x8, 167 HR_BIN = 0x10, 168 }; 169 170 // auxrb, auxiliary register B 171 enum auxrb_bits { 172 HR_CPTE = (1 << 0), 173 HR_SPEOI = (1 << 1), 174 HR_TRI = (1 << 2), 175 HR_INV = (1 << 3), 176 HR_ISS = (1 << 4), 177 }; 178 179 enum auxre_bits { 180 HR_DAC_HLD_DCAS = 0x1, /* perform DAC holdoff on receiving clear */ 181 HR_DAC_HLD_DTAS = 0x2, /* perform DAC holdoff on receiving trigger */ 182 }; 183 184 // parallel poll register 185 enum ppr_bits { 186 HR_PPS = (1 << 3), 187 HR_PPU = (1 << 4), 188 }; 189 190 /* 7210 Auxiliary Commands */ 191 enum aux_cmds { 192 AUX_PON = 0x0, /* Immediate Execute pon */ 193 AUX_CPPF = 0x1, /* Clear Parallel Poll Flag */ 194 AUX_CR = 0x2, /* Chip Reset */ 195 AUX_FH = 0x3, /* Finish Handshake */ 196 AUX_TRIG = 0x4, /* Trigger */ 197 AUX_RTL = 0x5, /* Return to local */ 198 AUX_SEOI = 0x6, /* Send EOI */ 199 AUX_NVAL = 0x7, /* Non-Valid Secondary Command or Address */ 200 AUX_SPPF = 0x9, /* Set Parallel Poll Flag */ 201 AUX_VAL = 0xf, /* Valid Secondary Command or Address */ 202 AUX_GTS = 0x10, /* Go To Standby */ 203 AUX_TCA = 0x11, /* Take Control Asynchronously */ 204 AUX_TCS = 0x12, /* Take Control Synchronously */ 205 AUX_LTN = 0x13, /* Listen */ 206 AUX_DSC = 0x14, /* Disable System Control */ 207 AUX_CIFC = 0x16, /* Clear IFC */ 208 AUX_CREN = 0x17, /* Clear REN */ 209 AUX_TCSE = 0x1a, /* Take Control Synchronously on End */ 210 AUX_LTNC = 0x1b, /* Listen in Continuous Mode */ 211 AUX_LUN = 0x1c, /* Local Unlisten */ 212 AUX_EPP = 0x1d, /* Execute Parallel Poll */ 213 AUX_SIFC = 0x1e, /* Set IFC */ 214 AUX_SREN = 0x1f, /* Set REN */ 215 }; 216 217 #endif //_NEC7210_REGISTERS_H 218