1 /***********************************************************************************************************************
2 * Copyright [2015-2017] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
3 *
4 * This file is part of Renesas SynergyTM Software Package (SSP)
5 *
6 * The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
7 * and/or its licensors ("Renesas") and subject to statutory and contractual protections.
8 *
9 * This file is subject to a Renesas SSP license agreement. Unless otherwise agreed in an SSP license agreement with
10 * Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
11 * or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
12 * MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
13 * "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
14 * PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
15 * CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
16 * CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
17 * included in this file may be subject to different terms.
18 **********************************************************************************************************************/
19
20 /**********************************************************************************************************************
21 * File Name : hw_dataflash.c
22 * Description : Data Flash Control processing for Low Power Flash
23 **********************************************************************************************************************/
24
25 /******************************************************************************
26 * Includes <System Includes> , “Project Includes”
27 ******************************************************************************/
28 #include "bsp_api.h"
29 #include "r_flash_lp.h"
30 #include "../hw_flash_lp_private.h"
31 #include "r_flash_cfg.h"
32 #include "hw_flash_common.h"
33 #include "hw_dataflash.h"
34
35 /*******************************************************************************************************************//**
36 * @addtogroup FLASH
37 * @{
38 **********************************************************************************************************************/
39 /*******************************************************************************************************************//**
40 * @} (end FLASH)
41 **********************************************************************************************************************/
42
43 /******************************************************************************
44 * Macro definitions
45 ******************************************************************************/
46
47 /******************************************************************************
48 * Private global variables and functions
49 ******************************************************************************/
50 static current_parameters_t * gp_flash_settings = NULL;
51
52 static void HW_FLASH_LP_write_fpmcr (flash_lp_instance_ctrl_t * const p_ctrl, uint8_t value);
53
54 /*******************************************************************************************************************//**
55 * @brief Enable Data Flash Access and wait for the Data Flash STOP recovery time.
56 * @param[in] p_ctrl Pointer to the Flash control block
57 * @retval none
58 **********************************************************************************************************************/
HW_FLASH_LP_dataflash_enable(flash_lp_instance_ctrl_t * const p_ctrl)59 void HW_FLASH_LP_dataflash_enable (flash_lp_instance_ctrl_t * const p_ctrl)
60 {
61 R_FACI_Type * p_faci_reg = (R_FACI_Type *) p_ctrl->p_reg;
62 /** Data Flash Access enable */
63 p_faci_reg->DFLCTL = 1U;
64
65 if (1U == p_faci_reg->DFLCTL)
66 {
67 __NOP();
68 }
69
70 /** Wait for 5us over (tDSTOP) */
71 HW_FLASH_LP_delay_us(WAIT_TDSTOP, gp_flash_settings->system_clock_freq);
72
73 }
74
75 /*******************************************************************************************************************//**
76 * @brief Transition to Data Flash P/E mode.
77 * @param[in] p_ctrl Pointer to the Flash control block
78 * @retval none
79 **********************************************************************************************************************/
HW_FLASH_LP_dataflash_enter_pe_mode(flash_lp_instance_ctrl_t * const p_ctrl)80 void HW_FLASH_LP_dataflash_enter_pe_mode (flash_lp_instance_ctrl_t * const p_ctrl)
81 {
82 R_FACI_Type * p_faci_reg = (R_FACI_Type *) p_ctrl->p_reg;
83
84 p_faci_reg->FENTRYR = FENTRYR_DATAFLASH_PE_MODE;
85
86 /** If BGO mode is enabled for dataflash and the vector is valid enable the vector. */
87 if (gp_flash_settings->bgo_enabled_df == true)
88 {
89 if (SSP_INVALID_VECTOR != p_ctrl->irq)
90 {
91 NVIC_EnableIRQ(p_ctrl->irq); // We are supporting Flash Rdy interrupts for Data Flash operations
92 }
93 }
94
95 HW_FLASH_LP_delay_us(WAIT_TDSTOP, gp_flash_settings->system_clock_freq);
96
97 if (R_SYSTEM->OPCCR_b.OPCM == 0U) ///< High speed mode?
98 {
99 HW_FLASH_LP_write_fpmcr(p_ctrl, DATAFLASH_PE_MODE);
100 }
101 else
102 {
103 HW_FLASH_LP_write_fpmcr(p_ctrl, (uint8_t)DATAFLASH_PE_MODE | (uint8_t)LVPE_MODE);
104 }
105
106 p_faci_reg->FISR_b.PCKA = (gp_flash_settings->flash_clock_freq - 1U) & (uint32_t)0x1F;
107 }
108
109 /*******************************************************************************************************************//**
110 * @brief This function switches the peripheral from P/E mode for Data Flash to Read mode.
111 * @param[in] p_ctrl Pointer to the Flash control block
112 * @retval SSP_SUCCESS Successfully entered read mode.
113 * @retval SSP_ERR_TIMEOUT Timed out waiting for confirmation of transition to read mode
114 *
115 **********************************************************************************************************************/
HW_FLASH_LP_dataflash_enter_read_mode(flash_lp_instance_ctrl_t * const p_ctrl)116 ssp_err_t HW_FLASH_LP_dataflash_enter_read_mode (flash_lp_instance_ctrl_t * const p_ctrl)
117 {
118 ssp_err_t err = SSP_SUCCESS;
119 R_FACI_Type * p_faci_reg = (R_FACI_Type *) p_ctrl->p_reg;
120
121 /* Timeout counter. */
122 volatile uint32_t wait_cnt = FLASH_FRDY_CMD_TIMEOUT;
123
124 /** Set the Flash P/E Mode Control Register to Read mode. */
125 HW_FLASH_LP_write_fpmcr(p_ctrl, READ_MODE);
126
127 /** Wait for 5us over (tMS) */
128 HW_FLASH_LP_delay_us(WAIT_TMS_HIGH, gp_flash_settings->system_clock_freq);
129
130 /** Clear the flash P/E mode entry register */
131 p_faci_reg->FENTRYR = FENTRYR_READ_MODE;
132
133 /** Loop until the Flash P/E mode entry register is cleared or a timeout occurs. If timeout occurs return error. */
134 while (0x0000U != p_faci_reg->FENTRYR)
135 {
136 /* Confirm that the written value can be read correctly. */
137 if (wait_cnt <= (uint32_t)0)
138 {
139 /* return timeout status*/
140 return SSP_ERR_TIMEOUT;
141 }
142 wait_cnt--;
143 }
144
145 return err;
146 }
147
148 /*******************************************************************************************************************//**
149 * @brief Initiates a Write sequence to the Low Power Data Flash data. Address validation has already been
150 * performed by the caller.
151 * @param[in] p_ctrl Pointer to the Flash control block
152 * @param[in] src_start_address Start address of the (RAM) area which stores the programming data.
153 * @param[in] dest_start_address Flash Start address which will be written.
154 * @param[in] num_bytes Number of bytes to write.
155 * @param[in] min_program_size The minimum Flash programming size.
156 * @retval none.
157 **********************************************************************************************************************/
HW_FLASH_LP_dataflash_write(flash_lp_instance_ctrl_t * const p_ctrl,uint32_t const src_start_address,uint32_t dest_start_address,uint32_t num_bytes,uint32_t min_program_size)158 void HW_FLASH_LP_dataflash_write (flash_lp_instance_ctrl_t * const p_ctrl, uint32_t const src_start_address,
159 uint32_t dest_start_address,
160 uint32_t num_bytes,
161 uint32_t min_program_size)
162 {
163 R_FACI_Type * p_faci_reg = (R_FACI_Type *) p_ctrl->p_reg;
164 uint32_t temp = min_program_size;
165 uint32_t right_shift = 0U;
166 while (1U != temp)
167 {
168 temp >>= 1;
169 right_shift++;
170 }
171 /** Calculate the number of writes. Each write is of length min_program_size. */
172 /** Configure the flash settings. */
173 /* This is done with right shift instead of division to avoid using the division library, which would be in flash
174 * and cause a jump from RAM to flash. */
175 gp_flash_settings->total_count = num_bytes >> right_shift; /* Number of bytes to write */
176 gp_flash_settings->dest_addr = dest_start_address;
177 gp_flash_settings->src_addr = src_start_address;
178 gp_flash_settings->current_count = (uint32_t)0;
179
180 p_faci_reg->FASR_b.EXS = 0U;
181
182 /** Initiate the data flash write operation. */
183 HW_FLASH_LP_dataflash_write_operation(p_ctrl, src_start_address, dest_start_address);
184 }
185
186 /*******************************************************************************************************************//**
187 * @brief Execute a single Write operation on the Low Power Data Flash data.
188 * @param[in] p_ctrl Pointer to the Flash control block
189 * @param[in] psrc_addr Source address for data to be written.
190 * @param[in] dest_addr End address (read form) for writing.
191 * @retval none.
192 **********************************************************************************************************************/
HW_FLASH_LP_dataflash_write_operation(flash_lp_instance_ctrl_t * const p_ctrl,const uint32_t psrc_addr,uint32_t dest_addr)193 void HW_FLASH_LP_dataflash_write_operation (flash_lp_instance_ctrl_t * const p_ctrl, const uint32_t psrc_addr, uint32_t dest_addr)
194 {
195 uint32_t dest_addr_idx;
196 uint8_t * data8_ptr;
197 R_FACI_Type * p_faci_reg = (R_FACI_Type *) p_ctrl->p_reg;
198 data8_ptr = (uint8_t *)psrc_addr;
199
200 dest_addr_idx = dest_addr + DATAFLASH_ADDR_OFFSET; /* Conversion to the P/E address from the read address */
201
202 /** Write flash address setting */
203 p_faci_reg->FSARH = (uint16_t) ((uint32_t)(dest_addr_idx >> 16) & 0xFFFF);
204 p_faci_reg->FSARL = (uint16_t) (dest_addr_idx & 0xFFFF);
205
206 /** Write data address setting */
207 p_faci_reg->FWBL0 = *data8_ptr; // For data flash there are only 8 bits used of the 16 in the reg
208
209 /** Execute Write command */
210 p_faci_reg->FCR = FCR_WRITE;
211 }
212
213 /*******************************************************************************************************************//**
214 * @brief Waits for the write command to be completed and verifies the result of the command execution.
215 * @param[in] p_ctrl Pointer to the Flash control block
216 * @param[in] min_program_size The minimum Flash programming size.
217 * @retval SSP_SUCCESS Write command successfully completed.
218 * @retval SSP_ERR_IN_USE Write command still in progress.
219 * @retval SSP_ERR_TIMEOUT Timed out waiting for write command completion.
220 * @retval SSP_ERR_WRITE_FAILED Write failed. Flash could be locked, area has not been erased, or address
221 * could be under access window control.
222 **********************************************************************************************************************/
HW_FLASH_LP_dataflash_write_monitor(flash_lp_instance_ctrl_t * const p_ctrl,uint32_t min_program_size)223 ssp_err_t HW_FLASH_LP_dataflash_write_monitor (flash_lp_instance_ctrl_t * const p_ctrl, uint32_t min_program_size)
224 {
225 ssp_err_t status;
226 R_FACI_Type * p_faci_reg = (R_FACI_Type *) p_ctrl->p_reg;
227
228
229 /** If the flash has not completed the software command return error. */
230 if (1U != p_faci_reg->FSTATR1_b.FRDY)
231 {
232 return SSP_ERR_IN_USE;
233 }
234
235 /** Clear the Flash Control Register */
236 p_faci_reg->FCR = FCR_CLEAR;
237
238 /** Prepare worst case timeout counter */
239 gp_flash_settings->wait_cnt = gp_flash_settings->wait_max_write_df;
240
241 while (0U != p_faci_reg->FSTATR1_b.FRDY)
242 {
243 /** Check that execute command is completed. */
244 /** Wait until FRDY is 1 unless timeout occurs. If timeout return error. */
245 if (gp_flash_settings->wait_cnt <= (uint32_t)0)
246 {
247 /* if FRDY is not set to 0 after max timeout, return error*/
248 return SSP_ERR_TIMEOUT;
249 }
250 gp_flash_settings->wait_cnt--;
251 }
252
253 /** If illegal command or programming error reset and return error. */
254 if ((0U != p_faci_reg->FSTATR2_b.ILGLERR) || (0U != p_faci_reg->FSTATR2_b.PRGERR1))
255 {
256 HW_FLASH_LP_reset(p_ctrl);
257 status = SSP_ERR_WRITE_FAILED;
258 }
259 else
260 {
261 /** If there are more blocks to write initiate another write operation. If failure return error. */
262 gp_flash_settings->src_addr += min_program_size;
263 gp_flash_settings->dest_addr += min_program_size;
264 gp_flash_settings->total_count--;
265
266 if (gp_flash_settings->total_count)
267 {
268 HW_FLASH_LP_dataflash_write_operation(p_ctrl, gp_flash_settings->src_addr, gp_flash_settings->dest_addr);
269 status = SSP_ERR_IN_USE;
270 }
271 else
272 {
273 status = SSP_SUCCESS;
274 }
275 }
276
277 /** Return status */
278 return status;
279 }
280
281 /*******************************************************************************************************************//**
282 * @brief Initiates the Erase sequence to Erase the # of Data Flash blocks specified by num_blocks, starting with the
283 * Block containing 'address'.
284 * @param[in] p_ctrl Pointer to the Flash control block
285 * @param[in] start_addr - The block containing this address is the first block to be erased.
286 * @param[in] num_blocks - The # of blocks to be erased.
287 * @param[in] block_size - The block size for this Flash block.
288 * @retval None.
289 **********************************************************************************************************************/
HW_FLASH_LP_dataflash_erase(flash_lp_instance_ctrl_t * const p_ctrl,uint32_t start_addr,uint32_t num_blocks,uint32_t block_size)290 void HW_FLASH_LP_dataflash_erase (flash_lp_instance_ctrl_t * const p_ctrl, uint32_t start_addr, uint32_t num_blocks, uint32_t block_size)
291 {
292 R_FACI_Type * p_faci_reg = (R_FACI_Type *) p_ctrl->p_reg;
293
294 /** Save the current operation parameters. */
295 gp_flash_settings->dest_addr = start_addr;
296 gp_flash_settings->total_count = num_blocks;
297 gp_flash_settings->wait_cnt = gp_flash_settings->wait_max_erase_df_block;
298 gp_flash_settings->current_count = 1U; // Include the one we are doing right here
299
300 p_faci_reg->FASR_b.EXS = 0U;
301
302 /** Call the data flash erase operation. */
303 HW_FLASH_LP_dataflash_erase_operation(p_ctrl, gp_flash_settings->dest_addr, block_size);
304 }
305
306 /*******************************************************************************************************************//**
307 * @brief Execute a single Erase operation on the Low Power Data Flash data.
308 * @param[in] p_ctrl Pointer to the Flash control block
309 * @param[in] start_addr Starting Code Flash address to erase.
310 * @param[in] block_size - The block size for this Flash block.
311 * @retval none.
312 **********************************************************************************************************************/
HW_FLASH_LP_dataflash_erase_operation(flash_lp_instance_ctrl_t * const p_ctrl,const uint32_t start_addr,uint32_t block_size)313 void HW_FLASH_LP_dataflash_erase_operation (flash_lp_instance_ctrl_t * const p_ctrl, const uint32_t start_addr, uint32_t block_size)
314 {
315 R_FACI_Type * p_faci_reg = (R_FACI_Type *) p_ctrl->p_reg;
316
317 uint32_t block_start_addr;
318 uint32_t block_end_addr;
319
320 block_start_addr = start_addr + (uint32_t)DATAFLASH_ADDR_OFFSET; /* Conversion to the P/E address from the read address */
321 block_end_addr = (block_start_addr + (block_size - 1U));
322
323 /** Set the erase start address. */
324 p_faci_reg->FSARH = (uint16_t) ((block_start_addr >> 16) & 0xFFFFU);
325 p_faci_reg->FSARL = (uint16_t) (block_start_addr & 0xFFFFU);
326
327 /** Set the erase end address. */
328 p_faci_reg->FEARH = ((block_end_addr >> 16) & 0xFFFFU);
329 p_faci_reg->FEARL = (uint16_t) (block_end_addr & 0xFFFFU);
330
331 /** Execute the erase command. */
332 p_faci_reg->FCR = FCR_ERASE;
333 }
334
335 /*******************************************************************************************************************//**
336 * @brief Waits for the erase command to be completed and verifies the result of the command execution.
337 * @param[in] p_ctrl Pointer to the Flash control block
338 * @param[in] block_size - The block size for this Flash block.
339 * @retval SSP_SUCCESS Erase command successfully completed.
340 * @retval SSP_ERR_IN_USE Erase command still in progress.
341 * @retval SSP_ERR_TIMEOUT Timed out waiting for erase command completion.
342 * @retval SSP_ERR_WRITE_FAILED Erase failed. Flash could be locked or address could be under access window
343 * control.
344 **********************************************************************************************************************/
HW_FLASH_LP_dataflash_erase_monitor(flash_lp_instance_ctrl_t * const p_ctrl,uint32_t block_size)345 ssp_err_t HW_FLASH_LP_dataflash_erase_monitor (flash_lp_instance_ctrl_t * const p_ctrl, uint32_t block_size)
346 {
347 ssp_err_t status;
348 R_FACI_Type * p_faci_reg = (R_FACI_Type *) p_ctrl->p_reg;
349
350 /** If the flash has not completed the software command return error. */
351 if (1U != p_faci_reg->FSTATR1_b.FRDY)
352 {
353 return SSP_ERR_IN_USE;
354 }
355
356 /** Clear Flash Control Register. */
357 p_faci_reg->FCR = FCR_CLEAR;
358
359 /** Prepare worst case timeout counter */
360 gp_flash_settings->wait_cnt = gp_flash_settings->wait_max_erase_df_block;
361
362 /** Wait until the ready flag is set or timeout. If timeout return error */
363 while (0U != p_faci_reg->FSTATR1_b.FRDY)
364 {
365 /* Check that execute command is completed. */
366 /* Wait until FRDY is 1 unless timeout occurs. If timeout return error. */
367 if (gp_flash_settings->wait_cnt <= (uint32_t)0)
368 {
369 /* if FRDY is not set to 0 after max timeout, return error*/
370 return SSP_ERR_TIMEOUT;
371 }
372 gp_flash_settings->wait_cnt--;
373 }
374
375 /** If invalid command or erase error flag is set reset and return error. */
376 if ((0U != p_faci_reg->FSTATR2_b.ILGLERR) || (0U != p_faci_reg->FSTATR2_b.ERERR))
377 {
378 HW_FLASH_LP_reset(p_ctrl);
379 status = SSP_ERR_WRITE_FAILED;
380 }
381 else
382 {
383 /** If there are more blocks to erase initiate another erase operation. Otherwise return success. */
384 gp_flash_settings->dest_addr += block_size;
385
386 if (gp_flash_settings->current_count < gp_flash_settings->total_count)
387 {
388 HW_FLASH_LP_dataflash_erase_operation(p_ctrl, gp_flash_settings->dest_addr, block_size);
389 status = SSP_ERR_IN_USE;
390 }
391 else
392 {
393 status = SSP_SUCCESS;
394 }
395 gp_flash_settings->current_count++;
396 }
397
398 return status;
399 }
400
401 /*******************************************************************************************************************//**
402 * @brief Initiates a Blank check sequence to the Low Power Data Flash data. Address validation has already been
403 * performed by the caller.
404 * @param[in] p_ctrl Pointer to the Flash control block
405 * @param[in] start_addr Start address of the Data Flash area to blank check.
406 * @param[in] end_addr End address of the Data flash area to blank check This address is included in the blank
407 * check.
408 * @retval none.
409 **********************************************************************************************************************/
HW_FLASH_LP_dataflash_blank_check(flash_lp_instance_ctrl_t * const p_ctrl,uint32_t start_addr,uint32_t end_addr)410 void HW_FLASH_LP_dataflash_blank_check (flash_lp_instance_ctrl_t * const p_ctrl, uint32_t start_addr, uint32_t end_addr)
411 {
412 R_FACI_Type * p_faci_reg = (R_FACI_Type *) p_ctrl->p_reg;
413 uint32_t start_addr_idx;
414 uint32_t end_addr_idx;
415
416 start_addr_idx = start_addr + DATAFLASH_ADDR_OFFSET; /* Conversion to the P/E address from the read address */
417 end_addr_idx = end_addr + DATAFLASH_ADDR_OFFSET; /* Conversion to the P/E address from the read address */
418
419 p_faci_reg->FASR_b.EXS = 0U;
420
421 /** BlankCheck start address setting */
422 p_faci_reg->FSARH = (uint16_t) ((start_addr_idx >> 16) & 0xFFFFU);
423 p_faci_reg->FSARL = (uint16_t) (start_addr_idx & 0xFFFFU);
424
425 /** BlankCheck end address setting */
426 p_faci_reg->FEARH = ((end_addr_idx >> 16) & 0xFFFFU);
427 p_faci_reg->FEARL = (uint16_t) (end_addr_idx & 0xFFFFU);
428
429 /** Execute BlankCheck command */
430 p_faci_reg->FCR = FCR_BLANKCHECK;
431 }
432
433 /*******************************************************************************************************************//**
434 * @brief Waits for the blank check command to be completed and verifies the result of the command execution.
435 * @param[in] p_ctrl Pointer to the Flash control block
436 * @retval SSP_SUCCESS Blank check command successfully completed.
437 * @retval SSP_ERR_IN_USE Blank check command still in progress.
438 * @retval SSP_ERR_TIMEOUT Timed out waiting for Blank check command completion.
439 **********************************************************************************************************************/
HW_FLASH_LP_dataflash_blank_check_monitor(flash_lp_instance_ctrl_t * const p_ctrl)440 ssp_err_t HW_FLASH_LP_dataflash_blank_check_monitor (flash_lp_instance_ctrl_t * const p_ctrl)
441 {
442 ssp_err_t err = SSP_SUCCESS;
443 R_FACI_Type * p_faci_reg = (R_FACI_Type *) p_ctrl->p_reg;
444
445 /** If the flash has not completed the software command return error. */
446 if (1U != p_faci_reg->FSTATR1_b.FRDY)
447 {
448 return SSP_ERR_IN_USE;
449 }
450
451 /** Clear the Flash Control Register */
452 p_faci_reg->FCR = FCR_CLEAR;
453
454 /** Prepare worst case timeout counter */
455 gp_flash_settings->wait_cnt = gp_flash_settings->wait_max_blank_check;
456
457 while (0U != p_faci_reg->FSTATR1_b.FRDY)
458 {
459 /** Check that execute command is completed. */
460 /** Wait until FRDY is 1 unless timeout occurs. If timeout return error. */
461 if (gp_flash_settings->wait_cnt <= (uint32_t)0)
462 {
463 /* if FRDY is not set to 0 after max timeout, return error*/
464 return SSP_ERR_TIMEOUT;
465 }
466 gp_flash_settings->wait_cnt--;
467 }
468
469 /** If illegal command reset and return error. */
470 if (0U != p_faci_reg->FSTATR2_b.ILGLERR)
471 {
472 HW_FLASH_LP_reset(p_ctrl);
473 err = SSP_ERR_WRITE_FAILED;
474 }
475
476 /** Return status. */
477 return err;
478 }
479
480 /*******************************************************************************************************************//**
481 * @brief Sets the FPMCR register, used to place the Flash sequencer in Data Flash P/E mode.
482 * @param[in] p_ctrl Pointer to the Flash control block
483 * @param[in] value - 8 bit value to be written to the FPMCR register.
484 * @retval none.
485 **********************************************************************************************************************/
HW_FLASH_LP_write_fpmcr(flash_lp_instance_ctrl_t * const p_ctrl,uint8_t value)486 static void HW_FLASH_LP_write_fpmcr (flash_lp_instance_ctrl_t * const p_ctrl, uint8_t value)
487 {
488 R_FACI_Type * p_faci_reg = (R_FACI_Type *) p_ctrl->p_reg;
489
490 p_faci_reg->FPR = 0xA5U;
491
492 p_faci_reg->FPMCR = value;
493 p_faci_reg->FPMCR = (uint8_t) ~value;
494 p_faci_reg->FPMCR = value;
495
496 if (value == p_faci_reg->FPMCR)
497 {
498 __NOP();
499 }
500 }
501
502 /*******************************************************************************
503 * Outline : Give the Data Flash HW layer access to the flash settings
504 * Header : none
505 * Function Name: set_flash_settings
506 * Description : Give the Data Flash HW layer access to the flash settings
507 * Arguments : current_parameters_t *p_current_parameters - Pointer the settings.
508 * :
509 * Return Value : none
510 *******************************************************************************/
HW_FLASH_LP_data_flash_set_flash_settings(current_parameters_t * const p_current_parameters)511 void HW_FLASH_LP_data_flash_set_flash_settings (current_parameters_t * const p_current_parameters)
512 {
513 gp_flash_settings = p_current_parameters;
514 }
515