1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7
8 #include <linux/firmware.h>
9 #include <linux/slab.h>
10 #include <drv_types.h>
11 #include <rtl8723b_hal.h>
12 #include "hal_com_h2c.h"
13
_FWDownloadEnable(struct adapter * padapter,bool enable)14 static void _FWDownloadEnable(struct adapter *padapter, bool enable)
15 {
16 u8 tmp, count = 0;
17
18 if (enable) {
19 /* 8051 enable */
20 tmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
21 rtw_write8(padapter, REG_SYS_FUNC_EN+1, tmp|0x04);
22
23 tmp = rtw_read8(padapter, REG_MCUFWDL);
24 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01);
25
26 do {
27 tmp = rtw_read8(padapter, REG_MCUFWDL);
28 if (tmp & 0x01)
29 break;
30 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01);
31 msleep(1);
32 } while (count++ < 100);
33
34 /* 8051 reset */
35 tmp = rtw_read8(padapter, REG_MCUFWDL+2);
36 rtw_write8(padapter, REG_MCUFWDL+2, tmp&0xf7);
37 } else {
38 /* MCU firmware download disable. */
39 tmp = rtw_read8(padapter, REG_MCUFWDL);
40 rtw_write8(padapter, REG_MCUFWDL, tmp&0xfe);
41 }
42 }
43
_BlockWrite(struct adapter * padapter,void * buffer,u32 buffSize)44 static int _BlockWrite(struct adapter *padapter, void *buffer, u32 buffSize)
45 {
46 int ret = _SUCCESS;
47
48 u32 blockSize_p1 = 4; /* (Default) Phase #1 : PCI muse use 4-byte write to download FW */
49 u32 blockSize_p2 = 8; /* Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */
50 u32 blockSize_p3 = 1; /* Phase #3 : Use 1-byte, the remnant of FW image. */
51 u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;
52 u32 remainSize_p1 = 0, remainSize_p2 = 0;
53 u8 *bufferPtr = buffer;
54 u32 i = 0, offset = 0;
55
56 /* 3 Phase #1 */
57 blockCount_p1 = buffSize / blockSize_p1;
58 remainSize_p1 = buffSize % blockSize_p1;
59
60 for (i = 0; i < blockCount_p1; i++) {
61 ret = rtw_write32(padapter, (FW_8723B_START_ADDRESS + i * blockSize_p1), *((u32 *)(bufferPtr + i * blockSize_p1)));
62 if (ret == _FAIL) {
63 netdev_dbg(padapter->pnetdev, "write failed at %s %d, block:%d\n",
64 __func__, __LINE__, i);
65 goto exit;
66 }
67 }
68
69 /* 3 Phase #2 */
70 if (remainSize_p1) {
71 offset = blockCount_p1 * blockSize_p1;
72
73 blockCount_p2 = remainSize_p1/blockSize_p2;
74 remainSize_p2 = remainSize_p1%blockSize_p2;
75 }
76
77 /* 3 Phase #3 */
78 if (remainSize_p2) {
79 offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2);
80
81 blockCount_p3 = remainSize_p2 / blockSize_p3;
82
83 for (i = 0; i < blockCount_p3; i++) {
84 ret = rtw_write8(padapter, (FW_8723B_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
85
86 if (ret == _FAIL) {
87 netdev_dbg(padapter->pnetdev, "write failed at %s %d, block:%d\n",
88 __func__, __LINE__, i);
89 goto exit;
90 }
91 }
92 }
93 exit:
94 return ret;
95 }
96
_PageWrite(struct adapter * padapter,u32 page,void * buffer,u32 size)97 static int _PageWrite(
98 struct adapter *padapter,
99 u32 page,
100 void *buffer,
101 u32 size
102 )
103 {
104 u8 value8;
105 u8 u8Page = (u8) (page & 0x07);
106
107 value8 = (rtw_read8(padapter, REG_MCUFWDL+2) & 0xF8) | u8Page;
108 rtw_write8(padapter, REG_MCUFWDL+2, value8);
109
110 return _BlockWrite(padapter, buffer, size);
111 }
112
_WriteFW(struct adapter * padapter,void * buffer,u32 size)113 static int _WriteFW(struct adapter *padapter, void *buffer, u32 size)
114 {
115 /* Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */
116 /* We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */
117 int ret = _SUCCESS;
118 u32 pageNums, remainSize;
119 u32 page, offset;
120 u8 *bufferPtr = buffer;
121
122 pageNums = size / MAX_DLFW_PAGE_SIZE;
123 remainSize = size % MAX_DLFW_PAGE_SIZE;
124
125 for (page = 0; page < pageNums; page++) {
126 offset = page * MAX_DLFW_PAGE_SIZE;
127 ret = _PageWrite(padapter, page, bufferPtr+offset, MAX_DLFW_PAGE_SIZE);
128
129 if (ret == _FAIL) {
130 netdev_dbg(padapter->pnetdev, "page write failed at %s %d\n",
131 __func__, __LINE__);
132 goto exit;
133 }
134 }
135
136 if (remainSize) {
137 offset = pageNums * MAX_DLFW_PAGE_SIZE;
138 page = pageNums;
139 ret = _PageWrite(padapter, page, bufferPtr+offset, remainSize);
140
141 if (ret == _FAIL) {
142 netdev_dbg(padapter->pnetdev, "remaining page write failed at %s %d\n",
143 __func__, __LINE__);
144 goto exit;
145 }
146 }
147
148 exit:
149 return ret;
150 }
151
_8051Reset8723(struct adapter * padapter)152 void _8051Reset8723(struct adapter *padapter)
153 {
154 u8 cpu_rst;
155 u8 io_rst;
156
157
158 /* Reset 8051(WLMCU) IO wrapper */
159 /* 0x1c[8] = 0 */
160 /* Suggested by Isaac@SD1 and Gimmy@SD1, coding by Lucas@20130624 */
161 io_rst = rtw_read8(padapter, REG_RSV_CTRL+1);
162 io_rst &= ~BIT(0);
163 rtw_write8(padapter, REG_RSV_CTRL+1, io_rst);
164
165 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
166 cpu_rst &= ~BIT(2);
167 rtw_write8(padapter, REG_SYS_FUNC_EN+1, cpu_rst);
168
169 /* Enable 8051 IO wrapper */
170 /* 0x1c[8] = 1 */
171 io_rst = rtw_read8(padapter, REG_RSV_CTRL+1);
172 io_rst |= BIT(0);
173 rtw_write8(padapter, REG_RSV_CTRL+1, io_rst);
174
175 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
176 cpu_rst |= BIT(2);
177 rtw_write8(padapter, REG_SYS_FUNC_EN+1, cpu_rst);
178 }
179
180 u8 g_fwdl_chksum_fail;
181
polling_fwdl_chksum(struct adapter * adapter,u32 min_cnt,u32 timeout_ms)182 static s32 polling_fwdl_chksum(
183 struct adapter *adapter, u32 min_cnt, u32 timeout_ms
184 )
185 {
186 s32 ret = _FAIL;
187 u32 value32;
188 unsigned long start = jiffies;
189 u32 cnt = 0;
190
191 /* polling CheckSum report */
192 do {
193 cnt++;
194 value32 = rtw_read32(adapter, REG_MCUFWDL);
195 if (value32 & FWDL_ChkSum_rpt || adapter->bSurpriseRemoved || adapter->bDriverStopped)
196 break;
197 yield();
198 } while (jiffies_to_msecs(jiffies-start) < timeout_ms || cnt < min_cnt);
199
200 if (!(value32 & FWDL_ChkSum_rpt)) {
201 goto exit;
202 }
203
204 if (g_fwdl_chksum_fail) {
205 g_fwdl_chksum_fail--;
206 goto exit;
207 }
208
209 ret = _SUCCESS;
210
211 exit:
212
213 return ret;
214 }
215
216 u8 g_fwdl_wintint_rdy_fail;
217
_FWFreeToGo(struct adapter * adapter,u32 min_cnt,u32 timeout_ms)218 static s32 _FWFreeToGo(struct adapter *adapter, u32 min_cnt, u32 timeout_ms)
219 {
220 s32 ret = _FAIL;
221 u32 value32;
222 unsigned long start = jiffies;
223 u32 cnt = 0;
224
225 value32 = rtw_read32(adapter, REG_MCUFWDL);
226 value32 |= MCUFWDL_RDY;
227 value32 &= ~WINTINI_RDY;
228 rtw_write32(adapter, REG_MCUFWDL, value32);
229
230 _8051Reset8723(adapter);
231
232 /* polling for FW ready */
233 do {
234 cnt++;
235 value32 = rtw_read32(adapter, REG_MCUFWDL);
236 if (value32 & WINTINI_RDY || adapter->bSurpriseRemoved || adapter->bDriverStopped)
237 break;
238 yield();
239 } while (jiffies_to_msecs(jiffies - start) < timeout_ms || cnt < min_cnt);
240
241 if (!(value32 & WINTINI_RDY)) {
242 goto exit;
243 }
244
245 if (g_fwdl_wintint_rdy_fail) {
246 g_fwdl_wintint_rdy_fail--;
247 goto exit;
248 }
249
250 ret = _SUCCESS;
251
252 exit:
253
254 return ret;
255 }
256
257 #define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
258
rtl8723b_FirmwareSelfReset(struct adapter * padapter)259 void rtl8723b_FirmwareSelfReset(struct adapter *padapter)
260 {
261 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
262 u8 u1bTmp;
263 u8 Delay = 100;
264
265 if (
266 !(IS_FW_81xxC(padapter) && ((pHalData->FirmwareVersion < 0x21) || (pHalData->FirmwareVersion == 0x21 && pHalData->FirmwareSubVersion < 0x01)))
267 ) { /* after 88C Fw v33.1 */
268 /* 0x1cf = 0x20. Inform 8051 to reset. 2009.12.25. tynli_test */
269 rtw_write8(padapter, REG_HMETFR+3, 0x20);
270
271 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
272 while (u1bTmp & BIT2) {
273 Delay--;
274 if (Delay == 0)
275 break;
276 udelay(50);
277 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
278 }
279
280 if (Delay == 0) {
281 /* force firmware reset */
282 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
283 rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2));
284 }
285 }
286 }
287
288 /* */
289 /* Description: */
290 /* Download 8192C firmware code. */
291 /* */
292 /* */
rtl8723b_FirmwareDownload(struct adapter * padapter,bool bUsedWoWLANFw)293 s32 rtl8723b_FirmwareDownload(struct adapter *padapter, bool bUsedWoWLANFw)
294 {
295 s32 rtStatus = _SUCCESS;
296 u8 write_fw = 0;
297 unsigned long fwdl_start_time;
298 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
299 struct rt_firmware *pFirmware;
300 struct rt_firmware *pBTFirmware;
301 struct rt_firmware_hdr *pFwHdr = NULL;
302 u8 *pFirmwareBuf;
303 u32 FirmwareLen;
304 const struct firmware *fw;
305 struct device *device = dvobj_to_dev(padapter->dvobj);
306 u8 *fwfilepath;
307 struct dvobj_priv *psdpriv = padapter->dvobj;
308 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
309 u8 tmp_ps;
310
311 pFirmware = kzalloc(sizeof(struct rt_firmware), GFP_KERNEL);
312 if (!pFirmware)
313 return _FAIL;
314 pBTFirmware = kzalloc(sizeof(struct rt_firmware), GFP_KERNEL);
315 if (!pBTFirmware) {
316 kfree(pFirmware);
317 return _FAIL;
318 }
319 tmp_ps = rtw_read8(padapter, 0xa3);
320 tmp_ps &= 0xf8;
321 tmp_ps |= 0x02;
322 /* 1. write 0xA3[:2:0] = 3b'010 */
323 rtw_write8(padapter, 0xa3, tmp_ps);
324 /* 2. read power_state = 0xA0[1:0] */
325 tmp_ps = rtw_read8(padapter, 0xa0);
326 tmp_ps &= 0x03;
327 if (tmp_ps != 0x01)
328 pdbgpriv->dbg_downloadfw_pwr_state_cnt++;
329
330 fwfilepath = "rtlwifi/rtl8723bs_nic.bin";
331
332 pr_info("rtl8723bs: acquire FW from file:%s\n", fwfilepath);
333
334 rtStatus = request_firmware(&fw, fwfilepath, device);
335 if (rtStatus) {
336 pr_err("Request firmware failed with error 0x%x\n", rtStatus);
337 rtStatus = _FAIL;
338 goto exit;
339 }
340
341 if (!fw) {
342 pr_err("Firmware %s not available\n", fwfilepath);
343 rtStatus = _FAIL;
344 goto exit;
345 }
346
347 if (fw->size > FW_8723B_SIZE) {
348 rtStatus = _FAIL;
349 goto exit;
350 }
351
352 pFirmware->fw_buffer_sz = kmemdup(fw->data, fw->size, GFP_KERNEL);
353 if (!pFirmware->fw_buffer_sz) {
354 rtStatus = _FAIL;
355 goto exit;
356 }
357
358 pFirmware->fw_length = fw->size;
359 release_firmware(fw);
360 if (pFirmware->fw_length > FW_8723B_SIZE) {
361 rtStatus = _FAIL;
362 netdev_emerg(padapter->pnetdev,
363 "Firmware size:%u exceed %u\n",
364 pFirmware->fw_length, FW_8723B_SIZE);
365 goto release_fw1;
366 }
367
368 pFirmwareBuf = pFirmware->fw_buffer_sz;
369 FirmwareLen = pFirmware->fw_length;
370
371 /* To Check Fw header. Added by tynli. 2009.12.04. */
372 pFwHdr = (struct rt_firmware_hdr *)pFirmwareBuf;
373
374 pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->version);
375 pHalData->FirmwareSubVersion = le16_to_cpu(pFwHdr->subversion);
376 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->signature);
377
378 if (IS_FW_HEADER_EXIST_8723B(pFwHdr)) {
379 /* Shift 32 bytes for FW header */
380 pFirmwareBuf = pFirmwareBuf + 32;
381 FirmwareLen = FirmwareLen - 32;
382 }
383
384 /* Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself, */
385 /* or it will cause download Fw fail. 2010.02.01. by tynli. */
386 if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) { /* 8051 RAM code */
387 rtw_write8(padapter, REG_MCUFWDL, 0x00);
388 rtl8723b_FirmwareSelfReset(padapter);
389 }
390
391 _FWDownloadEnable(padapter, true);
392 fwdl_start_time = jiffies;
393 while (
394 !padapter->bDriverStopped &&
395 !padapter->bSurpriseRemoved &&
396 (write_fw++ < 3 || jiffies_to_msecs(jiffies - fwdl_start_time) < 500)
397 ) {
398 /* reset FWDL chksum */
399 rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL)|FWDL_ChkSum_rpt);
400
401 rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen);
402 if (rtStatus != _SUCCESS)
403 continue;
404
405 rtStatus = polling_fwdl_chksum(padapter, 5, 50);
406 if (rtStatus == _SUCCESS)
407 break;
408 }
409 _FWDownloadEnable(padapter, false);
410 if (_SUCCESS != rtStatus)
411 goto fwdl_stat;
412
413 rtStatus = _FWFreeToGo(padapter, 10, 200);
414 if (_SUCCESS != rtStatus)
415 goto fwdl_stat;
416
417 fwdl_stat:
418
419 exit:
420 kfree(pFirmware->fw_buffer_sz);
421 kfree(pFirmware);
422 release_fw1:
423 kfree(pBTFirmware);
424 return rtStatus;
425 }
426
rtl8723b_InitializeFirmwareVars(struct adapter * padapter)427 void rtl8723b_InitializeFirmwareVars(struct adapter *padapter)
428 {
429 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
430
431 /* Init Fw LPS related. */
432 adapter_to_pwrctl(padapter)->fw_current_in_ps_mode = false;
433
434 /* Init H2C cmd. */
435 rtw_write8(padapter, REG_HMETFR, 0x0f);
436
437 /* Init H2C counter. by tynli. 2009.12.09. */
438 pHalData->LastHMEBoxNum = 0;
439 /* pHalData->H2CQueueHead = 0; */
440 /* pHalData->H2CQueueTail = 0; */
441 /* pHalData->H2CStopInsertQueue = false; */
442 }
443
444 /* */
445 /* Efuse related code */
446 /* */
hal_EfuseSwitchToBank(struct adapter * padapter,u8 bank,bool bPseudoTest)447 static u8 hal_EfuseSwitchToBank(
448 struct adapter *padapter, u8 bank, bool bPseudoTest
449 )
450 {
451 u8 bRet = false;
452 u32 value32 = 0;
453 #ifdef HAL_EFUSE_MEMORY
454 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
455 struct efuse_hal *pEfuseHal = &pHalData->EfuseHal;
456 #endif
457
458
459 if (bPseudoTest) {
460 #ifdef HAL_EFUSE_MEMORY
461 pEfuseHal->fakeEfuseBank = bank;
462 #else
463 fakeEfuseBank = bank;
464 #endif
465 bRet = true;
466 } else {
467 value32 = rtw_read32(padapter, EFUSE_TEST);
468 bRet = true;
469 switch (bank) {
470 case 0:
471 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
472 break;
473 case 1:
474 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);
475 break;
476 case 2:
477 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);
478 break;
479 case 3:
480 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);
481 break;
482 default:
483 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
484 bRet = false;
485 break;
486 }
487 rtw_write32(padapter, EFUSE_TEST, value32);
488 }
489
490 return bRet;
491 }
492
Hal_GetEfuseDefinition(struct adapter * padapter,u8 efuseType,u8 type,void * pOut,bool bPseudoTest)493 void Hal_GetEfuseDefinition(
494 struct adapter *padapter,
495 u8 efuseType,
496 u8 type,
497 void *pOut,
498 bool bPseudoTest
499 )
500 {
501 switch (type) {
502 case TYPE_EFUSE_MAX_SECTION:
503 {
504 u8 *pMax_section;
505 pMax_section = pOut;
506
507 if (efuseType == EFUSE_WIFI)
508 *pMax_section = EFUSE_MAX_SECTION_8723B;
509 else
510 *pMax_section = EFUSE_BT_MAX_SECTION;
511 }
512 break;
513
514 case TYPE_EFUSE_REAL_CONTENT_LEN:
515 {
516 u16 *pu2Tmp;
517 pu2Tmp = pOut;
518
519 if (efuseType == EFUSE_WIFI)
520 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8723B;
521 else
522 *pu2Tmp = EFUSE_BT_REAL_CONTENT_LEN;
523 }
524 break;
525
526 case TYPE_AVAILABLE_EFUSE_BYTES_BANK:
527 {
528 u16 *pu2Tmp;
529 pu2Tmp = pOut;
530
531 if (efuseType == EFUSE_WIFI)
532 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8723B-EFUSE_OOB_PROTECT_BYTES);
533 else
534 *pu2Tmp = (EFUSE_BT_REAL_BANK_CONTENT_LEN-EFUSE_PROTECT_BYTES_BANK);
535 }
536 break;
537
538 case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL:
539 {
540 u16 *pu2Tmp;
541 pu2Tmp = pOut;
542
543 if (efuseType == EFUSE_WIFI)
544 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8723B-EFUSE_OOB_PROTECT_BYTES);
545 else
546 *pu2Tmp = (EFUSE_BT_REAL_CONTENT_LEN-(EFUSE_PROTECT_BYTES_BANK*3));
547 }
548 break;
549
550 case TYPE_EFUSE_MAP_LEN:
551 {
552 u16 *pu2Tmp;
553 pu2Tmp = pOut;
554
555 if (efuseType == EFUSE_WIFI)
556 *pu2Tmp = EFUSE_MAX_MAP_LEN;
557 else
558 *pu2Tmp = EFUSE_BT_MAP_LEN;
559 }
560 break;
561
562 case TYPE_EFUSE_PROTECT_BYTES_BANK:
563 {
564 u8 *pu1Tmp;
565 pu1Tmp = pOut;
566
567 if (efuseType == EFUSE_WIFI)
568 *pu1Tmp = EFUSE_OOB_PROTECT_BYTES;
569 else
570 *pu1Tmp = EFUSE_PROTECT_BYTES_BANK;
571 }
572 break;
573
574 case TYPE_EFUSE_CONTENT_LEN_BANK:
575 {
576 u16 *pu2Tmp;
577 pu2Tmp = pOut;
578
579 if (efuseType == EFUSE_WIFI)
580 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8723B;
581 else
582 *pu2Tmp = EFUSE_BT_REAL_BANK_CONTENT_LEN;
583 }
584 break;
585
586 default:
587 {
588 u8 *pu1Tmp;
589 pu1Tmp = pOut;
590 *pu1Tmp = 0;
591 }
592 break;
593 }
594 }
595
596 #define VOLTAGE_V25 0x03
597
598 /* */
599 /* The following is for compile ok */
600 /* That should be merged with the original in the future */
601 /* */
602 #define EFUSE_ACCESS_ON_8723 0x69 /* For RTL8723 only. */
603 #define REG_EFUSE_ACCESS_8723 0x00CF /* Efuse access protection for RTL8723 */
604
Hal_EfusePowerSwitch(struct adapter * padapter,u8 bWrite,u8 PwrState)605 void Hal_EfusePowerSwitch(
606 struct adapter *padapter, u8 bWrite, u8 PwrState
607 )
608 {
609 u8 tempval;
610 u16 tmpV16;
611
612
613 if (PwrState) {
614 /* To avoid cannot access efuse registers after disable/enable several times during DTM test. */
615 /* Suggested by SD1 IsaacHsu. 2013.07.08, added by tynli. */
616 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL);
617 if (tempval & BIT(0)) { /* SDIO local register is suspend */
618 u8 count = 0;
619
620
621 tempval &= ~BIT(0);
622 rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL, tempval);
623
624 /* check 0x86[1:0]= 10'2h, wait power state to leave suspend */
625 do {
626 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL);
627 tempval &= 0x3;
628 if (tempval == 0x02)
629 break;
630
631 count++;
632 if (count >= 100)
633 break;
634
635 mdelay(10);
636 } while (1);
637 }
638
639 rtw_write8(padapter, REG_EFUSE_ACCESS_8723, EFUSE_ACCESS_ON_8723);
640
641 /* Reset: 0x0000h[28], default valid */
642 tmpV16 = rtw_read16(padapter, REG_SYS_FUNC_EN);
643 if (!(tmpV16 & FEN_ELDR)) {
644 tmpV16 |= FEN_ELDR;
645 rtw_write16(padapter, REG_SYS_FUNC_EN, tmpV16);
646 }
647
648 /* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */
649 tmpV16 = rtw_read16(padapter, REG_SYS_CLKR);
650 if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) {
651 tmpV16 |= (LOADER_CLK_EN | ANA8M);
652 rtw_write16(padapter, REG_SYS_CLKR, tmpV16);
653 }
654
655 if (bWrite) {
656 /* Enable LDO 2.5V before read/write action */
657 tempval = rtw_read8(padapter, EFUSE_TEST+3);
658 tempval &= 0x0F;
659 tempval |= (VOLTAGE_V25 << 4);
660 rtw_write8(padapter, EFUSE_TEST+3, (tempval | 0x80));
661
662 /* rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); */
663 }
664 } else {
665 rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
666
667 if (bWrite) {
668 /* Disable LDO 2.5V after read/write action */
669 tempval = rtw_read8(padapter, EFUSE_TEST+3);
670 rtw_write8(padapter, EFUSE_TEST+3, (tempval & 0x7F));
671 }
672
673 }
674 }
675
hal_ReadEFuse_WiFi(struct adapter * padapter,u16 _offset,u16 _size_byte,u8 * pbuf,bool bPseudoTest)676 static void hal_ReadEFuse_WiFi(
677 struct adapter *padapter,
678 u16 _offset,
679 u16 _size_byte,
680 u8 *pbuf,
681 bool bPseudoTest
682 )
683 {
684 #ifdef HAL_EFUSE_MEMORY
685 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
686 struct efuse_hal *pEfuseHal = &pHalData->EfuseHal;
687 #endif
688 u8 *efuseTbl = NULL;
689 u16 eFuse_Addr = 0;
690 u8 offset, wden;
691 u8 efuseHeader, efuseExtHdr, efuseData;
692 u16 i, total, used;
693 u8 efuse_usage = 0;
694
695 /* */
696 /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
697 /* */
698 if ((_offset + _size_byte) > EFUSE_MAX_MAP_LEN)
699 return;
700
701 efuseTbl = rtw_malloc(EFUSE_MAX_MAP_LEN);
702 if (!efuseTbl)
703 return;
704
705 /* 0xff will be efuse default value instead of 0x00. */
706 memset(efuseTbl, 0xFF, EFUSE_MAX_MAP_LEN);
707
708 /* switch bank back to bank 0 for later BT and wifi use. */
709 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
710
711 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
712 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
713 if (efuseHeader == 0xFF)
714 break;
715
716 /* Check PG header for section num. */
717 if (EXT_HEADER(efuseHeader)) { /* extended header */
718 offset = GET_HDR_OFFSET_2_0(efuseHeader);
719
720 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
721 if (ALL_WORDS_DISABLED(efuseExtHdr))
722 continue;
723
724 offset |= ((efuseExtHdr & 0xF0) >> 1);
725 wden = (efuseExtHdr & 0x0F);
726 } else {
727 offset = ((efuseHeader >> 4) & 0x0f);
728 wden = (efuseHeader & 0x0f);
729 }
730
731 if (offset < EFUSE_MAX_SECTION_8723B) {
732 u16 addr;
733 /* Get word enable value from PG header */
734
735 addr = offset * PGPKT_DATA_SIZE;
736 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
737 /* Check word enable condition in the section */
738 if (!(wden & (0x01<<i))) {
739 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
740 efuseTbl[addr] = efuseData;
741
742 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
743 efuseTbl[addr+1] = efuseData;
744 }
745 addr += 2;
746 }
747 } else {
748 eFuse_Addr += Efuse_CalculateWordCnts(wden)*2;
749 }
750 }
751
752 /* Copy from Efuse map to output pointer memory!!! */
753 for (i = 0; i < _size_byte; i++)
754 pbuf[i] = efuseTbl[_offset+i];
755
756 /* Calculate Efuse utilization */
757 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
758 used = eFuse_Addr - 1;
759 efuse_usage = (u8)((used*100)/total);
760 if (bPseudoTest) {
761 #ifdef HAL_EFUSE_MEMORY
762 pEfuseHal->fakeEfuseUsedBytes = used;
763 #else
764 fakeEfuseUsedBytes = used;
765 #endif
766 } else {
767 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&used);
768 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_USAGE, (u8 *)&efuse_usage);
769 }
770
771 kfree(efuseTbl);
772 }
773
hal_ReadEFuse_BT(struct adapter * padapter,u16 _offset,u16 _size_byte,u8 * pbuf,bool bPseudoTest)774 static void hal_ReadEFuse_BT(
775 struct adapter *padapter,
776 u16 _offset,
777 u16 _size_byte,
778 u8 *pbuf,
779 bool bPseudoTest
780 )
781 {
782 #ifdef HAL_EFUSE_MEMORY
783 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
784 struct efuse_hal *pEfuseHal = &pHalData->EfuseHal;
785 #endif
786 u8 *efuseTbl;
787 u8 bank;
788 u16 eFuse_Addr;
789 u8 efuseHeader, efuseExtHdr, efuseData;
790 u8 offset, wden;
791 u16 i, total, used;
792 u8 efuse_usage;
793
794
795 /* */
796 /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
797 /* */
798 if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN)
799 return;
800
801 efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN);
802 if (!efuseTbl)
803 return;
804
805 /* 0xff will be efuse default value instead of 0x00. */
806 memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
807
808 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total, bPseudoTest);
809
810 for (bank = 1; bank < 3; bank++) { /* 8723b Max bake 0~2 */
811 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == false)
812 goto exit;
813
814 eFuse_Addr = 0;
815
816 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
817 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
818 if (efuseHeader == 0xFF)
819 break;
820
821 /* Check PG header for section num. */
822 if (EXT_HEADER(efuseHeader)) { /* extended header */
823 offset = GET_HDR_OFFSET_2_0(efuseHeader);
824
825 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
826 if (ALL_WORDS_DISABLED(efuseExtHdr))
827 continue;
828
829
830 offset |= ((efuseExtHdr & 0xF0) >> 1);
831 wden = (efuseExtHdr & 0x0F);
832 } else {
833 offset = ((efuseHeader >> 4) & 0x0f);
834 wden = (efuseHeader & 0x0f);
835 }
836
837 if (offset < EFUSE_BT_MAX_SECTION) {
838 u16 addr;
839
840 addr = offset * PGPKT_DATA_SIZE;
841 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
842 /* Check word enable condition in the section */
843 if (!(wden & (0x01<<i))) {
844 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
845 efuseTbl[addr] = efuseData;
846
847 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
848 efuseTbl[addr+1] = efuseData;
849 }
850 addr += 2;
851 }
852 } else {
853 eFuse_Addr += Efuse_CalculateWordCnts(wden)*2;
854 }
855 }
856
857 if ((eFuse_Addr - 1) < total)
858 break;
859
860 }
861
862 /* switch bank back to bank 0 for later BT and wifi use. */
863 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
864
865 /* Copy from Efuse map to output pointer memory!!! */
866 for (i = 0; i < _size_byte; i++)
867 pbuf[i] = efuseTbl[_offset+i];
868
869 /* */
870 /* Calculate Efuse utilization. */
871 /* */
872 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
873 used = (EFUSE_BT_REAL_BANK_CONTENT_LEN*(bank-1)) + eFuse_Addr - 1;
874 efuse_usage = (u8)((used*100)/total);
875 if (bPseudoTest) {
876 #ifdef HAL_EFUSE_MEMORY
877 pEfuseHal->fakeBTEfuseUsedBytes = used;
878 #else
879 fakeBTEfuseUsedBytes = used;
880 #endif
881 } else {
882 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&used);
883 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_USAGE, (u8 *)&efuse_usage);
884 }
885
886 exit:
887 kfree(efuseTbl);
888 }
889
Hal_ReadEFuse(struct adapter * padapter,u8 efuseType,u16 _offset,u16 _size_byte,u8 * pbuf,bool bPseudoTest)890 void Hal_ReadEFuse(
891 struct adapter *padapter,
892 u8 efuseType,
893 u16 _offset,
894 u16 _size_byte,
895 u8 *pbuf,
896 bool bPseudoTest
897 )
898 {
899 if (efuseType == EFUSE_WIFI)
900 hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf, bPseudoTest);
901 else
902 hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf, bPseudoTest);
903 }
904
hal_EfuseGetCurrentSize_WiFi(struct adapter * padapter,bool bPseudoTest)905 static u16 hal_EfuseGetCurrentSize_WiFi(
906 struct adapter *padapter, bool bPseudoTest
907 )
908 {
909 #ifdef HAL_EFUSE_MEMORY
910 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
911 struct efuse_hal *pEfuseHal = &pHalData->EfuseHal;
912 #endif
913 u16 efuse_addr = 0;
914 u16 start_addr = 0; /* for debug */
915 u8 hworden = 0;
916 u8 efuse_data, word_cnts = 0;
917 u32 count = 0; /* for debug */
918
919
920 if (bPseudoTest) {
921 #ifdef HAL_EFUSE_MEMORY
922 efuse_addr = (u16)pEfuseHal->fakeEfuseUsedBytes;
923 #else
924 efuse_addr = (u16)fakeEfuseUsedBytes;
925 #endif
926 } else
927 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
928
929 start_addr = efuse_addr;
930
931 /* switch bank back to bank 0 for later BT and wifi use. */
932 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
933
934 count = 0;
935 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
936 if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == false)
937 goto error;
938
939 if (efuse_data == 0xFF)
940 break;
941
942 if ((start_addr != 0) && (efuse_addr == start_addr)) {
943 count++;
944
945 efuse_data = 0xFF;
946 if (count < 4) {
947 /* try again! */
948
949 if (count > 2) {
950 /* try again form address 0 */
951 efuse_addr = 0;
952 start_addr = 0;
953 }
954
955 continue;
956 }
957
958 goto error;
959 }
960
961 if (EXT_HEADER(efuse_data)) {
962 efuse_addr++;
963 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
964 if (ALL_WORDS_DISABLED(efuse_data))
965 continue;
966
967 hworden = efuse_data & 0x0F;
968 } else {
969 hworden = efuse_data & 0x0F;
970 }
971
972 word_cnts = Efuse_CalculateWordCnts(hworden);
973 efuse_addr += (word_cnts*2)+1;
974 }
975
976 if (bPseudoTest) {
977 #ifdef HAL_EFUSE_MEMORY
978 pEfuseHal->fakeEfuseUsedBytes = efuse_addr;
979 #else
980 fakeEfuseUsedBytes = efuse_addr;
981 #endif
982 } else
983 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
984
985 goto exit;
986
987 error:
988 /* report max size to prevent write efuse */
989 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_addr, bPseudoTest);
990
991 exit:
992
993 return efuse_addr;
994 }
995
hal_EfuseGetCurrentSize_BT(struct adapter * padapter,u8 bPseudoTest)996 static u16 hal_EfuseGetCurrentSize_BT(struct adapter *padapter, u8 bPseudoTest)
997 {
998 #ifdef HAL_EFUSE_MEMORY
999 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1000 struct efuse_hal *pEfuseHal = &pHalData->EfuseHal;
1001 #endif
1002 u16 btusedbytes;
1003 u16 efuse_addr;
1004 u8 bank, startBank;
1005 u8 hworden = 0;
1006 u8 efuse_data, word_cnts = 0;
1007 u16 retU2 = 0;
1008
1009 if (bPseudoTest) {
1010 #ifdef HAL_EFUSE_MEMORY
1011 btusedbytes = pEfuseHal->fakeBTEfuseUsedBytes;
1012 #else
1013 btusedbytes = fakeBTEfuseUsedBytes;
1014 #endif
1015 } else
1016 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&btusedbytes);
1017
1018 efuse_addr = (u16)((btusedbytes%EFUSE_BT_REAL_BANK_CONTENT_LEN));
1019 startBank = (u8)(1+(btusedbytes/EFUSE_BT_REAL_BANK_CONTENT_LEN));
1020
1021 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2, bPseudoTest);
1022
1023 for (bank = startBank; bank < 3; bank++) {
1024 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == false)
1025 /* bank = EFUSE_MAX_BANK; */
1026 break;
1027
1028 /* only when bank is switched we have to reset the efuse_addr. */
1029 if (bank != startBank)
1030 efuse_addr = 0;
1031
1032 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
1033 if (efuse_OneByteRead(padapter, efuse_addr,
1034 &efuse_data, bPseudoTest) == false)
1035 /* bank = EFUSE_MAX_BANK; */
1036 break;
1037
1038 if (efuse_data == 0xFF)
1039 break;
1040
1041 if (EXT_HEADER(efuse_data)) {
1042 efuse_addr++;
1043 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
1044
1045 if (ALL_WORDS_DISABLED(efuse_data)) {
1046 efuse_addr++;
1047 continue;
1048 }
1049
1050 hworden = efuse_data & 0x0F;
1051 } else {
1052 hworden = efuse_data & 0x0F;
1053 }
1054
1055 word_cnts = Efuse_CalculateWordCnts(hworden);
1056 /* read next header */
1057 efuse_addr += (word_cnts*2)+1;
1058 }
1059
1060 /* Check if we need to check next bank efuse */
1061 if (efuse_addr < retU2)
1062 break; /* don't need to check next bank. */
1063 }
1064
1065 retU2 = ((bank-1)*EFUSE_BT_REAL_BANK_CONTENT_LEN)+efuse_addr;
1066 if (bPseudoTest) {
1067 pEfuseHal->fakeBTEfuseUsedBytes = retU2;
1068 } else {
1069 pEfuseHal->BTEfuseUsedBytes = retU2;
1070 }
1071
1072 return retU2;
1073 }
1074
Hal_EfuseGetCurrentSize(struct adapter * padapter,u8 efuseType,bool bPseudoTest)1075 u16 Hal_EfuseGetCurrentSize(
1076 struct adapter *padapter, u8 efuseType, bool bPseudoTest
1077 )
1078 {
1079 u16 ret = 0;
1080
1081 if (efuseType == EFUSE_WIFI)
1082 ret = hal_EfuseGetCurrentSize_WiFi(padapter, bPseudoTest);
1083 else
1084 ret = hal_EfuseGetCurrentSize_BT(padapter, bPseudoTest);
1085
1086 return ret;
1087 }
1088
Hal_EfuseWordEnableDataWrite(struct adapter * padapter,u16 efuse_addr,u8 word_en,u8 * data,bool bPseudoTest)1089 static u8 Hal_EfuseWordEnableDataWrite(
1090 struct adapter *padapter,
1091 u16 efuse_addr,
1092 u8 word_en,
1093 u8 *data,
1094 bool bPseudoTest
1095 )
1096 {
1097 u16 tmpaddr = 0;
1098 u16 start_addr = efuse_addr;
1099 u8 badworden = 0x0F;
1100 u8 tmpdata[PGPKT_DATA_SIZE];
1101
1102 memset(tmpdata, 0xFF, PGPKT_DATA_SIZE);
1103
1104 if (!(word_en & BIT(0))) {
1105 tmpaddr = start_addr;
1106 efuse_OneByteWrite(padapter, start_addr++, data[0], bPseudoTest);
1107 efuse_OneByteWrite(padapter, start_addr++, data[1], bPseudoTest);
1108
1109 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[0], bPseudoTest);
1110 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[1], bPseudoTest);
1111 if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1])) {
1112 badworden &= (~BIT(0));
1113 }
1114 }
1115 if (!(word_en & BIT(1))) {
1116 tmpaddr = start_addr;
1117 efuse_OneByteWrite(padapter, start_addr++, data[2], bPseudoTest);
1118 efuse_OneByteWrite(padapter, start_addr++, data[3], bPseudoTest);
1119
1120 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[2], bPseudoTest);
1121 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[3], bPseudoTest);
1122 if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3])) {
1123 badworden &= (~BIT(1));
1124 }
1125 }
1126
1127 if (!(word_en & BIT(2))) {
1128 tmpaddr = start_addr;
1129 efuse_OneByteWrite(padapter, start_addr++, data[4], bPseudoTest);
1130 efuse_OneByteWrite(padapter, start_addr++, data[5], bPseudoTest);
1131
1132 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[4], bPseudoTest);
1133 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[5], bPseudoTest);
1134 if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5])) {
1135 badworden &= (~BIT(2));
1136 }
1137 }
1138
1139 if (!(word_en & BIT(3))) {
1140 tmpaddr = start_addr;
1141 efuse_OneByteWrite(padapter, start_addr++, data[6], bPseudoTest);
1142 efuse_OneByteWrite(padapter, start_addr++, data[7], bPseudoTest);
1143
1144 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[6], bPseudoTest);
1145 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[7], bPseudoTest);
1146 if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7])) {
1147 badworden &= (~BIT(3));
1148 }
1149 }
1150
1151 return badworden;
1152 }
1153
ReadChipVersion8723B(struct adapter * padapter)1154 static struct hal_version ReadChipVersion8723B(struct adapter *padapter)
1155 {
1156 u32 value32;
1157 struct hal_version ChipVersion;
1158 struct hal_com_data *pHalData;
1159
1160 /* YJ, TODO, move read chip type here */
1161 pHalData = GET_HAL_DATA(padapter);
1162
1163 value32 = rtw_read32(padapter, REG_SYS_CFG);
1164 ChipVersion.ICType = CHIP_8723B;
1165 ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
1166 ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
1167 ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
1168
1169 /* For regulator mode. by tynli. 2011.01.14 */
1170 pHalData->RegulatorMode = ((value32 & SPS_SEL) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
1171
1172 value32 = rtw_read32(padapter, REG_GPIO_OUTSTS);
1173 ChipVersion.ROMVer = ((value32 & RF_RL_ID) >> 20); /* ROM code version. */
1174
1175 /* For multi-function consideration. Added by Roger, 2010.10.06. */
1176 pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
1177 value32 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
1178 pHalData->MultiFunc |= ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0);
1179 pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0);
1180 pHalData->MultiFunc |= ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0);
1181 pHalData->PolarityCtl = ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT);
1182
1183 dump_chip_info(ChipVersion);
1184
1185 pHalData->VersionID = ChipVersion;
1186
1187 return ChipVersion;
1188 }
1189
rtl8723b_read_chip_version(struct adapter * padapter)1190 void rtl8723b_read_chip_version(struct adapter *padapter)
1191 {
1192 ReadChipVersion8723B(padapter);
1193 }
1194
rtl8723b_InitBeaconParameters(struct adapter * padapter)1195 void rtl8723b_InitBeaconParameters(struct adapter *padapter)
1196 {
1197 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1198 u16 val16;
1199 u8 val8;
1200
1201
1202 val8 = DIS_TSF_UDT;
1203 val16 = val8 | (val8 << 8); /* port0 and port1 */
1204
1205 /* Enable prot0 beacon function for PSTDMA */
1206 val16 |= EN_BCN_FUNCTION;
1207
1208 rtw_write16(padapter, REG_BCN_CTRL, val16);
1209
1210 /* TODO: Remove these magic number */
1211 rtw_write16(padapter, REG_TBTT_PROHIBIT, 0x6404);/* ms */
1212 /* Firmware will control REG_DRVERLYINT when power saving is enable, */
1213 /* so don't set this register on STA mode. */
1214 if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == false)
1215 rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8723B); /* 5ms */
1216 rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8723B); /* 2ms */
1217
1218 /* Suggested by designer timchen. Change beacon AIFS to the largest number */
1219 /* because test chip does not contension before sending beacon. by tynli. 2009.11.03 */
1220 rtw_write16(padapter, REG_BCNTCFG, 0x660F);
1221
1222 pHalData->RegBcnCtrlVal = rtw_read8(padapter, REG_BCN_CTRL);
1223 pHalData->RegTxPause = rtw_read8(padapter, REG_TXPAUSE);
1224 pHalData->RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2);
1225 pHalData->RegReg542 = rtw_read8(padapter, REG_TBTT_PROHIBIT+2);
1226 pHalData->RegCR_1 = rtw_read8(padapter, REG_CR+1);
1227 }
1228
_InitBurstPktLen_8723BS(struct adapter * Adapter)1229 void _InitBurstPktLen_8723BS(struct adapter *Adapter)
1230 {
1231 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1232
1233 rtw_write8(Adapter, 0x4c7, rtw_read8(Adapter, 0x4c7)|BIT(7)); /* enable single pkt ampdu */
1234 rtw_write8(Adapter, REG_RX_PKT_LIMIT_8723B, 0x18); /* for VHT packet length 11K */
1235 rtw_write8(Adapter, REG_MAX_AGGR_NUM_8723B, 0x1F);
1236 rtw_write8(Adapter, REG_PIFS_8723B, 0x00);
1237 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8723B, rtw_read8(Adapter, REG_FWHW_TXQ_CTRL)&(~BIT(7)));
1238 if (pHalData->AMPDUBurstMode)
1239 rtw_write8(Adapter, REG_AMPDU_BURST_MODE_8723B, 0x5F);
1240 rtw_write8(Adapter, REG_AMPDU_MAX_TIME_8723B, 0x70);
1241
1242 /* ARFB table 9 for 11ac 5G 2SS */
1243 rtw_write32(Adapter, REG_ARFR0_8723B, 0x00000010);
1244 if (IS_NORMAL_CHIP(pHalData->VersionID))
1245 rtw_write32(Adapter, REG_ARFR0_8723B+4, 0xfffff000);
1246 else
1247 rtw_write32(Adapter, REG_ARFR0_8723B+4, 0x3e0ff000);
1248
1249 /* ARFB table 10 for 11ac 5G 1SS */
1250 rtw_write32(Adapter, REG_ARFR1_8723B, 0x00000010);
1251 rtw_write32(Adapter, REG_ARFR1_8723B+4, 0x003ff000);
1252 }
1253
ResumeTxBeacon(struct adapter * padapter)1254 static void ResumeTxBeacon(struct adapter *padapter)
1255 {
1256 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1257
1258 pHalData->RegFwHwTxQCtrl |= BIT(6);
1259 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
1260 rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0xff);
1261 pHalData->RegReg542 |= BIT(0);
1262 rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542);
1263 }
1264
StopTxBeacon(struct adapter * padapter)1265 static void StopTxBeacon(struct adapter *padapter)
1266 {
1267 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1268
1269 pHalData->RegFwHwTxQCtrl &= ~BIT(6);
1270 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
1271 rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0x64);
1272 pHalData->RegReg542 &= ~BIT(0);
1273 rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542);
1274
1275 CheckFwRsvdPageContent(padapter); /* 2010.06.23. Added by tynli. */
1276 }
1277
_BeaconFunctionEnable(struct adapter * padapter,u8 Enable,u8 Linked)1278 static void _BeaconFunctionEnable(struct adapter *padapter, u8 Enable, u8 Linked)
1279 {
1280 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
1281 rtw_write8(padapter, REG_RD_CTRL+1, 0x6F);
1282 }
1283
rtl8723b_SetBeaconRelatedRegisters(struct adapter * padapter)1284 void rtl8723b_SetBeaconRelatedRegisters(struct adapter *padapter)
1285 {
1286 u8 val8;
1287 u32 value32;
1288 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
1289 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1290 u32 bcn_ctrl_reg;
1291
1292 /* reset TSF, enable update TSF, correcting TSF On Beacon */
1293
1294 /* REG_BCN_INTERVAL */
1295 /* REG_BCNDMATIM */
1296 /* REG_ATIMWND */
1297 /* REG_TBTT_PROHIBIT */
1298 /* REG_DRVERLYINT */
1299 /* REG_BCN_MAX_ERR */
1300 /* REG_BCNTCFG (0x510) */
1301 /* REG_DUAL_TSF_RST */
1302 /* REG_BCN_CTRL (0x550) */
1303
1304
1305 bcn_ctrl_reg = REG_BCN_CTRL;
1306
1307 /* */
1308 /* ATIM window */
1309 /* */
1310 rtw_write16(padapter, REG_ATIMWND, 2);
1311
1312 /* */
1313 /* Beacon interval (in unit of TU). */
1314 /* */
1315 rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
1316
1317 rtl8723b_InitBeaconParameters(padapter);
1318
1319 rtw_write8(padapter, REG_SLOT, 0x09);
1320
1321 /* */
1322 /* Reset TSF Timer to zero, added by Roger. 2008.06.24 */
1323 /* */
1324 value32 = rtw_read32(padapter, REG_TCR);
1325 value32 &= ~TSFRST;
1326 rtw_write32(padapter, REG_TCR, value32);
1327
1328 value32 |= TSFRST;
1329 rtw_write32(padapter, REG_TCR, value32);
1330
1331 /* NOTE: Fix test chip's bug (about contention windows's randomness) */
1332 if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE) == true) {
1333 rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
1334 rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
1335 }
1336
1337 _BeaconFunctionEnable(padapter, true, true);
1338
1339 ResumeTxBeacon(padapter);
1340 val8 = rtw_read8(padapter, bcn_ctrl_reg);
1341 val8 |= DIS_BCNQ_SUB;
1342 rtw_write8(padapter, bcn_ctrl_reg, val8);
1343 }
1344
rtl8723b_SetHalODMVar(struct adapter * Adapter,enum hal_odm_variable eVariable,void * pValue1,bool bSet)1345 static void rtl8723b_SetHalODMVar(
1346 struct adapter *Adapter,
1347 enum hal_odm_variable eVariable,
1348 void *pValue1,
1349 bool bSet
1350 )
1351 {
1352 SetHalODMVar(Adapter, eVariable, pValue1, bSet);
1353 }
1354
hal_notch_filter_8723b(struct adapter * adapter,bool enable)1355 static void hal_notch_filter_8723b(struct adapter *adapter, bool enable)
1356 {
1357 if (enable)
1358 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1);
1359 else
1360 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1);
1361 }
1362
UpdateHalRAMask8723B(struct adapter * padapter,u32 mac_id,u8 rssi_level)1363 void UpdateHalRAMask8723B(struct adapter *padapter, u32 mac_id, u8 rssi_level)
1364 {
1365 u32 mask, rate_bitmap;
1366 u8 shortGIrate = false;
1367 struct sta_info *psta;
1368 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1369 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1370 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
1371 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
1372
1373 if (mac_id >= NUM_STA) /* CAM_SIZE */
1374 return;
1375
1376 psta = pmlmeinfo->FW_sta_info[mac_id].psta;
1377 if (!psta)
1378 return;
1379
1380 shortGIrate = query_ra_short_GI(psta);
1381
1382 mask = psta->ra_mask;
1383
1384 rate_bitmap = 0xffffffff;
1385 rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, mac_id, mask, rssi_level);
1386
1387 mask &= rate_bitmap;
1388
1389 rate_bitmap = hal_btcoex_GetRaMask(padapter);
1390 mask &= ~rate_bitmap;
1391
1392 if (pHalData->fw_ractrl) {
1393 rtl8723b_set_FwMacIdConfig_cmd(padapter, mac_id, psta->raid, psta->bw_mode, shortGIrate, mask);
1394 }
1395
1396 /* set correct initial date rate for each mac_id */
1397 pdmpriv->INIDATA_RATE[mac_id] = psta->init_rate;
1398 }
1399
1400
rtl8723b_set_hal_ops(struct hal_ops * pHalFunc)1401 void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc)
1402 {
1403 /* Efuse related function */
1404 pHalFunc->Efuse_WordEnableDataWrite = &Hal_EfuseWordEnableDataWrite;
1405
1406 pHalFunc->SetHalODMVarHandler = &rtl8723b_SetHalODMVar;
1407
1408 pHalFunc->xmit_thread_handler = &hal_xmit_handler;
1409 pHalFunc->hal_notch_filter = &hal_notch_filter_8723b;
1410
1411 pHalFunc->c2h_handler = c2h_handler_8723b;
1412 pHalFunc->c2h_id_filter_ccx = c2h_id_filter_ccx_8723b;
1413
1414 pHalFunc->fill_h2c_cmd = &FillH2CCmd8723B;
1415 }
1416
rtl8723b_InitAntenna_Selection(struct adapter * padapter)1417 void rtl8723b_InitAntenna_Selection(struct adapter *padapter)
1418 {
1419 u8 val;
1420
1421 val = rtw_read8(padapter, REG_LEDCFG2);
1422 /* Let 8051 take control antenna setting */
1423 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
1424 rtw_write8(padapter, REG_LEDCFG2, val);
1425 }
1426
rtl8723b_init_default_value(struct adapter * padapter)1427 void rtl8723b_init_default_value(struct adapter *padapter)
1428 {
1429 struct hal_com_data *pHalData;
1430 struct dm_priv *pdmpriv;
1431 u8 i;
1432
1433
1434 pHalData = GET_HAL_DATA(padapter);
1435 pdmpriv = &pHalData->dmpriv;
1436
1437 padapter->registrypriv.wireless_mode = WIRELESS_11BG_24N;
1438
1439 /* init default value */
1440 pHalData->fw_ractrl = false;
1441 pHalData->bIQKInitialized = false;
1442 if (!adapter_to_pwrctl(padapter)->bkeepfwalive)
1443 pHalData->LastHMEBoxNum = 0;
1444
1445 pHalData->bIQKInitialized = false;
1446
1447 /* init dm default value */
1448 pdmpriv->TM_Trigger = 0;/* for IQK */
1449 /* pdmpriv->binitialized = false; */
1450 /* pdmpriv->prv_traffic_idx = 3; */
1451 /* pdmpriv->initialize = 0; */
1452
1453 pdmpriv->ThermalValue_HP_index = 0;
1454 for (i = 0; i < HP_THERMAL_NUM; i++)
1455 pdmpriv->ThermalValue_HP[i] = 0;
1456
1457 /* init Efuse variables */
1458 pHalData->EfuseUsedBytes = 0;
1459 pHalData->EfuseUsedPercentage = 0;
1460 #ifdef HAL_EFUSE_MEMORY
1461 pHalData->EfuseHal.fakeEfuseBank = 0;
1462 pHalData->EfuseHal.fakeEfuseUsedBytes = 0;
1463 memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE);
1464 memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN);
1465 memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
1466 pHalData->EfuseHal.BTEfuseUsedBytes = 0;
1467 pHalData->EfuseHal.BTEfuseUsedPercentage = 0;
1468 memset(pHalData->EfuseHal.BTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK*EFUSE_MAX_HW_SIZE);
1469 memset(pHalData->EfuseHal.BTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
1470 memset(pHalData->EfuseHal.BTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
1471 pHalData->EfuseHal.fakeBTEfuseUsedBytes = 0;
1472 memset(pHalData->EfuseHal.fakeBTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK*EFUSE_MAX_HW_SIZE);
1473 memset(pHalData->EfuseHal.fakeBTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
1474 memset(pHalData->EfuseHal.fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
1475 #endif
1476 }
1477
GetEEPROMSize8723B(struct adapter * padapter)1478 u8 GetEEPROMSize8723B(struct adapter *padapter)
1479 {
1480 u8 size = 0;
1481 u32 cr;
1482
1483 cr = rtw_read16(padapter, REG_9346CR);
1484 /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */
1485 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
1486
1487 return size;
1488 }
1489
1490 /* */
1491 /* */
1492 /* LLT R/W/Init function */
1493 /* */
1494 /* */
rtl8723b_InitLLTTable(struct adapter * padapter)1495 s32 rtl8723b_InitLLTTable(struct adapter *padapter)
1496 {
1497 unsigned long start, passing_time;
1498 u32 val32;
1499 s32 ret;
1500
1501
1502 ret = _FAIL;
1503
1504 val32 = rtw_read32(padapter, REG_AUTO_LLT);
1505 val32 |= BIT_AUTO_INIT_LLT;
1506 rtw_write32(padapter, REG_AUTO_LLT, val32);
1507
1508 start = jiffies;
1509
1510 do {
1511 val32 = rtw_read32(padapter, REG_AUTO_LLT);
1512 if (!(val32 & BIT_AUTO_INIT_LLT)) {
1513 ret = _SUCCESS;
1514 break;
1515 }
1516
1517 passing_time = jiffies_to_msecs(jiffies - start);
1518 if (passing_time > 1000)
1519 break;
1520
1521 msleep(1);
1522 } while (1);
1523
1524 return ret;
1525 }
1526
hal_get_chnl_group_8723b(u8 channel,u8 * group)1527 static void hal_get_chnl_group_8723b(u8 channel, u8 *group)
1528 {
1529 if (1 <= channel && channel <= 2)
1530 *group = 0;
1531 else if (3 <= channel && channel <= 5)
1532 *group = 1;
1533 else if (6 <= channel && channel <= 8)
1534 *group = 2;
1535 else if (9 <= channel && channel <= 11)
1536 *group = 3;
1537 else if (12 <= channel && channel <= 14)
1538 *group = 4;
1539 }
1540
Hal_InitPGData(struct adapter * padapter,u8 * PROMContent)1541 void Hal_InitPGData(struct adapter *padapter, u8 *PROMContent)
1542 {
1543 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1544
1545 if (!pEEPROM->bautoload_fail_flag) { /* autoload OK. */
1546 if (!pEEPROM->EepromOrEfuse) {
1547 /* Read EFUSE real map to shadow. */
1548 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false);
1549 memcpy((void *)PROMContent, (void *)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_8723B);
1550 }
1551 } else {/* autoload fail */
1552 if (!pEEPROM->EepromOrEfuse)
1553 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false);
1554 memcpy((void *)PROMContent, (void *)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_8723B);
1555 }
1556 }
1557
Hal_EfuseParseIDCode(struct adapter * padapter,u8 * hwinfo)1558 void Hal_EfuseParseIDCode(struct adapter *padapter, u8 *hwinfo)
1559 {
1560 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1561 /* struct hal_com_data *pHalData = GET_HAL_DATA(padapter); */
1562 u16 EEPROMId;
1563
1564
1565 /* Check 0x8129 again for making sure autoload status!! */
1566 EEPROMId = le16_to_cpu(*((__le16 *)hwinfo));
1567 if (EEPROMId != RTL_EEPROM_ID) {
1568 pEEPROM->bautoload_fail_flag = true;
1569 } else
1570 pEEPROM->bautoload_fail_flag = false;
1571 }
1572
Hal_ReadPowerValueFromPROM_8723B(struct adapter * Adapter,struct TxPowerInfo24G * pwrInfo24G,u8 * PROMContent,bool AutoLoadFail)1573 static void Hal_ReadPowerValueFromPROM_8723B(
1574 struct adapter *Adapter,
1575 struct TxPowerInfo24G *pwrInfo24G,
1576 u8 *PROMContent,
1577 bool AutoLoadFail
1578 )
1579 {
1580 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1581 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX_8723B, group, TxCount = 0;
1582
1583 memset(pwrInfo24G, 0, sizeof(struct TxPowerInfo24G));
1584
1585 if (0xFF == PROMContent[eeAddr+1])
1586 AutoLoadFail = true;
1587
1588 if (AutoLoadFail) {
1589 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
1590 /* 2.4G default value */
1591 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1592 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
1593 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
1594 }
1595
1596 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
1597 if (TxCount == 0) {
1598 pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF;
1599 pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF;
1600 } else {
1601 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1602 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1603 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1604 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1605 }
1606 }
1607 }
1608
1609 return;
1610 }
1611
1612 pHalData->bTXPowerDataReadFromEEPORM = true; /* YJ, move, 120316 */
1613
1614 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
1615 /* 2 2.4G default value */
1616 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1617 pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++];
1618 if (pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF)
1619 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
1620 }
1621
1622 for (group = 0; group < MAX_CHNL_GROUP_24G-1; group++) {
1623 pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++];
1624 if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF)
1625 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
1626 }
1627
1628 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
1629 if (TxCount == 0) {
1630 pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0;
1631 if (PROMContent[eeAddr] == 0xFF)
1632 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF;
1633 else {
1634 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
1635 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
1636 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
1637 }
1638
1639 if (PROMContent[eeAddr] == 0xFF)
1640 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF;
1641 else {
1642 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
1643 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
1644 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
1645 }
1646 pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0;
1647 eeAddr++;
1648 } else {
1649 if (PROMContent[eeAddr] == 0xFF)
1650 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1651 else {
1652 pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
1653 if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
1654 pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0;
1655 }
1656
1657 if (PROMContent[eeAddr] == 0xFF)
1658 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1659 else {
1660 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
1661 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
1662 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
1663 }
1664 eeAddr++;
1665
1666 if (PROMContent[eeAddr] == 0xFF)
1667 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1668 else {
1669 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
1670 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
1671 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
1672 }
1673
1674 if (PROMContent[eeAddr] == 0xFF)
1675 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1676 else {
1677 pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
1678 if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
1679 pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0;
1680 }
1681 eeAddr++;
1682 }
1683 }
1684 }
1685 }
1686
1687
Hal_EfuseParseTxPowerInfo_8723B(struct adapter * padapter,u8 * PROMContent,bool AutoLoadFail)1688 void Hal_EfuseParseTxPowerInfo_8723B(
1689 struct adapter *padapter, u8 *PROMContent, bool AutoLoadFail
1690 )
1691 {
1692 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1693 struct TxPowerInfo24G pwrInfo24G;
1694 u8 rfPath, ch, TxCount = 1;
1695
1696 Hal_ReadPowerValueFromPROM_8723B(padapter, &pwrInfo24G, PROMContent, AutoLoadFail);
1697 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
1698 for (ch = 0 ; ch < CHANNEL_MAX_NUMBER; ch++) {
1699 u8 group = 0;
1700
1701 hal_get_chnl_group_8723b(ch + 1, &group);
1702
1703 if (ch == 14-1) {
1704 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][5];
1705 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group];
1706 } else {
1707 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group];
1708 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group];
1709 }
1710 }
1711
1712 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
1713 pHalData->CCK_24G_Diff[rfPath][TxCount] = pwrInfo24G.CCK_Diff[rfPath][TxCount];
1714 pHalData->OFDM_24G_Diff[rfPath][TxCount] = pwrInfo24G.OFDM_Diff[rfPath][TxCount];
1715 pHalData->BW20_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW20_Diff[rfPath][TxCount];
1716 pHalData->BW40_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW40_Diff[rfPath][TxCount];
1717 }
1718 }
1719
1720 /* 2010/10/19 MH Add Regulator recognize for CU. */
1721 if (!AutoLoadFail) {
1722 pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_8723B]&0x7); /* bit0~2 */
1723 if (PROMContent[EEPROM_RF_BOARD_OPTION_8723B] == 0xFF)
1724 pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7); /* bit0~2 */
1725 } else
1726 pHalData->EEPROMRegulatory = 0;
1727 }
1728
Hal_EfuseParseBTCoexistInfo_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1729 void Hal_EfuseParseBTCoexistInfo_8723B(
1730 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1731 )
1732 {
1733 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1734 u8 tempval;
1735 u32 tmpu4;
1736
1737 if (!AutoLoadFail) {
1738 tmpu4 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
1739 if (tmpu4 & BT_FUNC_EN)
1740 pHalData->EEPROMBluetoothCoexist = true;
1741 else
1742 pHalData->EEPROMBluetoothCoexist = false;
1743
1744 pHalData->EEPROMBluetoothType = BT_RTL8723B;
1745
1746 tempval = hwinfo[EEPROM_RF_BT_SETTING_8723B];
1747 if (tempval != 0xFF) {
1748 pHalData->EEPROMBluetoothAntNum = tempval & BIT(0);
1749 /* EFUSE_0xC3[6] == 0, S1(Main)-RF_PATH_A; */
1750 /* EFUSE_0xC3[6] == 1, S0(Aux)-RF_PATH_B */
1751 if (tempval & BIT(6))
1752 pHalData->ant_path = RF_PATH_B;
1753 else
1754 pHalData->ant_path = RF_PATH_A;
1755 } else {
1756 pHalData->EEPROMBluetoothAntNum = Ant_x1;
1757 if (pHalData->PackageType == PACKAGE_QFN68)
1758 pHalData->ant_path = RF_PATH_B;
1759 else
1760 pHalData->ant_path = RF_PATH_A;
1761 }
1762 } else {
1763 pHalData->EEPROMBluetoothCoexist = false;
1764 pHalData->EEPROMBluetoothType = BT_RTL8723B;
1765 pHalData->EEPROMBluetoothAntNum = Ant_x1;
1766 pHalData->ant_path = RF_PATH_A;
1767 }
1768
1769 if (padapter->registrypriv.ant_num > 0) {
1770 switch (padapter->registrypriv.ant_num) {
1771 case 1:
1772 pHalData->EEPROMBluetoothAntNum = Ant_x1;
1773 break;
1774 case 2:
1775 pHalData->EEPROMBluetoothAntNum = Ant_x2;
1776 break;
1777 default:
1778 break;
1779 }
1780 }
1781
1782 hal_btcoex_SetBTCoexist(padapter, pHalData->EEPROMBluetoothCoexist);
1783 hal_btcoex_SetPgAntNum(padapter, pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);
1784 if (pHalData->EEPROMBluetoothAntNum == Ant_x1)
1785 hal_btcoex_SetSingleAntPath(padapter, pHalData->ant_path);
1786 }
1787
Hal_EfuseParseEEPROMVer_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1788 void Hal_EfuseParseEEPROMVer_8723B(
1789 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1790 )
1791 {
1792 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1793
1794 if (!AutoLoadFail)
1795 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8723B];
1796 else
1797 pHalData->EEPROMVersion = 1;
1798 }
1799
1800
1801
Hal_EfuseParsePackageType_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1802 void Hal_EfuseParsePackageType_8723B(
1803 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1804 )
1805 {
1806 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1807 u8 package;
1808 u8 efuseContent;
1809
1810 Efuse_PowerSwitch(padapter, false, true);
1811 efuse_OneByteRead(padapter, 0x1FB, &efuseContent, false);
1812 Efuse_PowerSwitch(padapter, false, false);
1813
1814 package = efuseContent & 0x7;
1815 switch (package) {
1816 case 0x4:
1817 pHalData->PackageType = PACKAGE_TFBGA79;
1818 break;
1819 case 0x5:
1820 pHalData->PackageType = PACKAGE_TFBGA90;
1821 break;
1822 case 0x6:
1823 pHalData->PackageType = PACKAGE_QFN68;
1824 break;
1825 case 0x7:
1826 pHalData->PackageType = PACKAGE_TFBGA80;
1827 break;
1828
1829 default:
1830 pHalData->PackageType = PACKAGE_DEFAULT;
1831 break;
1832 }
1833 }
1834
1835
Hal_EfuseParseVoltage_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1836 void Hal_EfuseParseVoltage_8723B(
1837 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1838 )
1839 {
1840 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1841
1842 /* memcpy(pEEPROM->adjuseVoltageVal, &hwinfo[EEPROM_Voltage_ADDR_8723B], 1); */
1843 pEEPROM->adjuseVoltageVal = (hwinfo[EEPROM_Voltage_ADDR_8723B] & 0xf0) >> 4;
1844 }
1845
Hal_EfuseParseChnlPlan_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1846 void Hal_EfuseParseChnlPlan_8723B(
1847 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1848 )
1849 {
1850 padapter->mlmepriv.ChannelPlan = hal_com_config_channel_plan(
1851 padapter,
1852 hwinfo ? hwinfo[EEPROM_ChannelPlan_8723B] : 0xFF,
1853 padapter->registrypriv.channel_plan,
1854 RT_CHANNEL_DOMAIN_WORLD_NULL,
1855 AutoLoadFail
1856 );
1857
1858 Hal_ChannelPlanToRegulation(padapter, padapter->mlmepriv.ChannelPlan);
1859 }
1860
Hal_EfuseParseCustomerID_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1861 void Hal_EfuseParseCustomerID_8723B(
1862 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1863 )
1864 {
1865 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1866
1867 if (!AutoLoadFail)
1868 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8723B];
1869 else
1870 pHalData->EEPROMCustomerID = 0;
1871 }
1872
Hal_EfuseParseAntennaDiversity_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1873 void Hal_EfuseParseAntennaDiversity_8723B(
1874 struct adapter *padapter,
1875 u8 *hwinfo,
1876 bool AutoLoadFail
1877 )
1878 {
1879 }
1880
Hal_EfuseParseXtal_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1881 void Hal_EfuseParseXtal_8723B(
1882 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1883 )
1884 {
1885 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1886
1887 if (!AutoLoadFail) {
1888 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_8723B];
1889 if (pHalData->CrystalCap == 0xFF)
1890 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723B; /* what value should 8812 set? */
1891 } else
1892 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723B;
1893 }
1894
1895
Hal_EfuseParseThermalMeter_8723B(struct adapter * padapter,u8 * PROMContent,u8 AutoLoadFail)1896 void Hal_EfuseParseThermalMeter_8723B(
1897 struct adapter *padapter, u8 *PROMContent, u8 AutoLoadFail
1898 )
1899 {
1900 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1901
1902 /* */
1903 /* ThermalMeter from EEPROM */
1904 /* */
1905 if (!AutoLoadFail)
1906 pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_8723B];
1907 else
1908 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_8723B;
1909
1910 if ((pHalData->EEPROMThermalMeter == 0xff) || AutoLoadFail) {
1911 pHalData->bAPKThermalMeterIgnore = true;
1912 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_8723B;
1913 }
1914 }
1915
1916
Hal_ReadRFGainOffset(struct adapter * Adapter,u8 * PROMContent,bool AutoloadFail)1917 void Hal_ReadRFGainOffset(
1918 struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail
1919 )
1920 {
1921 /* */
1922 /* BB_RF Gain Offset from EEPROM */
1923 /* */
1924
1925 if (!AutoloadFail) {
1926 Adapter->eeprompriv.EEPROMRFGainOffset = PROMContent[EEPROM_RF_GAIN_OFFSET];
1927 Adapter->eeprompriv.EEPROMRFGainVal = EFUSE_Read1Byte(Adapter, EEPROM_RF_GAIN_VAL);
1928 } else {
1929 Adapter->eeprompriv.EEPROMRFGainOffset = 0;
1930 Adapter->eeprompriv.EEPROMRFGainVal = 0xFF;
1931 }
1932 }
1933
BWMapping_8723B(struct adapter * Adapter,struct pkt_attrib * pattrib)1934 u8 BWMapping_8723B(struct adapter *Adapter, struct pkt_attrib *pattrib)
1935 {
1936 u8 BWSettingOfDesc = 0;
1937 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1938
1939 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
1940 if (pattrib->bwmode == CHANNEL_WIDTH_40)
1941 BWSettingOfDesc = 1;
1942 else
1943 BWSettingOfDesc = 0;
1944 } else
1945 BWSettingOfDesc = 0;
1946
1947 /* if (pTcb->bBTTxPacket) */
1948 /* BWSettingOfDesc = 0; */
1949
1950 return BWSettingOfDesc;
1951 }
1952
SCMapping_8723B(struct adapter * Adapter,struct pkt_attrib * pattrib)1953 u8 SCMapping_8723B(struct adapter *Adapter, struct pkt_attrib *pattrib)
1954 {
1955 u8 SCSettingOfDesc = 0;
1956 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1957
1958 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
1959 if (pattrib->bwmode == CHANNEL_WIDTH_40) {
1960 SCSettingOfDesc = HT_DATA_SC_DONOT_CARE;
1961 } else if (pattrib->bwmode == CHANNEL_WIDTH_20) {
1962 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) {
1963 SCSettingOfDesc = HT_DATA_SC_20_UPPER_OF_40MHZ;
1964 } else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) {
1965 SCSettingOfDesc = HT_DATA_SC_20_LOWER_OF_40MHZ;
1966 } else {
1967 SCSettingOfDesc = HT_DATA_SC_DONOT_CARE;
1968 }
1969 }
1970 } else {
1971 SCSettingOfDesc = HT_DATA_SC_DONOT_CARE;
1972 }
1973
1974 return SCSettingOfDesc;
1975 }
1976
rtl8723b_cal_txdesc_chksum(struct tx_desc * ptxdesc)1977 static void rtl8723b_cal_txdesc_chksum(struct tx_desc *ptxdesc)
1978 {
1979 u16 *usPtr = (u16 *)ptxdesc;
1980 u32 count;
1981 u32 index;
1982 u16 checksum = 0;
1983
1984
1985 /* Clear first */
1986 ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
1987
1988 /* checksum is always calculated by first 32 bytes, */
1989 /* and it doesn't depend on TX DESC length. */
1990 /* Thomas, Lucas@SD4, 20130515 */
1991 count = 16;
1992
1993 for (index = 0; index < count; index++) {
1994 checksum |= le16_to_cpu(*(__le16 *)(usPtr + index));
1995 }
1996
1997 ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff);
1998 }
1999
fill_txdesc_sectype(struct pkt_attrib * pattrib)2000 static u8 fill_txdesc_sectype(struct pkt_attrib *pattrib)
2001 {
2002 u8 sectype = 0;
2003 if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
2004 switch (pattrib->encrypt) {
2005 /* SEC_TYPE */
2006 case _WEP40_:
2007 case _WEP104_:
2008 case _TKIP_:
2009 case _TKIP_WTMIC_:
2010 sectype = 1;
2011 break;
2012
2013 case _AES_:
2014 sectype = 3;
2015 break;
2016
2017 case _NO_PRIVACY_:
2018 default:
2019 break;
2020 }
2021 }
2022 return sectype;
2023 }
2024
fill_txdesc_vcs_8723b(struct adapter * padapter,struct pkt_attrib * pattrib,struct txdesc_8723b * ptxdesc)2025 static void fill_txdesc_vcs_8723b(struct adapter *padapter, struct pkt_attrib *pattrib, struct txdesc_8723b *ptxdesc)
2026 {
2027 if (pattrib->vcs_mode) {
2028 switch (pattrib->vcs_mode) {
2029 case RTS_CTS:
2030 ptxdesc->rtsen = 1;
2031 /* ENABLE HW RTS */
2032 ptxdesc->hw_rts_en = 1;
2033 break;
2034
2035 case CTS_TO_SELF:
2036 ptxdesc->cts2self = 1;
2037 break;
2038
2039 case NONE_VCS:
2040 default:
2041 break;
2042 }
2043
2044 ptxdesc->rtsrate = 8; /* RTS Rate =24M */
2045 ptxdesc->rts_ratefb_lmt = 0xF;
2046
2047 if (padapter->mlmeextpriv.mlmext_info.preamble_mode == PREAMBLE_SHORT)
2048 ptxdesc->rts_short = 1;
2049
2050 /* Set RTS BW */
2051 if (pattrib->ht_en)
2052 ptxdesc->rts_sc = SCMapping_8723B(padapter, pattrib);
2053 }
2054 }
2055
fill_txdesc_phy_8723b(struct adapter * padapter,struct pkt_attrib * pattrib,struct txdesc_8723b * ptxdesc)2056 static void fill_txdesc_phy_8723b(struct adapter *padapter, struct pkt_attrib *pattrib, struct txdesc_8723b *ptxdesc)
2057 {
2058 if (pattrib->ht_en) {
2059 ptxdesc->data_bw = BWMapping_8723B(padapter, pattrib);
2060
2061 ptxdesc->data_sc = SCMapping_8723B(padapter, pattrib);
2062 }
2063 }
2064
rtl8723b_fill_default_txdesc(struct xmit_frame * pxmitframe,u8 * pbuf)2065 static void rtl8723b_fill_default_txdesc(
2066 struct xmit_frame *pxmitframe, u8 *pbuf
2067 )
2068 {
2069 struct adapter *padapter;
2070 struct hal_com_data *pHalData;
2071 struct mlme_ext_priv *pmlmeext;
2072 struct mlme_ext_info *pmlmeinfo;
2073 struct pkt_attrib *pattrib;
2074 struct txdesc_8723b *ptxdesc;
2075 s32 bmcst;
2076
2077 memset(pbuf, 0, TXDESC_SIZE);
2078
2079 padapter = pxmitframe->padapter;
2080 pHalData = GET_HAL_DATA(padapter);
2081 pmlmeext = &padapter->mlmeextpriv;
2082 pmlmeinfo = &(pmlmeext->mlmext_info);
2083
2084 pattrib = &pxmitframe->attrib;
2085 bmcst = is_multicast_ether_addr(pattrib->ra);
2086
2087 ptxdesc = (struct txdesc_8723b *)pbuf;
2088
2089 if (pxmitframe->frame_tag == DATA_FRAMETAG) {
2090 u8 drv_userate = 0;
2091
2092 ptxdesc->macid = pattrib->mac_id; /* CAM_ID(MAC_ID) */
2093 ptxdesc->rate_id = pattrib->raid;
2094 ptxdesc->qsel = pattrib->qsel;
2095 ptxdesc->seq = pattrib->seqnum;
2096
2097 ptxdesc->sectype = fill_txdesc_sectype(pattrib);
2098 fill_txdesc_vcs_8723b(padapter, pattrib, ptxdesc);
2099
2100 if (pattrib->icmp_pkt == 1 && padapter->registrypriv.wifi_spec == 1)
2101 drv_userate = 1;
2102
2103 if (
2104 (pattrib->ether_type != 0x888e) &&
2105 (pattrib->ether_type != 0x0806) &&
2106 (pattrib->ether_type != 0x88B4) &&
2107 (pattrib->dhcp_pkt != 1) &&
2108 (drv_userate != 1)
2109 ) {
2110 /* Non EAP & ARP & DHCP type data packet */
2111
2112 if (pattrib->ampdu_en) {
2113 ptxdesc->agg_en = 1; /* AGG EN */
2114 ptxdesc->max_agg_num = 0x1f;
2115 ptxdesc->ampdu_density = pattrib->ampdu_spacing;
2116 } else
2117 ptxdesc->bk = 1; /* AGG BK */
2118
2119 fill_txdesc_phy_8723b(padapter, pattrib, ptxdesc);
2120
2121 ptxdesc->data_ratefb_lmt = 0x1F;
2122
2123 if (!pHalData->fw_ractrl) {
2124 ptxdesc->userate = 1;
2125
2126 if (pHalData->dmpriv.INIDATA_RATE[pattrib->mac_id] & BIT(7))
2127 ptxdesc->data_short = 1;
2128
2129 ptxdesc->datarate = pHalData->dmpriv.INIDATA_RATE[pattrib->mac_id] & 0x7F;
2130 }
2131
2132 if (padapter->fix_rate != 0xFF) { /* modify data rate by iwpriv */
2133 ptxdesc->userate = 1;
2134 if (padapter->fix_rate & BIT(7))
2135 ptxdesc->data_short = 1;
2136
2137 ptxdesc->datarate = (padapter->fix_rate & 0x7F);
2138 ptxdesc->disdatafb = 1;
2139 }
2140
2141 if (pattrib->ldpc)
2142 ptxdesc->data_ldpc = 1;
2143 if (pattrib->stbc)
2144 ptxdesc->data_stbc = 1;
2145 } else {
2146 /* EAP data packet and ARP packet. */
2147 /* Use the 1M data rate to send the EAP/ARP packet. */
2148 /* This will maybe make the handshake smooth. */
2149
2150 ptxdesc->bk = 1; /* AGG BK */
2151 ptxdesc->userate = 1; /* driver uses rate */
2152 if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
2153 ptxdesc->data_short = 1;/* DATA_SHORT */
2154 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
2155 }
2156
2157 ptxdesc->usb_txagg_num = pxmitframe->agg_num;
2158 } else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {
2159 ptxdesc->macid = pattrib->mac_id; /* CAM_ID(MAC_ID) */
2160 ptxdesc->qsel = pattrib->qsel;
2161 ptxdesc->rate_id = pattrib->raid; /* Rate ID */
2162 ptxdesc->seq = pattrib->seqnum;
2163 ptxdesc->userate = 1; /* driver uses rate, 1M */
2164
2165 ptxdesc->mbssid = pattrib->mbssid & 0xF;
2166
2167 ptxdesc->rty_lmt_en = 1; /* retry limit enable */
2168 if (pattrib->retry_ctrl) {
2169 ptxdesc->data_rt_lmt = 6;
2170 } else {
2171 ptxdesc->data_rt_lmt = 12;
2172 }
2173
2174 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
2175
2176 /* CCX-TXRPT ack for xmit mgmt frames. */
2177 if (pxmitframe->ack_report) {
2178 ptxdesc->spe_rpt = 1;
2179 ptxdesc->sw_define = (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no);
2180 }
2181 } else {
2182 ptxdesc->macid = pattrib->mac_id; /* CAM_ID(MAC_ID) */
2183 ptxdesc->rate_id = pattrib->raid; /* Rate ID */
2184 ptxdesc->qsel = pattrib->qsel;
2185 ptxdesc->seq = pattrib->seqnum;
2186 ptxdesc->userate = 1; /* driver uses rate */
2187 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
2188 }
2189
2190 ptxdesc->pktlen = pattrib->last_txcmdsz;
2191 ptxdesc->offset = TXDESC_SIZE + OFFSET_SZ;
2192
2193 if (bmcst)
2194 ptxdesc->bmc = 1;
2195
2196 /* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS.
2197 * (1) The sequence number of each non-Qos frame / broadcast /
2198 * multicast / mgnt frame should be controlled by Hw because Fw
2199 * will also send null data which we cannot control when Fw LPS
2200 * enable.
2201 * --> default enable non-Qos data sequence number. 2010.06.23.
2202 * by tynli.
2203 * (2) Enable HW SEQ control for beacon packet, because we use
2204 * Hw beacon.
2205 * (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos
2206 * packets.
2207 * 2010.06.23. Added by tynli.
2208 */
2209 if (!pattrib->qos_en) /* Hw set sequence number */
2210 ptxdesc->en_hwseq = 1; /* HWSEQ_EN */
2211 }
2212
2213 /* Description:
2214 *
2215 * Parameters:
2216 * pxmitframe xmitframe
2217 * pbuf where to fill tx desc
2218 */
rtl8723b_update_txdesc(struct xmit_frame * pxmitframe,u8 * pbuf)2219 void rtl8723b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
2220 {
2221 struct tx_desc *pdesc;
2222
2223 rtl8723b_fill_default_txdesc(pxmitframe, pbuf);
2224 pdesc = (struct tx_desc *)pbuf;
2225 rtl8723b_cal_txdesc_chksum(pdesc);
2226 }
2227
2228 /* */
2229 /* Description: In normal chip, we should send some packet to Hw which will be used by Fw */
2230 /* in FW LPS mode. The function is to fill the Tx descriptor of this packets, then */
2231 /* Fw can tell Hw to send these packet derectly. */
2232 /* Added by tynli. 2009.10.15. */
2233 /* */
2234 /* type1:pspoll, type2:null */
rtl8723b_fill_fake_txdesc(struct adapter * padapter,u8 * pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull,u8 bDataFrame)2235 void rtl8723b_fill_fake_txdesc(
2236 struct adapter *padapter,
2237 u8 *pDesc,
2238 u32 BufferLen,
2239 u8 IsPsPoll,
2240 u8 IsBTQosNull,
2241 u8 bDataFrame
2242 )
2243 {
2244 /* Clear all status */
2245 memset(pDesc, 0, TXDESC_SIZE);
2246
2247 SET_TX_DESC_FIRST_SEG_8723B(pDesc, 1); /* bFirstSeg; */
2248 SET_TX_DESC_LAST_SEG_8723B(pDesc, 1); /* bLastSeg; */
2249
2250 SET_TX_DESC_OFFSET_8723B(pDesc, 0x28); /* Offset = 32 */
2251
2252 SET_TX_DESC_PKT_SIZE_8723B(pDesc, BufferLen); /* Buffer size + command header */
2253 SET_TX_DESC_QUEUE_SEL_8723B(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */
2254
2255 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error value by Hw. */
2256 if (IsPsPoll) {
2257 SET_TX_DESC_NAV_USE_HDR_8723B(pDesc, 1);
2258 } else {
2259 SET_TX_DESC_HWSEQ_EN_8723B(pDesc, 1); /* Hw set sequence number */
2260 SET_TX_DESC_HWSEQ_SEL_8723B(pDesc, 0);
2261 }
2262
2263 if (IsBTQosNull) {
2264 SET_TX_DESC_BT_INT_8723B(pDesc, 1);
2265 }
2266
2267 SET_TX_DESC_USE_RATE_8723B(pDesc, 1); /* use data rate which is set by Sw */
2268 SET_TX_DESC_OWN_8723B((u8 *)pDesc, 1);
2269
2270 SET_TX_DESC_TX_RATE_8723B(pDesc, DESC8723B_RATE1M);
2271
2272 /* */
2273 /* Encrypt the data frame if under security mode excepct null data. Suggested by CCW. */
2274 /* */
2275 if (bDataFrame) {
2276 u32 EncAlg;
2277
2278 EncAlg = padapter->securitypriv.dot11PrivacyAlgrthm;
2279 switch (EncAlg) {
2280 case _NO_PRIVACY_:
2281 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x0);
2282 break;
2283 case _WEP40_:
2284 case _WEP104_:
2285 case _TKIP_:
2286 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x1);
2287 break;
2288 case _SMS4_:
2289 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x2);
2290 break;
2291 case _AES_:
2292 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x3);
2293 break;
2294 default:
2295 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x0);
2296 break;
2297 }
2298 }
2299
2300 /* USB interface drop packet if the checksum of descriptor isn't correct. */
2301 /* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */
2302 rtl8723b_cal_txdesc_chksum((struct tx_desc *)pDesc);
2303 }
2304
hw_var_set_opmode(struct adapter * padapter,u8 variable,u8 * val)2305 static void hw_var_set_opmode(struct adapter *padapter, u8 variable, u8 *val)
2306 {
2307 u8 val8;
2308 u8 mode = *((u8 *)val);
2309
2310 {
2311 /* disable Port0 TSF update */
2312 val8 = rtw_read8(padapter, REG_BCN_CTRL);
2313 val8 |= DIS_TSF_UDT;
2314 rtw_write8(padapter, REG_BCN_CTRL, val8);
2315
2316 /* set net_type */
2317 Set_MSR(padapter, mode);
2318
2319 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
2320 {
2321 StopTxBeacon(padapter);
2322 }
2323
2324 /* disable atim wnd */
2325 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|EN_BCN_FUNCTION|DIS_ATIM);
2326 /* rtw_write8(padapter, REG_BCN_CTRL, 0x18); */
2327 } else if (mode == _HW_STATE_ADHOC_) {
2328 ResumeTxBeacon(padapter);
2329 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|EN_BCN_FUNCTION|DIS_BCNQ_SUB);
2330 } else if (mode == _HW_STATE_AP_) {
2331
2332 ResumeTxBeacon(padapter);
2333
2334 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|DIS_BCNQ_SUB);
2335
2336 /* Set RCR */
2337 rtw_write32(padapter, REG_RCR, 0x7000208e);/* CBSSID_DATA must set to 0, reject ICV_ERR packet */
2338 /* enable to rx data frame */
2339 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
2340 /* enable to rx ps-poll */
2341 rtw_write16(padapter, REG_RXFLTMAP1, 0x0400);
2342
2343 /* Beacon Control related register for first time */
2344 rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms */
2345
2346 /* rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); */
2347 rtw_write8(padapter, REG_ATIMWND, 0x0a); /* 10ms */
2348 rtw_write16(padapter, REG_BCNTCFG, 0x00);
2349 rtw_write16(padapter, REG_TBTT_PROHIBIT, 0xff04);
2350 rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
2351
2352 /* reset TSF */
2353 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
2354
2355 /* enable BCN0 Function for if1 */
2356 /* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */
2357 rtw_write8(padapter, REG_BCN_CTRL, (DIS_TSF_UDT|EN_BCN_FUNCTION|EN_TXBCN_RPT|DIS_BCNQ_SUB));
2358
2359 /* SW_BCN_SEL - Port0 */
2360 /* rtw_write8(Adapter, REG_DWBCN1_CTRL_8192E+2, rtw_read8(Adapter, REG_DWBCN1_CTRL_8192E+2) & ~BIT4); */
2361 rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
2362
2363 /* select BCN on port 0 */
2364 rtw_write8(
2365 padapter,
2366 REG_CCK_CHECK_8723B,
2367 (rtw_read8(padapter, REG_CCK_CHECK_8723B)&~BIT_BCN_PORT_SEL)
2368 );
2369
2370 /* dis BCN1 ATIM WND if if2 is station */
2371 val8 = rtw_read8(padapter, REG_BCN_CTRL_1);
2372 val8 |= DIS_ATIM;
2373 rtw_write8(padapter, REG_BCN_CTRL_1, val8);
2374 }
2375 }
2376 }
2377
hw_var_set_macaddr(struct adapter * padapter,u8 variable,u8 * val)2378 static void hw_var_set_macaddr(struct adapter *padapter, u8 variable, u8 *val)
2379 {
2380 u8 idx = 0;
2381 u32 reg_macid;
2382
2383 reg_macid = REG_MACID;
2384
2385 for (idx = 0 ; idx < 6; idx++)
2386 rtw_write8(GET_PRIMARY_ADAPTER(padapter), (reg_macid+idx), val[idx]);
2387 }
2388
hw_var_set_bssid(struct adapter * padapter,u8 variable,u8 * val)2389 static void hw_var_set_bssid(struct adapter *padapter, u8 variable, u8 *val)
2390 {
2391 u8 idx = 0;
2392 u32 reg_bssid;
2393
2394 reg_bssid = REG_BSSID;
2395
2396 for (idx = 0 ; idx < 6; idx++)
2397 rtw_write8(padapter, (reg_bssid+idx), val[idx]);
2398 }
2399
hw_var_set_bcn_func(struct adapter * padapter,u8 variable,u8 * val)2400 static void hw_var_set_bcn_func(struct adapter *padapter, u8 variable, u8 *val)
2401 {
2402 u32 bcn_ctrl_reg;
2403
2404 bcn_ctrl_reg = REG_BCN_CTRL;
2405
2406 if (*(u8 *)val)
2407 rtw_write8(padapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
2408 else {
2409 u8 val8;
2410 val8 = rtw_read8(padapter, bcn_ctrl_reg);
2411 val8 &= ~(EN_BCN_FUNCTION | EN_TXBCN_RPT);
2412
2413 /* Always enable port0 beacon function for PSTDMA */
2414 if (REG_BCN_CTRL == bcn_ctrl_reg)
2415 val8 |= EN_BCN_FUNCTION;
2416
2417 rtw_write8(padapter, bcn_ctrl_reg, val8);
2418 }
2419 }
2420
hw_var_set_correct_tsf(struct adapter * padapter,u8 variable,u8 * val)2421 static void hw_var_set_correct_tsf(struct adapter *padapter, u8 variable, u8 *val)
2422 {
2423 u8 val8;
2424 u64 tsf;
2425 struct mlme_ext_priv *pmlmeext;
2426 struct mlme_ext_info *pmlmeinfo;
2427
2428
2429 pmlmeext = &padapter->mlmeextpriv;
2430 pmlmeinfo = &pmlmeext->mlmext_info;
2431
2432 tsf = pmlmeext->TSFValue-do_div(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024))-1024; /* us */
2433
2434 if (
2435 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ||
2436 ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
2437 )
2438 StopTxBeacon(padapter);
2439
2440 {
2441 /* disable related TSF function */
2442 val8 = rtw_read8(padapter, REG_BCN_CTRL);
2443 val8 &= ~EN_BCN_FUNCTION;
2444 rtw_write8(padapter, REG_BCN_CTRL, val8);
2445
2446 rtw_write32(padapter, REG_TSFTR, tsf);
2447 rtw_write32(padapter, REG_TSFTR+4, tsf>>32);
2448
2449 /* enable related TSF function */
2450 val8 = rtw_read8(padapter, REG_BCN_CTRL);
2451 val8 |= EN_BCN_FUNCTION;
2452 rtw_write8(padapter, REG_BCN_CTRL, val8);
2453 }
2454
2455 if (
2456 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ||
2457 ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
2458 )
2459 ResumeTxBeacon(padapter);
2460 }
2461
hw_var_set_mlme_disconnect(struct adapter * padapter,u8 variable,u8 * val)2462 static void hw_var_set_mlme_disconnect(struct adapter *padapter, u8 variable, u8 *val)
2463 {
2464 u8 val8;
2465
2466 /* Set RCR to not to receive data frame when NO LINK state */
2467 /* rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF); */
2468 /* reject all data frames */
2469 rtw_write16(padapter, REG_RXFLTMAP2, 0);
2470
2471 /* reset TSF */
2472 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
2473
2474 /* disable update TSF */
2475 val8 = rtw_read8(padapter, REG_BCN_CTRL);
2476 val8 |= DIS_TSF_UDT;
2477 rtw_write8(padapter, REG_BCN_CTRL, val8);
2478 }
2479
hw_var_set_mlme_sitesurvey(struct adapter * padapter,u8 variable,u8 * val)2480 static void hw_var_set_mlme_sitesurvey(struct adapter *padapter, u8 variable, u8 *val)
2481 {
2482 u32 value_rcr, rcr_clear_bit, reg_bcn_ctl;
2483 u16 value_rxfltmap2;
2484 u8 val8;
2485 struct hal_com_data *pHalData;
2486 struct mlme_priv *pmlmepriv;
2487
2488
2489 pHalData = GET_HAL_DATA(padapter);
2490 pmlmepriv = &padapter->mlmepriv;
2491
2492 reg_bcn_ctl = REG_BCN_CTRL;
2493
2494 rcr_clear_bit = RCR_CBSSID_BCN;
2495
2496 /* config RCR to receive different BSSID & not to receive data frame */
2497 value_rxfltmap2 = 0;
2498
2499 if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == true))
2500 rcr_clear_bit = RCR_CBSSID_BCN;
2501
2502 value_rcr = rtw_read32(padapter, REG_RCR);
2503
2504 if (*((u8 *)val)) {
2505 /* under sitesurvey */
2506 value_rcr &= ~(rcr_clear_bit);
2507 rtw_write32(padapter, REG_RCR, value_rcr);
2508
2509 rtw_write16(padapter, REG_RXFLTMAP2, value_rxfltmap2);
2510
2511 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
2512 /* disable update TSF */
2513 val8 = rtw_read8(padapter, reg_bcn_ctl);
2514 val8 |= DIS_TSF_UDT;
2515 rtw_write8(padapter, reg_bcn_ctl, val8);
2516 }
2517
2518 /* Save original RRSR setting. */
2519 pHalData->RegRRSR = rtw_read16(padapter, REG_RRSR);
2520 } else {
2521 /* sitesurvey done */
2522 if (check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)))
2523 /* enable to rx data frame */
2524 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
2525
2526 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
2527 /* enable update TSF */
2528 val8 = rtw_read8(padapter, reg_bcn_ctl);
2529 val8 &= ~DIS_TSF_UDT;
2530 rtw_write8(padapter, reg_bcn_ctl, val8);
2531 }
2532
2533 value_rcr |= rcr_clear_bit;
2534 rtw_write32(padapter, REG_RCR, value_rcr);
2535
2536 /* Restore original RRSR setting. */
2537 rtw_write16(padapter, REG_RRSR, pHalData->RegRRSR);
2538 }
2539 }
2540
hw_var_set_mlme_join(struct adapter * padapter,u8 variable,u8 * val)2541 static void hw_var_set_mlme_join(struct adapter *padapter, u8 variable, u8 *val)
2542 {
2543 u8 val8;
2544 u16 val16;
2545 u32 val32;
2546 u8 RetryLimit;
2547 u8 type;
2548 struct mlme_priv *pmlmepriv;
2549 struct eeprom_priv *pEEPROM;
2550
2551
2552 RetryLimit = 0x30;
2553 type = *(u8 *)val;
2554 pmlmepriv = &padapter->mlmepriv;
2555 pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2556
2557 if (type == 0) { /* prepare to join */
2558 /* enable to rx data frame.Accept all data frame */
2559 /* rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); */
2560 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
2561
2562 val32 = rtw_read32(padapter, REG_RCR);
2563 if (padapter->in_cta_test)
2564 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/* RCR_ADF */
2565 else
2566 val32 |= RCR_CBSSID_DATA|RCR_CBSSID_BCN;
2567 rtw_write32(padapter, REG_RCR, val32);
2568
2569 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == true)
2570 RetryLimit = (pEEPROM->CustomerID == RT_CID_CCX) ? 7 : 48;
2571 else /* Ad-hoc Mode */
2572 RetryLimit = 0x7;
2573 } else if (type == 1) /* joinbss_event call back when join res < 0 */
2574 rtw_write16(padapter, REG_RXFLTMAP2, 0x00);
2575 else if (type == 2) { /* sta add event call back */
2576 /* enable update TSF */
2577 val8 = rtw_read8(padapter, REG_BCN_CTRL);
2578 val8 &= ~DIS_TSF_UDT;
2579 rtw_write8(padapter, REG_BCN_CTRL, val8);
2580
2581 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
2582 RetryLimit = 0x7;
2583 }
2584
2585 val16 = (RetryLimit << RETRY_LIMIT_SHORT_SHIFT) | (RetryLimit << RETRY_LIMIT_LONG_SHIFT);
2586 rtw_write16(padapter, REG_RL, val16);
2587 }
2588
CCX_FwC2HTxRpt_8723b(struct adapter * padapter,u8 * pdata,u8 len)2589 void CCX_FwC2HTxRpt_8723b(struct adapter *padapter, u8 *pdata, u8 len)
2590 {
2591
2592 #define GET_8723B_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
2593 #define GET_8723B_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
2594
2595 if (GET_8723B_C2H_TX_RPT_RETRY_OVER(pdata) | GET_8723B_C2H_TX_RPT_LIFE_TIME_OVER(pdata)) {
2596 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
2597 }
2598 /*
2599 else if (seq_no != padapter->xmitpriv.seq_no) {
2600 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
2601 }
2602 */
2603 else
2604 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
2605 }
2606
c2h_id_filter_ccx_8723b(u8 * buf)2607 s32 c2h_id_filter_ccx_8723b(u8 *buf)
2608 {
2609 struct c2h_evt_hdr_88xx *c2h_evt = (struct c2h_evt_hdr_88xx *)buf;
2610 s32 ret = false;
2611 if (c2h_evt->id == C2H_CCX_TX_RPT)
2612 ret = true;
2613
2614 return ret;
2615 }
2616
2617
c2h_handler_8723b(struct adapter * padapter,u8 * buf)2618 s32 c2h_handler_8723b(struct adapter *padapter, u8 *buf)
2619 {
2620 struct c2h_evt_hdr_88xx *pC2hEvent = (struct c2h_evt_hdr_88xx *)buf;
2621 s32 ret = _SUCCESS;
2622
2623 if (!pC2hEvent) {
2624 ret = _FAIL;
2625 goto exit;
2626 }
2627
2628 switch (pC2hEvent->id) {
2629 case C2H_AP_RPT_RSP:
2630 break;
2631 case C2H_DBG:
2632 {
2633 }
2634 break;
2635
2636 case C2H_CCX_TX_RPT:
2637 /* CCX_FwC2HTxRpt(padapter, QueueID, pC2hEvent->payload); */
2638 break;
2639
2640 case C2H_EXT_RA_RPT:
2641 /* C2HExtRaRptHandler(padapter, pC2hEvent->payload, C2hEvent.CmdLen); */
2642 break;
2643
2644 case C2H_HW_INFO_EXCH:
2645 break;
2646
2647 case C2H_8723B_BT_INFO:
2648 hal_btcoex_BtInfoNotify(padapter, pC2hEvent->plen, pC2hEvent->payload);
2649 break;
2650
2651 default:
2652 break;
2653 }
2654
2655 /* Clear event to notify FW we have read the command. */
2656 /* Note: */
2657 /* If this field isn't clear, the FW won't update the next command message. */
2658 /* rtw_write8(padapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE); */
2659 exit:
2660 return ret;
2661 }
2662
process_c2h_event(struct adapter * padapter,struct c2h_evt_hdr_t * pC2hEvent,u8 * c2hBuf)2663 static void process_c2h_event(struct adapter *padapter, struct c2h_evt_hdr_t *pC2hEvent, u8 *c2hBuf)
2664 {
2665 if (!c2hBuf)
2666 return;
2667
2668 switch (pC2hEvent->CmdID) {
2669 case C2H_AP_RPT_RSP:
2670 break;
2671 case C2H_DBG:
2672 {
2673 }
2674 break;
2675
2676 case C2H_CCX_TX_RPT:
2677 /* CCX_FwC2HTxRpt(padapter, QueueID, tmpBuf); */
2678 break;
2679
2680 case C2H_EXT_RA_RPT:
2681 /* C2HExtRaRptHandler(padapter, tmpBuf, C2hEvent.CmdLen); */
2682 break;
2683
2684 case C2H_HW_INFO_EXCH:
2685 break;
2686
2687 case C2H_8723B_BT_INFO:
2688 hal_btcoex_BtInfoNotify(padapter, pC2hEvent->CmdLen, c2hBuf);
2689 break;
2690
2691 default:
2692 break;
2693 }
2694 }
2695
C2HPacketHandler_8723B(struct adapter * padapter,u8 * pbuffer,u16 length)2696 void C2HPacketHandler_8723B(struct adapter *padapter, u8 *pbuffer, u16 length)
2697 {
2698 struct c2h_evt_hdr_t C2hEvent;
2699 u8 *tmpBuf = NULL;
2700 C2hEvent.CmdID = pbuffer[0];
2701 C2hEvent.CmdSeq = pbuffer[1];
2702 C2hEvent.CmdLen = length-2;
2703 tmpBuf = pbuffer+2;
2704
2705 process_c2h_event(padapter, &C2hEvent, tmpBuf);
2706 /* c2h_handler_8723b(padapter,&C2hEvent); */
2707 }
2708
SetHwReg8723B(struct adapter * padapter,u8 variable,u8 * val)2709 void SetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val)
2710 {
2711 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2712 u8 val8;
2713 u32 val32;
2714
2715 switch (variable) {
2716 case HW_VAR_MEDIA_STATUS:
2717 val8 = rtw_read8(padapter, MSR) & 0x0c;
2718 val8 |= *val;
2719 rtw_write8(padapter, MSR, val8);
2720 break;
2721
2722 case HW_VAR_MEDIA_STATUS1:
2723 val8 = rtw_read8(padapter, MSR) & 0x03;
2724 val8 |= *val << 2;
2725 rtw_write8(padapter, MSR, val8);
2726 break;
2727
2728 case HW_VAR_SET_OPMODE:
2729 hw_var_set_opmode(padapter, variable, val);
2730 break;
2731
2732 case HW_VAR_MAC_ADDR:
2733 hw_var_set_macaddr(padapter, variable, val);
2734 break;
2735
2736 case HW_VAR_BSSID:
2737 hw_var_set_bssid(padapter, variable, val);
2738 break;
2739
2740 case HW_VAR_BASIC_RATE:
2741 {
2742 struct mlme_ext_info *mlmext_info = &padapter->mlmeextpriv.mlmext_info;
2743 u16 BrateCfg = 0;
2744 u16 rrsr_2g_force_mask = (RRSR_11M|RRSR_5_5M|RRSR_1M);
2745 u16 rrsr_2g_allow_mask = (RRSR_24M|RRSR_12M|RRSR_6M|RRSR_CCK_RATES);
2746
2747 HalSetBrateCfg(padapter, val, &BrateCfg);
2748
2749 /* apply force and allow mask */
2750 BrateCfg |= rrsr_2g_force_mask;
2751 BrateCfg &= rrsr_2g_allow_mask;
2752
2753 /* IOT consideration */
2754 if (mlmext_info->assoc_AP_vendor == HT_IOT_PEER_CISCO) {
2755 /* if peer is cisco and didn't use ofdm rate, we enable 6M ack */
2756 if ((BrateCfg & (RRSR_24M|RRSR_12M|RRSR_6M)) == 0)
2757 BrateCfg |= RRSR_6M;
2758 }
2759
2760 pHalData->BasicRateSet = BrateCfg;
2761
2762 /* Set RRSR rate table. */
2763 rtw_write16(padapter, REG_RRSR, BrateCfg);
2764 rtw_write8(padapter, REG_RRSR+2, rtw_read8(padapter, REG_RRSR+2)&0xf0);
2765 }
2766 break;
2767
2768 case HW_VAR_TXPAUSE:
2769 rtw_write8(padapter, REG_TXPAUSE, *val);
2770 break;
2771
2772 case HW_VAR_BCN_FUNC:
2773 hw_var_set_bcn_func(padapter, variable, val);
2774 break;
2775
2776 case HW_VAR_CORRECT_TSF:
2777 hw_var_set_correct_tsf(padapter, variable, val);
2778 break;
2779
2780 case HW_VAR_CHECK_BSSID:
2781 {
2782 u32 val32;
2783 val32 = rtw_read32(padapter, REG_RCR);
2784 if (*val)
2785 val32 |= RCR_CBSSID_DATA|RCR_CBSSID_BCN;
2786 else
2787 val32 &= ~(RCR_CBSSID_DATA|RCR_CBSSID_BCN);
2788 rtw_write32(padapter, REG_RCR, val32);
2789 }
2790 break;
2791
2792 case HW_VAR_MLME_DISCONNECT:
2793 hw_var_set_mlme_disconnect(padapter, variable, val);
2794 break;
2795
2796 case HW_VAR_MLME_SITESURVEY:
2797 hw_var_set_mlme_sitesurvey(padapter, variable, val);
2798
2799 hal_btcoex_ScanNotify(padapter, *val?true:false);
2800 break;
2801
2802 case HW_VAR_MLME_JOIN:
2803 hw_var_set_mlme_join(padapter, variable, val);
2804
2805 switch (*val) {
2806 case 0:
2807 /* prepare to join */
2808 hal_btcoex_ConnectNotify(padapter, true);
2809 break;
2810 case 1:
2811 /* joinbss_event callback when join res < 0 */
2812 hal_btcoex_ConnectNotify(padapter, false);
2813 break;
2814 case 2:
2815 /* sta add event callback */
2816 /* rtw_btcoex_MediaStatusNotify(padapter, RT_MEDIA_CONNECT); */
2817 break;
2818 }
2819 break;
2820
2821 case HW_VAR_ON_RCR_AM:
2822 val32 = rtw_read32(padapter, REG_RCR);
2823 val32 |= RCR_AM;
2824 rtw_write32(padapter, REG_RCR, val32);
2825 break;
2826
2827 case HW_VAR_OFF_RCR_AM:
2828 val32 = rtw_read32(padapter, REG_RCR);
2829 val32 &= ~RCR_AM;
2830 rtw_write32(padapter, REG_RCR, val32);
2831 break;
2832
2833 case HW_VAR_BEACON_INTERVAL:
2834 rtw_write16(padapter, REG_BCN_INTERVAL, *((u16 *)val));
2835 break;
2836
2837 case HW_VAR_SLOT_TIME:
2838 rtw_write8(padapter, REG_SLOT, *val);
2839 break;
2840
2841 case HW_VAR_RESP_SIFS:
2842 /* SIFS_Timer = 0x0a0a0808; */
2843 /* RESP_SIFS for CCK */
2844 rtw_write8(padapter, REG_RESP_SIFS_CCK, val[0]); /* SIFS_T2T_CCK (0x08) */
2845 rtw_write8(padapter, REG_RESP_SIFS_CCK+1, val[1]); /* SIFS_R2T_CCK(0x08) */
2846 /* RESP_SIFS for OFDM */
2847 rtw_write8(padapter, REG_RESP_SIFS_OFDM, val[2]); /* SIFS_T2T_OFDM (0x0a) */
2848 rtw_write8(padapter, REG_RESP_SIFS_OFDM+1, val[3]); /* SIFS_R2T_OFDM(0x0a) */
2849 break;
2850
2851 case HW_VAR_ACK_PREAMBLE:
2852 {
2853 u8 regTmp;
2854 u8 bShortPreamble = *val;
2855
2856 /* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
2857 /* regTmp = (pHalData->nCur40MhzPrimeSC)<<5; */
2858 regTmp = 0;
2859 if (bShortPreamble)
2860 regTmp |= 0x80;
2861 rtw_write8(padapter, REG_RRSR+2, regTmp);
2862 }
2863 break;
2864
2865 case HW_VAR_CAM_EMPTY_ENTRY:
2866 {
2867 u8 ucIndex = *val;
2868 u8 i;
2869 u32 ulCommand = 0;
2870 u32 ulContent = 0;
2871 u32 ulEncAlgo = CAM_AES;
2872
2873 for (i = 0; i < CAM_CONTENT_COUNT; i++) {
2874 /* filled id in CAM config 2 byte */
2875 if (i == 0) {
2876 ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
2877 /* ulContent |= CAM_VALID; */
2878 } else
2879 ulContent = 0;
2880
2881 /* polling bit, and No Write enable, and address */
2882 ulCommand = CAM_CONTENT_COUNT*ucIndex+i;
2883 ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE;
2884 /* write content 0 is equal to mark as invalid */
2885 rtw_write32(padapter, WCAMI, ulContent); /* mdelay(40); */
2886 rtw_write32(padapter, RWCAM, ulCommand); /* mdelay(40); */
2887 }
2888 }
2889 break;
2890
2891 case HW_VAR_CAM_INVALID_ALL:
2892 rtw_write32(padapter, RWCAM, BIT(31)|BIT(30));
2893 break;
2894
2895 case HW_VAR_CAM_WRITE:
2896 {
2897 u32 cmd;
2898 u32 *cam_val = (u32 *)val;
2899
2900 rtw_write32(padapter, WCAMI, cam_val[0]);
2901
2902 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
2903 rtw_write32(padapter, RWCAM, cmd);
2904 }
2905 break;
2906
2907 case HW_VAR_AC_PARAM_VO:
2908 rtw_write32(padapter, REG_EDCA_VO_PARAM, *((u32 *)val));
2909 break;
2910
2911 case HW_VAR_AC_PARAM_VI:
2912 rtw_write32(padapter, REG_EDCA_VI_PARAM, *((u32 *)val));
2913 break;
2914
2915 case HW_VAR_AC_PARAM_BE:
2916 pHalData->AcParam_BE = ((u32 *)(val))[0];
2917 rtw_write32(padapter, REG_EDCA_BE_PARAM, *((u32 *)val));
2918 break;
2919
2920 case HW_VAR_AC_PARAM_BK:
2921 rtw_write32(padapter, REG_EDCA_BK_PARAM, *((u32 *)val));
2922 break;
2923
2924 case HW_VAR_ACM_CTRL:
2925 {
2926 u8 ctrl = *((u8 *)val);
2927 u8 hwctrl = 0;
2928
2929 if (ctrl != 0) {
2930 hwctrl |= AcmHw_HwEn;
2931
2932 if (ctrl & BIT(1)) /* BE */
2933 hwctrl |= AcmHw_BeqEn;
2934
2935 if (ctrl & BIT(2)) /* VI */
2936 hwctrl |= AcmHw_ViqEn;
2937
2938 if (ctrl & BIT(3)) /* VO */
2939 hwctrl |= AcmHw_VoqEn;
2940 }
2941
2942 rtw_write8(padapter, REG_ACMHWCTRL, hwctrl);
2943 }
2944 break;
2945
2946 case HW_VAR_AMPDU_FACTOR:
2947 {
2948 u32 AMPDULen = (*((u8 *)val));
2949
2950 if (AMPDULen < HT_AGG_SIZE_32K)
2951 AMPDULen = (0x2000 << (*((u8 *)val)))-1;
2952 else
2953 AMPDULen = 0x7fff;
2954
2955 rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8723B, AMPDULen);
2956 }
2957 break;
2958
2959 case HW_VAR_H2C_FW_PWRMODE:
2960 {
2961 u8 psmode = *val;
2962
2963 /* Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power */
2964 /* saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. */
2965 if (psmode != PS_MODE_ACTIVE) {
2966 ODM_RF_Saving(&pHalData->odmpriv, true);
2967 }
2968
2969 /* if (psmode != PS_MODE_ACTIVE) { */
2970 /* rtl8723b_set_lowpwr_lps_cmd(padapter, true); */
2971 /* else { */
2972 /* rtl8723b_set_lowpwr_lps_cmd(padapter, false); */
2973 /* */
2974 rtl8723b_set_FwPwrMode_cmd(padapter, psmode);
2975 }
2976 break;
2977 case HW_VAR_H2C_PS_TUNE_PARAM:
2978 rtl8723b_set_FwPsTuneParam_cmd(padapter);
2979 break;
2980
2981 case HW_VAR_H2C_FW_JOINBSSRPT:
2982 rtl8723b_set_FwJoinBssRpt_cmd(padapter, *val);
2983 break;
2984
2985 case HW_VAR_INITIAL_GAIN:
2986 {
2987 struct dig_t *pDigTable = &pHalData->odmpriv.DM_DigTable;
2988 u32 rx_gain = *(u32 *)val;
2989
2990 if (rx_gain == 0xff) {/* restore rx gain */
2991 ODM_Write_DIG(&pHalData->odmpriv, pDigTable->BackupIGValue);
2992 } else {
2993 pDigTable->BackupIGValue = pDigTable->CurIGValue;
2994 ODM_Write_DIG(&pHalData->odmpriv, rx_gain);
2995 }
2996 }
2997 break;
2998
2999 case HW_VAR_EFUSE_USAGE:
3000 pHalData->EfuseUsedPercentage = *val;
3001 break;
3002
3003 case HW_VAR_EFUSE_BYTES:
3004 pHalData->EfuseUsedBytes = *((u16 *)val);
3005 break;
3006
3007 case HW_VAR_EFUSE_BT_USAGE:
3008 #ifdef HAL_EFUSE_MEMORY
3009 pHalData->EfuseHal.BTEfuseUsedPercentage = *val;
3010 #endif
3011 break;
3012
3013 case HW_VAR_EFUSE_BT_BYTES:
3014 #ifdef HAL_EFUSE_MEMORY
3015 pHalData->EfuseHal.BTEfuseUsedBytes = *((u16 *)val);
3016 #else
3017 BTEfuseUsedBytes = *((u16 *)val);
3018 #endif
3019 break;
3020
3021 case HW_VAR_FIFO_CLEARN_UP:
3022 {
3023 #define RW_RELEASE_EN BIT(18)
3024 #define RXDMA_IDLE BIT(17)
3025
3026 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
3027 u8 trycnt = 100;
3028
3029 /* pause tx */
3030 rtw_write8(padapter, REG_TXPAUSE, 0xff);
3031
3032 /* keep sn */
3033 padapter->xmitpriv.nqos_ssn = rtw_read16(padapter, REG_NQOS_SEQ);
3034
3035 if (!pwrpriv->bkeepfwalive) {
3036 /* RX DMA stop */
3037 val32 = rtw_read32(padapter, REG_RXPKT_NUM);
3038 val32 |= RW_RELEASE_EN;
3039 rtw_write32(padapter, REG_RXPKT_NUM, val32);
3040 do {
3041 val32 = rtw_read32(padapter, REG_RXPKT_NUM);
3042 val32 &= RXDMA_IDLE;
3043 if (val32)
3044 break;
3045 } while (--trycnt);
3046
3047 /* RQPN Load 0 */
3048 rtw_write16(padapter, REG_RQPN_NPQ, 0);
3049 rtw_write32(padapter, REG_RQPN, 0x80000000);
3050 mdelay(2);
3051 }
3052 }
3053 break;
3054
3055 case HW_VAR_APFM_ON_MAC:
3056 pHalData->bMacPwrCtrlOn = *val;
3057 break;
3058
3059 case HW_VAR_NAV_UPPER:
3060 {
3061 u32 usNavUpper = *((u32 *)val);
3062
3063 if (usNavUpper > HAL_NAV_UPPER_UNIT_8723B * 0xFF)
3064 break;
3065
3066 usNavUpper = DIV_ROUND_UP(usNavUpper,
3067 HAL_NAV_UPPER_UNIT_8723B);
3068 rtw_write8(padapter, REG_NAV_UPPER, (u8)usNavUpper);
3069 }
3070 break;
3071
3072 case HW_VAR_H2C_MEDIA_STATUS_RPT:
3073 {
3074 u16 mstatus_rpt = (*(u16 *)val);
3075 u8 mstatus, macId;
3076
3077 mstatus = (u8) (mstatus_rpt & 0xFF);
3078 macId = (u8)(mstatus_rpt >> 8);
3079 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, mstatus, macId);
3080 }
3081 break;
3082 case HW_VAR_BCN_VALID:
3083 {
3084 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */
3085 val8 = rtw_read8(padapter, REG_TDECTRL+2);
3086 val8 |= BIT(0);
3087 rtw_write8(padapter, REG_TDECTRL+2, val8);
3088 }
3089 break;
3090
3091 case HW_VAR_DL_BCN_SEL:
3092 {
3093 /* SW_BCN_SEL - Port0 */
3094 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723B+2);
3095 val8 &= ~BIT(4);
3096 rtw_write8(padapter, REG_DWBCN1_CTRL_8723B+2, val8);
3097 }
3098 break;
3099
3100 case HW_VAR_DO_IQK:
3101 pHalData->bNeedIQK = true;
3102 break;
3103
3104 case HW_VAR_DL_RSVD_PAGE:
3105 if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == true)
3106 rtl8723b_download_BTCoex_AP_mode_rsvd_page(padapter);
3107 else
3108 rtl8723b_download_rsvd_page(padapter, RT_MEDIA_CONNECT);
3109 break;
3110
3111 case HW_VAR_MACID_SLEEP:
3112 /* Input is MACID */
3113 val32 = *(u32 *)val;
3114 if (val32 > 31)
3115 break;
3116
3117 val8 = (u8)val32; /* macid is between 0~31 */
3118
3119 val32 = rtw_read32(padapter, REG_MACID_SLEEP);
3120 if (val32 & BIT(val8))
3121 break;
3122 val32 |= BIT(val8);
3123 rtw_write32(padapter, REG_MACID_SLEEP, val32);
3124 break;
3125
3126 case HW_VAR_MACID_WAKEUP:
3127 /* Input is MACID */
3128 val32 = *(u32 *)val;
3129 if (val32 > 31)
3130 break;
3131
3132 val8 = (u8)val32; /* macid is between 0~31 */
3133
3134 val32 = rtw_read32(padapter, REG_MACID_SLEEP);
3135 if (!(val32 & BIT(val8)))
3136 break;
3137 val32 &= ~BIT(val8);
3138 rtw_write32(padapter, REG_MACID_SLEEP, val32);
3139 break;
3140
3141 default:
3142 SetHwReg(padapter, variable, val);
3143 break;
3144 }
3145 }
3146
GetHwReg8723B(struct adapter * padapter,u8 variable,u8 * val)3147 void GetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val)
3148 {
3149 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
3150 u8 val8;
3151 u16 val16;
3152
3153 switch (variable) {
3154 case HW_VAR_TXPAUSE:
3155 *val = rtw_read8(padapter, REG_TXPAUSE);
3156 break;
3157
3158 case HW_VAR_BCN_VALID:
3159 {
3160 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */
3161 val8 = rtw_read8(padapter, REG_TDECTRL+2);
3162 *val = (BIT(0) & val8) ? true : false;
3163 }
3164 break;
3165
3166 case HW_VAR_FWLPS_RF_ON:
3167 {
3168 /* When we halt NIC, we should check if FW LPS is leave. */
3169 u32 valRCR;
3170
3171 if (
3172 padapter->bSurpriseRemoved ||
3173 (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off)
3174 ) {
3175 /* If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, */
3176 /* because Fw is unload. */
3177 *val = true;
3178 } else {
3179 valRCR = rtw_read32(padapter, REG_RCR);
3180 valRCR &= 0x00070000;
3181 if (valRCR)
3182 *val = false;
3183 else
3184 *val = true;
3185 }
3186 }
3187 break;
3188
3189 case HW_VAR_EFUSE_USAGE:
3190 *val = pHalData->EfuseUsedPercentage;
3191 break;
3192
3193 case HW_VAR_EFUSE_BYTES:
3194 *((u16 *)val) = pHalData->EfuseUsedBytes;
3195 break;
3196
3197 case HW_VAR_EFUSE_BT_USAGE:
3198 #ifdef HAL_EFUSE_MEMORY
3199 *val = pHalData->EfuseHal.BTEfuseUsedPercentage;
3200 #endif
3201 break;
3202
3203 case HW_VAR_EFUSE_BT_BYTES:
3204 #ifdef HAL_EFUSE_MEMORY
3205 *((u16 *)val) = pHalData->EfuseHal.BTEfuseUsedBytes;
3206 #else
3207 *((u16 *)val) = BTEfuseUsedBytes;
3208 #endif
3209 break;
3210
3211 case HW_VAR_APFM_ON_MAC:
3212 *val = pHalData->bMacPwrCtrlOn;
3213 break;
3214 case HW_VAR_CHK_HI_QUEUE_EMPTY:
3215 val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
3216 *val = (val16 & BIT(10)) ? true:false;
3217 break;
3218 default:
3219 GetHwReg(padapter, variable, val);
3220 break;
3221 }
3222 }
3223
3224 /* Description:
3225 * Change default setting of specified variable.
3226 */
SetHalDefVar8723B(struct adapter * padapter,enum hal_def_variable variable,void * pval)3227 u8 SetHalDefVar8723B(struct adapter *padapter, enum hal_def_variable variable, void *pval)
3228 {
3229 u8 bResult;
3230
3231 bResult = _SUCCESS;
3232
3233 switch (variable) {
3234 default:
3235 bResult = SetHalDefVar(padapter, variable, pval);
3236 break;
3237 }
3238
3239 return bResult;
3240 }
3241
3242 /* Description:
3243 * Query setting of specified variable.
3244 */
GetHalDefVar8723B(struct adapter * padapter,enum hal_def_variable variable,void * pval)3245 u8 GetHalDefVar8723B(struct adapter *padapter, enum hal_def_variable variable, void *pval)
3246 {
3247 u8 bResult;
3248
3249 bResult = _SUCCESS;
3250
3251 switch (variable) {
3252 case HAL_DEF_MAX_RECVBUF_SZ:
3253 *((u32 *)pval) = MAX_RECVBUF_SZ;
3254 break;
3255
3256 case HAL_DEF_RX_PACKET_OFFSET:
3257 *((u32 *)pval) = RXDESC_SIZE + DRVINFO_SZ*8;
3258 break;
3259
3260 case HW_VAR_MAX_RX_AMPDU_FACTOR:
3261 /* [email protected] suggests 16K can get stable performance */
3262 /* The experiment was done on SDIO interface */
3263 /* coding by Lucas@20130730 */
3264 *(u32 *)pval = IEEE80211_HT_MAX_AMPDU_16K;
3265 break;
3266 case HAL_DEF_TX_LDPC:
3267 case HAL_DEF_RX_LDPC:
3268 *((u8 *)pval) = false;
3269 break;
3270 case HAL_DEF_TX_STBC:
3271 *((u8 *)pval) = 0;
3272 break;
3273 case HAL_DEF_RX_STBC:
3274 *((u8 *)pval) = 1;
3275 break;
3276 case HAL_DEF_EXPLICIT_BEAMFORMER:
3277 case HAL_DEF_EXPLICIT_BEAMFORMEE:
3278 *((u8 *)pval) = false;
3279 break;
3280
3281 case HW_DEF_RA_INFO_DUMP:
3282 {
3283 u8 mac_id = *(u8 *)pval;
3284 u32 cmd;
3285
3286 cmd = 0x40000100 | mac_id;
3287 rtw_write32(padapter, REG_HMEBOX_DBG_2_8723B, cmd);
3288 msleep(10);
3289 rtw_read32(padapter, 0x2F0); // info 1
3290
3291 cmd = 0x40000400 | mac_id;
3292 rtw_write32(padapter, REG_HMEBOX_DBG_2_8723B, cmd);
3293 msleep(10);
3294 rtw_read32(padapter, 0x2F0); // info 1
3295 rtw_read32(padapter, 0x2F4); // info 2
3296 rtw_read32(padapter, 0x2F8); // rate mask 1
3297 rtw_read32(padapter, 0x2FC); // rate mask 2
3298 }
3299 break;
3300
3301 case HAL_DEF_TX_PAGE_BOUNDARY:
3302 if (!padapter->registrypriv.wifi_spec) {
3303 *(u8 *)pval = TX_PAGE_BOUNDARY_8723B;
3304 } else {
3305 *(u8 *)pval = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
3306 }
3307 break;
3308
3309 case HAL_DEF_MACID_SLEEP:
3310 *(u8 *)pval = true; /* support macid sleep */
3311 break;
3312
3313 default:
3314 bResult = GetHalDefVar(padapter, variable, pval);
3315 break;
3316 }
3317
3318 return bResult;
3319 }
3320
rtl8723b_start_thread(struct adapter * padapter)3321 void rtl8723b_start_thread(struct adapter *padapter)
3322 {
3323 struct xmit_priv *xmitpriv = &padapter->xmitpriv;
3324
3325 xmitpriv->SdioXmitThread = kthread_run(rtl8723bs_xmit_thread, padapter, "RTWHALXT");
3326 }
3327
rtl8723b_stop_thread(struct adapter * padapter)3328 void rtl8723b_stop_thread(struct adapter *padapter)
3329 {
3330 struct xmit_priv *xmitpriv = &padapter->xmitpriv;
3331
3332 /* stop xmit_buf_thread */
3333 if (xmitpriv->SdioXmitThread) {
3334 complete(&xmitpriv->SdioXmitStart);
3335 wait_for_completion(&xmitpriv->SdioXmitTerminate);
3336 xmitpriv->SdioXmitThread = NULL;
3337 }
3338 }
3339