xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPMA.scala (revision 011d262c490b7fd9c718724a21daceb78ad6689a) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5import freechips.rocketchip.rocket.CSRs
6import freechips.rocketchip.tile.XLen
7import org.chipsalliance.cde.config.Parameters
8import xiangshan.backend.fu.NewCSR.CSRDefines.{CSRWARLField => WARL}
9import xiangshan.backend.fu.NewCSR.CSRFunc._
10import xiangshan.backend.fu.PMAConfigEntry
11import xiangshan.backend.fu.util.CSRConst
12import xiangshan.{HasPMParameters, PMParameKey}
13
14import scala.collection.immutable.SeqMap
15
16trait CSRPMA { self: NewCSR =>
17  val pmacfg: Seq[CSRModule[_]] = Range(0, p(PMParameKey).NumPMA/8+1, 2).map(num =>
18    Module(new CSRModule(s"Pmacfg$num") with HasPMACfgRSink {
19      // read condition
20      regOut := cfgRData(64*(num/2+1)-1, 64*num/2)
21    })
22      .setAddr(CSRConst.PmacfgBase + num)
23  )
24
25  // every pmacfg has 8 cfgs
26  val pmacfgs: Seq[CSRModule[_]] = Range(0, p(PMParameKey).NumPMA).map(num =>
27    Module(new CSRModule(s"Pma$num"+"cfg", new PMACfgInitBundle(num)))
28  )
29
30  val pmaaddr: Seq[CSRModule[_]] = Range(0, p(PMParameKey).NumPMA).map(num =>
31    Module(new CSRModule(s"Pmaaddr$num") with HasPMAAddrSink {
32      // read condition
33      regOut := addrRData(num)
34    })
35      .setAddr(CSRConst.PmaaddrBase + num)
36  )
37
38  val pmaCSRMods: Seq[CSRModule[_]] = pmacfg ++ pmaaddr
39
40  val pmaCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_], UInt)] = SeqMap.from(
41    pmaCSRMods.map(csr => csr.addr -> (csr.w -> csr.rdata)).iterator
42  )
43
44  val pmaCSROutMap: SeqMap[Int, UInt] = SeqMap.from(
45    pmpCSRMods.map(csr => csr.addr -> csr.regOut.asInstanceOf[CSRBundle].asUInt).iterator
46  )
47
48  private val pmaCfgRead = Cat(pmacfgs.map(_.rdata(7, 0)).reverse)
49
50  pmaCSRMods.foreach { mod =>
51    mod match {
52      case m: HasPMACfgRSink =>
53        m.cfgRData := pmaCfgRead
54      case _ =>
55    }
56  }
57}
58
59class PMACfgInitBundle(num: Int)(implicit val p: Parameters) extends PMACfgBundle with PMAInit {
60  override val R      = WARL(0, wNoFilter).withReset(pmaInit(num).r.B)
61  override val W      = WARL(1, wNoFilter).withReset(pmaInit(num).w.B)
62  override val X      = WARL(2, wNoFilter).withReset(pmaInit(num).x.B)
63  override val A      = PMPCfgAField(4, 3, wNoFilter).withReset(if (pmaInit(num).a > 0) pmaInit(num).a.U else 0.U)
64  override val ATOMIC = WARL(5, wNoFilter).withReset(pmaInit(num).atomic.B)
65  override val C      = WARL(6, wNoFilter).withReset(pmaInit(num).c.B)
66  override val L      = PMPCfgLField(7, wNoFilter).withReset(pmaInit(num).l.B)
67}
68
69class PMACfgBundle extends PMPCfgBundle {
70  override val ATOMIC = WARL(5, wNoFilter).withReset(false.B)
71  override val C      = WARL(6, wNoFilter).withReset(false.B)
72}
73
74trait HasPMACfgRSink { self: CSRModule[_] =>
75  val cfgRData = IO(Input(UInt((p(PMParameKey).NumPMA/8 * p(XLen)).W)))
76}
77
78trait HasPMAAddrSink { self: CSRModule[_] =>
79  val addrRData = IO(Input(Vec(p(PMParameKey).NumPMA, UInt(64.W))))
80}
81
82trait PMAInit extends HasPMParameters with PMAReadWrite {
83  def pmaInit: Seq[PMAConfigEntry] = (PMAConfigs ++ Seq.fill(NumPMA-PMAConfigs.length)(PMAConfigEntry(0))).reverse
84}
85