| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 810 Register HiReg = HiOperand.getReg(); in emitCombineRI() local
861 Register HiReg = HiOperand.getReg(); in emitCombineRR() local
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| H A D | HexagonFrameLowering.cpp | 976 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 805 Register HiReg = HiOperand.getReg(); in emitCombineRI() local
856 Register HiReg = HiOperand.getReg(); in emitCombineRR() local
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| H A D | HexagonFrameLowering.cpp | 1126 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt() local
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| /aosp_15_r20/external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 783 unsigned HiReg = HiOperand.getReg(); in emitCombineRI() local
834 unsigned HiReg = HiOperand.getReg(); in emitCombineRR() local
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| H A D | HexagonFrameLowering.cpp | 826 unsigned HiReg = HRI.getSubReg(Reg, Hexagon::subreg_hireg); in insertCFIInstructionsAt() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 2186 Register HiReg = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() local
2370 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_SZA_EXT() local
2483 Register HiReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local
2538 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local
2575 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FABS() local
2845 Register HiReg = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() local
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| H A D | SILoadStoreOptimizer.cpp | 186 Register HiReg; member
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1136 Register HiReg = MI.getOperand(1).getReg(); in emitReadCycleWidePseudo() local
1172 Register HiReg = MI.getOperand(1).getReg(); in emitSplitF64Pseudo() local
1205 Register HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 814 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| H A D | MipsSEFrameLowering.cpp | 309 Register HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| /aosp_15_r20/external/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 651 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| H A D | MipsSEFrameLowering.cpp | 285 unsigned HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| /aosp_15_r20/external/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2184 unsigned SrcReg, LoReg, HiReg; in Select() local
2341 unsigned LoReg, HiReg, ClrReg; in Select() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 828 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| H A D | MipsSEFrameLowering.cpp | 309 Register HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| H A D | MipsISelLowering.cpp | 2954 MCRegister HiReg = State.AllocateReg(IntRegs); in CC_MipsO32() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1465 Register HiReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local
1674 Register HiReg = MRI->createVirtualRegister(&RegRC); in selectG_PTR_MASK() local
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| H A D | SILoadStoreOptimizer.cpp | 187 unsigned HiReg = 0; member
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4790 unsigned SrcReg, LoReg, HiReg; in Select() local
4885 unsigned LoReg, HiReg, ClrReg; in Select() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1975 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5241 unsigned LoReg, HiReg; in Select() local
5380 unsigned LoReg, HiReg, ClrReg; in Select() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1283 Register HiReg = VA.getLocReg(); in LowerCall_64() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 11061 Register HiReg = MI.getOperand(1).getReg(); in emitReadCycleWidePseudo() local
11097 Register HiReg = MI.getOperand(1).getReg(); in emitSplitF64Pseudo() local
11132 Register HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
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| /aosp_15_r20/external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 6102 unsigned Reg, unsigned HiReg, in checkLowRegisterList()
|