1 /* SPDX-License-Identifier: BSD-3-Clause */
2
3 //-----------------------------------------------------------------------------
4 // Include files
5 //-----------------------------------------------------------------------------
6 #include "dramc_common.h"
7 #include "dramc_int_global.h"
8 #include "x_hal_io.h"
9 //-----------------------------------------------------------------------------
10 // Global variables
11 //-----------------------------------------------------------------------------
12 U8 gDRSEnableSelfWakeup = 0;
13
14 #if (CHECK_GOLDEN_SETTING == TRUE)
15 typedef struct _GOLDEN_FIELD_T
16 {
17 char fieldName[64];
18 U32 group;
19 U32 field;
20 U32 u4ChaValue;
21 } GOLDEN_FIELD_T;
22 GOLDEN_FIELD_T *golden_setting_anwer;
23
24 #if APPLY_LOWPOWER_GOLDEN_SETTINGS
25
26 GOLDEN_FIELD_T shuf_golden_setting_anwer[] =
27 {
28 {"SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0},
29 {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 0x0},
30 {"MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL", DDRPHY_REG_MISC_SHU_CG_CTRL0, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL, 0x334f3000},
31 {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0},
32 {"SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1},
33 {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0},
34 {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 0x0},
35 {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0},
36 {"SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 0x0},
37 {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 0x0},
38 {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0},
39 {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0},
40 {"SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0},
41 {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0},
42 {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0},
43 {"SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 0x0},
44 {"SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0},
45 {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0},
46 {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 0x0},
47 {"SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0},
48 {"SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1},
49 {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0},
50 {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0},
51 {"SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 0x0},
52 {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 0x0},
53 {"SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1},
54 {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 0x0},
55 {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0},
56 {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0},
57 {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0},
58 {"SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA", DDRPHY_REG_SHU_CA_CMD13, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA, 0x0},
59 {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0},
60 {"SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0},
61 {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0},
62 {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0},
63 {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0},
64 {"SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT", DRAMC_REG_SHU_APHY_TX_PICG_CTRL, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1},
65 {"SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0},
66 {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0},
67 {"SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1},
68 };
69
70 GOLDEN_FIELD_T nonshuf_golden_setting_anwer[] =
71 {
72 {"SCSMCTRL_CG_SCARB_SM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCARB_SM_CGAR, 0x0},
73 {"MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 0x1},
74 {"MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 0x0},
75 {"MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT, 0x0},
76 {"DUMMY_RD_DUMMY_RD_PA_OPT", DRAMC_REG_DUMMY_RD, DUMMY_RD_DUMMY_RD_PA_OPT, 0x1},
77 {"DVFS_CTRL0_DVFS_CG_OPT", DRAMC_REG_DVFS_CTRL0, DVFS_CTRL0_DVFS_CG_OPT, 0x0},
78 {"MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 0x0},
79 {"MISC_CTRL3_ARPI_CG_MCTL_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_CA_OPT, 0x0},
80 {"MISC_CTRL4_R_OPT2_CG_DQSIEN", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQSIEN, 0x1},
81 {"MISC_CG_CTRL2_RG_MEM_DCM_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FSEL, 0x0},
82 {"MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 0x0},
83 {"RX_CG_SET0_RDATCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDATCKAR, 0x0},
84 {"MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT, 0x0},
85 {"MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 0x0},
86 {"MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF, 0x0},
87 {"MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 0x0},
88 {"MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 0x0},
89 {"MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE, 0x0},
90 {"RX_CG_SET0_RDYCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDYCKAR, 0x0},
91 {"DDRCOMMON0_DISSTOP26M", DRAMC_REG_DDRCOMMON0, DDRCOMMON0_DISSTOP26M, 0x0},
92 {"MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS", DRAMC_REG_MISCTL0, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 0x0},
93 {"DCM_CTRL0_BCLKAR", DRAMC_REG_DCM_CTRL0, DCM_CTRL0_BCLKAR, 0x0},
94 {"DRAMC_PD_CTRL_DCMEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN, 0x1},
95 {"MISC_CG_CTRL5_R_CA_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 0x1},
96 {"CLKAR_REQQUECLKRUN", DRAMC_REG_CLKAR, CLKAR_REQQUECLKRUN, 0x0},
97 {"CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT", DDRPHY_REG_CA_DLL_ARPI1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 0x0},
98 {"DRAMC_PD_CTRL_DCMENNOTRFC", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMENNOTRFC, 0x1},
99 {"MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN", DDRPHY_REG_MISC_DUTYSCAN1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 0x0},
100 {"TX_TRACKING_SET0_HMRRSEL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_HMRRSEL_CGAR, 0x0},
101 {"ACTIMING_CTRL_SEQCLKRUN", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN, 0x0},
102 {"MISC_CTRL3_ARPI_CG_CLK_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CLK_OPT, 0x0},
103 {"CMD_DEC_CTRL0_SELPH_CMD_CG_DIS", DRAMC_REG_CMD_DEC_CTRL0, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 0x0},
104 {"MISC_CTRL4_R_OPT2_CG_DQS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQS, 0x1},
105 {"TX_TRACKING_SET0_RDDQSOSC_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_RDDQSOSC_CGAR, 0x0},
106 {"MISC_CTRL4_R_OPT2_CG_CMD", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CMD, 0x1},
107 {"DRAMC_PD_CTRL_PHYCLKDYNGEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYCLKDYNGEN, 0x1},
108 {"MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 0x1},
109 {"MISC_CTRL3_ARPI_CG_MCK_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_CA_OPT, 0x0},
110 {"MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, 0x1},
111 {"MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0x0},
112 {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF, 0x0},
113 {"DRAMC_PD_CTRL_COMBPHY_CLKENSAME", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 0x0},
114 {"MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, 0x0},
115 {"MISC_CTRL3_ARPI_CG_CMD_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CMD_OPT, 0x0},
116 {"MISC_CTRL4_R_OPT2_CG_DQ", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQ, 0x1},
117 {"MISC_CTRL3_ARPI_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQ_OPT, 0x0},
118 {"MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 0x0},
119 {"DRAMC_PD_CTRL_COMBCLKCTRL", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBCLKCTRL, 0x1},
120 {"MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 0x1},
121 {"MISC_CG_CTRL5_R_CA_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_PI_DCM_EN, 0x1},
122 {"MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 0x0},
123 {"MISC_CTRL3_ARPI_CG_DQS_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQS_OPT, 0x0},
124 {"TX_CG_SET0_TX_ATK_CLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_TX_ATK_CLKRUN, 0x0},
125 {"ZQ_SET0_ZQCS_MASK_SEL_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0x0},
126 {"DRAMC_PD_CTRL_APHYCKCG_FIXOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0x0},
127 {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30, 0x0},
128 {"MISC_CTRL4_R_OPT2_CG_CS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CS, 0x1},
129 {"MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN, 0x0},
130 {"MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE, 0x0},
131 {"MISC_CTRL3_R_DDRPHY_COMB_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 0x0},
132 {"MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF, 0x0},
133 {"DRAMC_PD_CTRL_DCMEN2", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN2, 0x1},
134 {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN, 0x1},
135 {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27, 0x0},
136 {"MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 0x0},
137 {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT, 0x5},
138 {"SCSMCTRL_CG_SCSM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCSM_CGAR, 0x0},
139 {"DRAMC_PD_CTRL_MIOCKCTRLOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_MIOCKCTRLOFF, 0x0},
140 {"MISC_CTRL4_R_OPT2_CG_CLK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CLK, 0x1},
141 {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 0x0},
142 {"MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 0x0},
143 {"ACTIMING_CTRL_SEQCLKRUN3", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN3, 0x1},
144 {"ACTIMING_CTRL_SEQCLKRUN2", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN2, 0x0},
145 {"MISC_CG_CTRL5_R_DQ0_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 0x1},
146 {"MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN", DDRPHY_REG_MISC_RX_AUTOK_CFG0, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 0x0},
147 {"MISC_CTRL3_ARPI_CG_MCK_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 0x0},
148 {"MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, 0x0},
149 {"MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 0x0},
150 {"TX_CG_SET0_DWCLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_DWCLKRUN, 0x0},
151 {"MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE, 0x1},
152 {"SREF_DPD_CTRL_SREF_CG_OPT", DRAMC_REG_SREF_DPD_CTRL, SREF_DPD_CTRL_SREF_CG_OPT, 0x0},
153 {"TX_TRACKING_SET0_TXUIPI_CAL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 0x0},
154 {"MISC_CTRL4_R_OPT2_MPDIV_CG", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_MPDIV_CG, 0x1},
155 {"TX_CG_SET0_WDATA_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_WDATA_CG_DIS, 0x0},
156 {"MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 0x0},
157 {"MISC_CTRL4_R_OPT2_CG_MCK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_MCK, 0x1},
158 {"MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 0x3},
159 {"MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 0x17},
160 {"TX_CG_SET0_SELPH_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_SELPH_CG_DIS, 0x0},
161 {"DRAMC_PD_CTRL_PHYGLUECLKRUN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYGLUECLKRUN, 0x0},
162 {"MISC_CG_CTRL5_R_DQ1_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 0x1},
163 {"CLKAR_REQQUE_PACG_DIS", DRAMC_REG_CLKAR, CLKAR_REQQUE_PACG_DIS, 0x0},
164 {"ZQ_SET0_ZQMASK_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQMASK_CGAR, 0x0},
165 {"MISC_CTRL4_R_OPT2_CG_DQM", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQM, 0x1},
166 };
167
168 #else
169
170 GOLDEN_FIELD_T shuf_golden_setting_anwer[] =
171 {
172 {"SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x1},
173 {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 0x1},
174 {"MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL", DDRPHY_REG_MISC_SHU_CG_CTRL0, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL, 0x11400000},
175 {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0},
176 {"SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1},
177 {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x1},
178 {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 0x1},
179 {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x1},
180 {"SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 0x1},
181 {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 0x0},
182 {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0},
183 {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x1},
184 {"SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x1},
185 {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x1},
186 {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x1},
187 {"SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 0x1},
188 {"SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x1},
189 {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x1},
190 {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 0x1},
191 {"SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x1},
192 {"SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1},
193 {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x1},
194 {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x1},
195 {"SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 0x1},
196 {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 0x1},
197 {"SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1},
198 {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 0x0},
199 {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0},
200 {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x1},
201 {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x1},
202 {"SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA", DDRPHY_REG_SHU_CA_CMD13, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA, 0x0},
203 {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x1},
204 {"SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x1},
205 {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x1},
206 {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0},
207 {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0},
208 {"SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT", DRAMC_REG_SHU_APHY_TX_PICG_CTRL, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x0},
209 {"SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x1},
210 {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0},
211 {"SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1},
212 };
213
214 GOLDEN_FIELD_T nonshuf_golden_setting_anwer[] =
215 {
216 {"SCSMCTRL_CG_SCARB_SM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCARB_SM_CGAR, 0x1},
217 {"MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 0x0},
218 {"MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 0x1},
219 {"MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT, 0x0},
220 {"DUMMY_RD_DUMMY_RD_PA_OPT", DRAMC_REG_DUMMY_RD, DUMMY_RD_DUMMY_RD_PA_OPT, 0x1},
221 {"DVFS_CTRL0_DVFS_CG_OPT", DRAMC_REG_DVFS_CTRL0, DVFS_CTRL0_DVFS_CG_OPT, 0x1},
222 {"MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 0x0},
223 {"MISC_CTRL3_ARPI_CG_MCTL_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_CA_OPT, 0x0},
224 {"MISC_CTRL4_R_OPT2_CG_DQSIEN", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQSIEN, 0x0},
225 {"MISC_CG_CTRL2_RG_MEM_DCM_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FSEL, 0x0},
226 {"MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 0x1},
227 {"RX_CG_SET0_RDATCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDATCKAR, 0x1},
228 {"MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT, 0x0},
229 {"MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 0x1},
230 {"MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF, 0x0},
231 {"MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 0x1},
232 {"MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 0x1},
233 {"MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE, 0x1},
234 {"RX_CG_SET0_RDYCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDYCKAR, 0x1},
235 {"DDRCOMMON0_DISSTOP26M", DRAMC_REG_DDRCOMMON0, DDRCOMMON0_DISSTOP26M, 0x1},
236 {"MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS", DRAMC_REG_MISCTL0, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 0x1},
237 {"DCM_CTRL0_BCLKAR", DRAMC_REG_DCM_CTRL0, DCM_CTRL0_BCLKAR, 0x1},
238 {"DRAMC_PD_CTRL_DCMEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN, 0x0},
239 {"MISC_CG_CTRL5_R_CA_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 0x0},
240 {"CLKAR_REQQUECLKRUN", DRAMC_REG_CLKAR, CLKAR_REQQUECLKRUN, 0x1},
241 {"CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT", DDRPHY_REG_CA_DLL_ARPI1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 0x0},
242 {"DRAMC_PD_CTRL_DCMENNOTRFC", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMENNOTRFC, 0x0},
243 {"MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN", DDRPHY_REG_MISC_DUTYSCAN1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 0x1},
244 {"TX_TRACKING_SET0_HMRRSEL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_HMRRSEL_CGAR, 0x1},
245 {"ACTIMING_CTRL_SEQCLKRUN", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN, 0x1},
246 {"MISC_CTRL3_ARPI_CG_CLK_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CLK_OPT, 0x0},
247 {"CMD_DEC_CTRL0_SELPH_CMD_CG_DIS", DRAMC_REG_CMD_DEC_CTRL0, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 0x1},
248 {"MISC_CTRL4_R_OPT2_CG_DQS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQS, 0x0},
249 {"TX_TRACKING_SET0_RDDQSOSC_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_RDDQSOSC_CGAR, 0x1},
250 {"MISC_CTRL4_R_OPT2_CG_CMD", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CMD, 0x0},
251 {"DRAMC_PD_CTRL_PHYCLKDYNGEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYCLKDYNGEN, 0x0},
252 {"MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 0x0},
253 {"MISC_CTRL3_ARPI_CG_MCK_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_CA_OPT, 0x0},
254 {"MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, 0x1},
255 {"MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0x0},
256 {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF, 0x0},
257 {"DRAMC_PD_CTRL_COMBPHY_CLKENSAME", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 0x1},
258 {"MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, 0x0},
259 {"MISC_CTRL3_ARPI_CG_CMD_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CMD_OPT, 0x0},
260 {"MISC_CTRL4_R_OPT2_CG_DQ", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQ, 0x0},
261 {"MISC_CTRL3_ARPI_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQ_OPT, 0x0},
262 {"MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 0x1},
263 {"DRAMC_PD_CTRL_COMBCLKCTRL", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBCLKCTRL, 0x0},
264 {"MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 0x0},
265 {"MISC_CG_CTRL5_R_CA_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_PI_DCM_EN, 0x0},
266 {"MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 0x1},
267 {"MISC_CTRL3_ARPI_CG_DQS_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQS_OPT, 0x0},
268 {"TX_CG_SET0_TX_ATK_CLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_TX_ATK_CLKRUN, 0x1},
269 {"ZQ_SET0_ZQCS_MASK_SEL_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0x1},
270 {"DRAMC_PD_CTRL_APHYCKCG_FIXOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0x1},
271 {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30, 0x0},
272 {"MISC_CTRL4_R_OPT2_CG_CS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CS, 0x0},
273 {"MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN, 0x0},
274 {"MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE, 0x1},
275 {"MISC_CTRL3_R_DDRPHY_COMB_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 0x1},
276 {"MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF, 0x0},
277 {"DRAMC_PD_CTRL_DCMEN2", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN2, 0x0},
278 {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN, 0x1},
279 {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27, 0x0},
280 {"MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 0x1},
281 {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT, 0x5},
282 {"SCSMCTRL_CG_SCSM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCSM_CGAR, 0x1},
283 {"DRAMC_PD_CTRL_MIOCKCTRLOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_MIOCKCTRLOFF, 0x1},
284 {"MISC_CTRL4_R_OPT2_CG_CLK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CLK, 0x0},
285 {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 0x1},
286 {"MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 0x1},
287 {"ACTIMING_CTRL_SEQCLKRUN3", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN3, 0x1},
288 {"ACTIMING_CTRL_SEQCLKRUN2", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN2, 0x1},
289 {"MISC_CG_CTRL5_R_DQ0_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 0x0},
290 {"MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN", DDRPHY_REG_MISC_RX_AUTOK_CFG0, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 0x1},
291 {"MISC_CTRL3_ARPI_CG_MCK_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 0x0},
292 {"MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, 0x0},
293 {"MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 0x1},
294 {"TX_CG_SET0_DWCLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_DWCLKRUN, 0x1},
295 {"MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE, 0x1},
296 {"SREF_DPD_CTRL_SREF_CG_OPT", DRAMC_REG_SREF_DPD_CTRL, SREF_DPD_CTRL_SREF_CG_OPT, 0x1},
297 {"TX_TRACKING_SET0_TXUIPI_CAL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 0x1},
298 {"MISC_CTRL4_R_OPT2_MPDIV_CG", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_MPDIV_CG, 0x0},
299 {"TX_CG_SET0_WDATA_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_WDATA_CG_DIS, 0x1},
300 {"MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 0x1},
301 {"MISC_CTRL4_R_OPT2_CG_MCK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_MCK, 0x0},
302 {"MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 0x3},
303 {"MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 0x17},
304 {"TX_CG_SET0_SELPH_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_SELPH_CG_DIS, 0x1},
305 {"DRAMC_PD_CTRL_PHYGLUECLKRUN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYGLUECLKRUN, 0x1},
306 {"MISC_CG_CTRL5_R_DQ1_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 0x0},
307 {"CLKAR_REQQUE_PACG_DIS", DRAMC_REG_CLKAR, CLKAR_REQQUE_PACG_DIS, 0x7fff},
308 {"ZQ_SET0_ZQMASK_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQMASK_CGAR, 0x1},
309 {"MISC_CTRL4_R_OPT2_CG_DQM", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQM, 0x0},
310 };
311
312 #endif
313 #endif
314
EnableCommonDCMNonShuffle(DRAMC_CTX_T * p)315 static void EnableCommonDCMNonShuffle(DRAMC_CTX_T *p)
316 {
317 vIO32WriteFldAlign_All(DRAMC_REG_ACTIMING_CTRL, 0x1, ACTIMING_CTRL_SEQCLKRUN3);
318 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0,
319 P_Fld(0x1, MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE) |
320 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN) |
321 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF) |
322 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF));
323 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2,
324 P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE) |
325 P_Fld(0x17, MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL) |
326 P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_FSEL) |
327 P_Fld(0x0, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27) |
328 P_Fld(0x3, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL) |
329 P_Fld(0x0, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30) |
330 P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF) |
331 P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN) |
332 P_Fld(0x0, MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE) |
333 P_Fld(0x0, MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE) |
334 P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG) |
335 P_Fld(0x5, MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT));
336
337 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
338 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
339 vIO32WriteFldAlign_All(DDRPHY_REG_CA_DLL_ARPI1, 0x0, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT);
340 vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DUMMY_RD_PA_OPT);
341 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3,
342 P_Fld(0x0, MISC_CTRL3_ARPI_CG_DQS_OPT) |
343 P_Fld(0x0, MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT) |
344 P_Fld(0x0, MISC_CTRL3_ARPI_CG_DQ_OPT) |
345 P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT) |
346 P_Fld(0x0, MISC_CTRL3_ARPI_CG_CMD_OPT) |
347 P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT) |
348 P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCTL_CA_OPT) |
349 P_Fld(0x0, MISC_CTRL3_ARPI_CG_CLK_OPT) |
350 P_Fld(0x0, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT) |
351 P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCK_CA_OPT));
352 return;
353 }
354
EnableCommonDCMShuffle(DRAMC_CTX_T * p)355 static void EnableCommonDCMShuffle(DRAMC_CTX_T *p)
356 {
357 BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
358
359 if((vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) && (isLP4_DSC))
360 {
361 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ12, 0x1, SHU_B1_DQ12_DMY_DQ12_B1);
362 }
363 else
364 {
365 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ12, 0, SHU_B1_DQ12_DMY_DQ12_B1);
366 }
367
368 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8,
369 P_Fld(!isLP4_DSC, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
370 P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1));
371 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD7,
372 P_Fld(0x0, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW) |
373 P_Fld(0x0, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW));
374 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ7,
375 P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
376 P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) |
377 P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1));
378 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD13, 0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA);
379 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8,
380 P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) |
381 P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0));
382 #if TX_PICG_NEW_MODE
383 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ7,
384 P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) |
385 P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) |
386 P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0));
387 #endif
388 return;
389 }
390
EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T * p,bool bEn)391 void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn)
392 {
393 BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
394 U8 MPDIV_CG = 1;
395
396 EnableCommonDCMNonShuffle(p);
397
398 if(bEn)
399 {
400 vIO32WriteFldAlign_All(DRAMC_REG_SREF_DPD_CTRL, 0x0, SREF_DPD_CTRL_SREF_CG_OPT);
401 vIO32WriteFldMulti_All(DRAMC_REG_RX_CG_SET0,
402 P_Fld(0x0, RX_CG_SET0_RDYCKAR) |
403 P_Fld(0x0, RX_CG_SET0_RDATCKAR));
404 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2,
405 P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON) |
406 P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN));
407
408 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
409 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
410 vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0,
411 P_Fld(0x0, TX_CG_SET0_DWCLKRUN) |
412 P_Fld(0x0, TX_CG_SET0_SELPH_CG_DIS) |
413 P_Fld(0x0, TX_CG_SET0_TX_ATK_CLKRUN) |
414 P_Fld(0x0, TX_CG_SET0_WDATA_CG_DIS));
415 vIO32WriteFldMulti_All(DRAMC_REG_ACTIMING_CTRL,
416 P_Fld(0x0, ACTIMING_CTRL_SEQCLKRUN2) |
417 P_Fld(0x0, ACTIMING_CTRL_SEQCLKRUN));
418 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0,
419 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE) |
420 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE) |
421 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE) |
422 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE) |
423 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE) |
424 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE) |
425 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE) |
426 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE) |
427 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE) |
428 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE) |
429 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE) |
430 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE));
431 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DUTYSCAN1, 0x0, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN);
432 vIO32WriteFldAlign_All(DRAMC_REG_DDRCOMMON0, 0x0, DDRCOMMON0_DISSTOP26M);
433 vIO32WriteFldMulti_All(DRAMC_REG_TX_TRACKING_SET0,
434 P_Fld(0x0, TX_TRACKING_SET0_TXUIPI_CAL_CGAR) |
435 P_Fld(0x0, TX_TRACKING_SET0_RDDQSOSC_CGAR) |
436 P_Fld(0x0, TX_TRACKING_SET0_HMRRSEL_CGAR));
437 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RX_AUTOK_CFG0, 0x0, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN);
438 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL5,
439 P_Fld(0x1, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN) |
440 P_Fld(0x1, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN) |
441 P_Fld(0x1, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN) |
442 P_Fld(0x1, MISC_CG_CTRL5_R_CA_PI_DCM_EN) |
443 P_Fld(0x1, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN) |
444 P_Fld(0x1, MISC_CG_CTRL5_R_CA_DLY_DCM_EN));
445 vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0,
446 P_Fld(0x0, ZQ_SET0_ZQCS_MASK_SEL_CGAR) |
447 P_Fld(0x0, ZQ_SET0_ZQMASK_CGAR));
448 vIO32WriteFldAlign_All(DRAMC_REG_DVFS_CTRL0, 0x0, DVFS_CTRL0_DVFS_CG_OPT);
449 vIO32WriteFldAlign_All(DRAMC_REG_DCM_CTRL0, 0x0, DCM_CTRL0_BCLKAR);
450 vIO32WriteFldMulti_All(DRAMC_REG_SCSMCTRL_CG,
451 P_Fld(0x0, SCSMCTRL_CG_SCARB_SM_CGAR) |
452 P_Fld(0x0, SCSMCTRL_CG_SCSM_CGAR));
453 vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_PD_CTRL,
454 P_Fld(0x1, DRAMC_PD_CTRL_PHYCLKDYNGEN) |
455 P_Fld(0x1, DRAMC_PD_CTRL_DCMEN2) |
456 P_Fld(0x1, DRAMC_PD_CTRL_DCMEN) |
457 P_Fld(0x0, DRAMC_PD_CTRL_PHYGLUECLKRUN) |
458 P_Fld(0x0, DRAMC_PD_CTRL_COMBPHY_CLKENSAME) |
459 P_Fld(0x0, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) |
460 P_Fld(0x0, DRAMC_PD_CTRL_MIOCKCTRLOFF) |
461 P_Fld(0x1, DRAMC_PD_CTRL_DCMENNOTRFC) |
462 P_Fld(0x1, DRAMC_PD_CTRL_COMBCLKCTRL));
463 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3,
464 P_Fld(0x0, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG) |
465 P_Fld(0x0, MISC_CTRL3_R_DDRPHY_COMB_CG_IG));
466 vIO32WriteFldAlign_All(DRAMC_REG_CMD_DEC_CTRL0, 0x0, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS);
467 vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 0x0, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS);
468 #if ENABLE_DDR800_SOPEN_DSC_WA
469 if (isLP4_DSC&&(vGet_DDR_Loop_Mode(p)==SEMI_OPEN_LOOP_MODE))
470 MPDIV_CG = 0;
471 #endif
472 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL4,
473 #if (RX_PICG_NEW_MODE || TX_PICG_NEW_MODE)
474 P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_MCK) |
475 P_Fld(MPDIV_CG, MISC_CTRL4_R_OPT2_MPDIV_CG) |
476 #endif
477 #if RX_PICG_NEW_MODE
478 P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQSIEN) |
479 #endif
480 #if TX_PICG_NEW_MODE
481 P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQ) |
482 P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQS) |
483 P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQM) |
484 #endif
485 P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_CMD) |
486 P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_CLK) |
487 P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_CS));
488 vIO32WriteFldMulti_All(DRAMC_REG_CLKAR,
489 P_Fld(0x0, CLKAR_REQQUE_PACG_DIS) |
490 P_Fld(0x0, CLKAR_REQQUECLKRUN));
491 }
492 else
493 {
494 vIO32WriteFldAlign_All(DRAMC_REG_SREF_DPD_CTRL, 0x1, SREF_DPD_CTRL_SREF_CG_OPT);
495 vIO32WriteFldMulti_All(DRAMC_REG_RX_CG_SET0,
496 P_Fld(0x1, RX_CG_SET0_RDYCKAR) |
497 P_Fld(0x1, RX_CG_SET0_RDATCKAR));
498 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2,
499 P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON) |
500 P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN));
501
502 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
503 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
504 vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0,
505 P_Fld(0x1, TX_CG_SET0_DWCLKRUN) |
506 P_Fld(0x1, TX_CG_SET0_SELPH_CG_DIS) |
507 P_Fld(0x1, TX_CG_SET0_TX_ATK_CLKRUN) |
508 P_Fld(0x1, TX_CG_SET0_WDATA_CG_DIS));
509 vIO32WriteFldMulti_All(DRAMC_REG_ACTIMING_CTRL,
510 P_Fld(0x1, ACTIMING_CTRL_SEQCLKRUN2) |
511 P_Fld(0x1, ACTIMING_CTRL_SEQCLKRUN));
512 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0,
513 P_Fld(0x1, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE) |
514 P_Fld(0x1, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE) |
515 P_Fld(0x1, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE) |
516 P_Fld(0x1, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE) |
517 P_Fld(0x1, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE) |
518 P_Fld(0x1, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE) |
519 P_Fld(0x1, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE) |
520 P_Fld(0x1, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE) |
521 P_Fld(0x1, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE) |
522 P_Fld(0x1, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE) |
523 P_Fld(0x1, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE) |
524 P_Fld(0x1, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE));
525 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DUTYSCAN1, 0x1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN);
526 vIO32WriteFldAlign_All(DRAMC_REG_DDRCOMMON0, 0x1, DDRCOMMON0_DISSTOP26M);
527 vIO32WriteFldMulti_All(DRAMC_REG_TX_TRACKING_SET0,
528 P_Fld(0x1, TX_TRACKING_SET0_TXUIPI_CAL_CGAR) |
529 P_Fld(0x1, TX_TRACKING_SET0_RDDQSOSC_CGAR) |
530 P_Fld(0x1, TX_TRACKING_SET0_HMRRSEL_CGAR));
531 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RX_AUTOK_CFG0, 0x1, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN);
532 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL5,
533 P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN) |
534 P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN) |
535 P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN) |
536 P_Fld(0x0, MISC_CG_CTRL5_R_CA_PI_DCM_EN) |
537 P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN) |
538 P_Fld(0x0, MISC_CG_CTRL5_R_CA_DLY_DCM_EN));
539 vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0,
540 P_Fld(0x1, ZQ_SET0_ZQCS_MASK_SEL_CGAR) |
541 P_Fld(0x1, ZQ_SET0_ZQMASK_CGAR));
542 vIO32WriteFldAlign_All(DRAMC_REG_DVFS_CTRL0, 0x1, DVFS_CTRL0_DVFS_CG_OPT);
543 vIO32WriteFldAlign_All(DRAMC_REG_DCM_CTRL0, 0x1, DCM_CTRL0_BCLKAR);
544 vIO32WriteFldMulti_All(DRAMC_REG_SCSMCTRL_CG,
545 P_Fld(0x1, SCSMCTRL_CG_SCARB_SM_CGAR) |
546 P_Fld(0x1, SCSMCTRL_CG_SCSM_CGAR));
547 vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_PD_CTRL,
548 P_Fld(0x0, DRAMC_PD_CTRL_PHYCLKDYNGEN) |
549 P_Fld(0x0, DRAMC_PD_CTRL_DCMEN2) |
550 P_Fld(0x0, DRAMC_PD_CTRL_DCMEN) |
551 P_Fld(0x1, DRAMC_PD_CTRL_PHYGLUECLKRUN) |
552 P_Fld(0x1, DRAMC_PD_CTRL_COMBPHY_CLKENSAME) |
553 P_Fld(0x1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) |
554 P_Fld(0x1, DRAMC_PD_CTRL_MIOCKCTRLOFF) |
555 P_Fld(0x0, DRAMC_PD_CTRL_DCMENNOTRFC) |
556 P_Fld(0x0, DRAMC_PD_CTRL_COMBCLKCTRL));
557 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3,
558 P_Fld(0x1, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG) |
559 P_Fld(0x1, MISC_CTRL3_R_DDRPHY_COMB_CG_IG));
560 vIO32WriteFldAlign_All(DRAMC_REG_CMD_DEC_CTRL0, 0x1, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS);
561 vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 0x1, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS);
562 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL4,
563 P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQSIEN) |
564 P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_CLK) |
565 P_Fld(0x0, MISC_CTRL4_R_OPT2_MPDIV_CG) |
566 P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQM) |
567 P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_CMD) |
568 P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQS) |
569 P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_MCK) |
570 P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_CS) |
571 P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQ));
572 vIO32WriteFldMulti_All(DRAMC_REG_CLKAR,
573 P_Fld(0x7fff, CLKAR_REQQUE_PACG_DIS) |
574 P_Fld(0x1, CLKAR_REQQUECLKRUN));
575 }
576 return;
577 }
578
EnableDramcPhyDCMShuffle(DRAMC_CTX_T * p,bool bEn)579 void EnableDramcPhyDCMShuffle(DRAMC_CTX_T *p, bool bEn)
580 {
581 BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
582
583 // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND3: Special case
584 // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND2: Special case
585 // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND1: Special case
586 // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_DLE_LAST_EXTEND1: Special case
587 // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_DLE_LAST_EXTEND2: Special case
588 // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_DLE_LAST_EXTEND3: Special case
589 EnableCommonDCMShuffle(p);
590
591 if(bEn)
592 {
593 #if TX_PICG_NEW_MODE
594 vIO32WriteFldAlign_All(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, 0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT);
595 #endif
596 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8,
597 P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
598 P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) |
599 P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
600 P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) |
601 P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) |
602 P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
603 P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
604 P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1) |
605 P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1));
606 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD8,
607 P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA) |
608 P_Fld(0x0, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA) |
609 P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA) |
610 P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA) |
611 P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA) |
612 P_Fld(0x0, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA) |
613 P_Fld(isLP4_DSC, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA));
614 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_CG_CTRL0, 0x334f3000, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL);
615 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8,
616 P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) |
617 P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) |
618 P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
619 P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
620 P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
621 P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) |
622 P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
623 P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0) |
624 P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0));
625 }
626 else
627 {
628 vIO32WriteFldAlign_All(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, 0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT);
629 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8,
630 P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
631 P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) |
632 P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
633 P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) |
634 P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) |
635 P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
636 P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
637 P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1) |
638 P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1));
639 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD8,
640 P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA) |
641 P_Fld(0x1, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA) |
642 P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA) |
643 P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA) |
644 P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA) |
645 P_Fld(0x1, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA) |
646 P_Fld(0x1, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA));
647 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_CG_CTRL0, 0x11400000, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL);
648 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8,
649 P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) |
650 P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) |
651 P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
652 P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
653 P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
654 P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) |
655 P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
656 P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0) |
657 P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0));
658 }
659 return;
660 }
661
662
663
EnableDramcPhyDCM(DRAMC_CTX_T * p,bool bEn)664 void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn)
665 {
666 U32 u4WbrBackup = GetDramcBroadcast();
667 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
668
669 EnableDramcPhyDCMNonShuffle(p, bEn);
670 EnableDramcPhyDCMShuffle(p, bEn);
671
672 #if ((CHECK_GOLDEN_SETTING == TRUE) && (APPLY_LOWPOWER_GOLDEN_SETTINGS == 0))
673 DRAM_STATUS_T stResult = CheckGoldenSetting(p);
674 mcSHOW_DBG_MSG3(("Golden setting check: %s\n", (stResult == DRAM_OK)? ("OK") : ("NG")));
675 #endif
676
677 DramcBroadcastOnOff(u4WbrBackup);
678 return;
679 }
680
681
682 #if RX_PICG_NEW_MODE
683 #if 0
684 DRAM_STATUS_T CheckRxPICGNewModeSetting(DRAMC_CTX_T *p)
685 {
686 U8 channel_idx;
687 U8 u1RankIdx;
688 U32 u4Value;
689
690
691 for(channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
692 {
693 p->channel = channel_idx;
694 mcSHOW_DBG_MSG(("CH[%d] \n", channel_idx));
695 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_CG_MCK);
696 mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_CG_MCK:0x%x \n", u4Value));
697
698 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_MPDIV_CG);
699 mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_MPDIV_CG:0x%x \n", u4Value));
700
701 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_CG_DQSIEN);
702 mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_CG_DQSIEN:0x%x \n", u4Value));
703
704
705 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), MISC_STBCAL1_STBCNT_SHU_RST_EN);
706 mcSHOW_DBG_MSG(("MISC_STBCAL1_STBCNT_SHU_RST_EN:0x%x \n", u4Value));
707
708 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN);
709 mcSHOW_DBG_MSG(("MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN:0x%x \n", u4Value));
710
711 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), MISC_SHU_STBCAL_DQSIEN_PICG_MODE);
712 mcSHOW_DBG_MSG(("MISC_SHU_STBCAL_DQSIEN_PICG_MODE:0x%x \n", u4Value));
713
714
715 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT);
716 mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT:0x%x \n", u4Value));
717
718 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT);
719 mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT:0x%x \n", u4Value));
720
721 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN);
722 mcSHOW_DBG_MSG(("MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN:0x%x \n", u4Value));
723
724 for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)
725 {
726
727 vSetRank(p, u1RankIdx);
728 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL), MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT);
729 mcSHOW_DBG_MSG(("Rank[%d] MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT:0x%x \n", u1RankIdx, u4Value));
730 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL), MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT);
731 mcSHOW_DBG_MSG(("Rank[%d] MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT:0x%x \n", u1RankIdx, u4Value));
732 }
733 vSetRank(p, RANK_0);
734
735 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN);
736 mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN:0x%x \n", u4Value));
737
738 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN);
739 mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN:0x%x \n", u4Value));
740
741 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN);
742 mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN:0x%x \n", u4Value));
743
744
745 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN);
746 mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN:0x%x \n", u4Value));
747
748 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN);
749 mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN:0x%x \n", u4Value));
750
751 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN);
752 mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN:0x%x \n", u4Value));
753
754 }
755 p->channel = CHANNEL_A;
756 }
757 #endif
758 #endif
759
760 #if (CHECK_GOLDEN_SETTING == TRUE)
CheckGoldenField(DRAMC_CTX_T * p,GOLDEN_FIELD_T * golden_setting_anwer,U16 array_size)761 static DRAM_STATUS_T CheckGoldenField(DRAMC_CTX_T *p, GOLDEN_FIELD_T *golden_setting_anwer, U16 array_size)
762 {
763 DRAM_STATUS_T eStatus = DRAM_OK;
764 U8 channel_idx;
765 U32 u4Value = 0;
766 U32 u4Answer = 0;
767 U16 array_cnt = array_size / sizeof(golden_setting_anwer[0]);
768
769 U16 u2Idx = 0;
770 for(u2Idx = 0; u2Idx < array_cnt; u2Idx++)
771 {
772 for(channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
773 {
774 vSetPHY2ChannelMapping(p, channel_idx);
775 u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(golden_setting_anwer[u2Idx].group), golden_setting_anwer[u2Idx].field);
776 //mcSHOW_DBG_MSG(("%s: 0x%x\n", golden_setting_anwer[u2Idx].fieldName, u4Value));
777
778 u4Answer = *(&golden_setting_anwer[u2Idx].u4ChaValue);
779
780 if(u4Answer != 0xffffffff)
781 {
782 if(u4Answer == u4Value)
783 {
784 //mcSHOW_DBG_MSG(("OK [%s] 0x%x\n", golden_setting_anwer[u2Idx].fieldName, u4Answer));
785 }
786 else
787 {
788 mcSHOW_ERR_MSG(("*** fail ***[%s]CH[%d][0x%x][ANS:0x%x]****** fail\n", golden_setting_anwer[u2Idx].fieldName, channel_idx, u4Value, u4Answer));
789 eStatus |= DRAM_FAIL;
790 }
791 }
792 }
793 }
794 return eStatus;
795 }
796
CheckGoldenSetting(DRAMC_CTX_T * p)797 DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p)
798 {
799 U8 u1BkShuffleIdx = vGet_Current_SRAMIdx(p);
800 U8 u1SramShuffleIdx = 0;
801 U8 u1ShuffleIdx = 0;
802 U8 backup_channel = vGetPHY2ChannelMapping(p);
803 DRAM_STATUS_T eStatus = DRAM_OK;
804
805 mcSHOW_DBG_MSG3(("Golden setting check[Begin]\n"));
806 eStatus |= CheckGoldenField(p, nonshuf_golden_setting_anwer, sizeof(nonshuf_golden_setting_anwer));
807
808
809 if(gAndroid_DVFS_en)
810 {
811 for (u1ShuffleIdx = 0; u1ShuffleIdx <= DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
812 {
813 if (u1ShuffleIdx < DRAM_DFS_SRAM_MAX)
814 {
815 mcSHOW_DBG_MSG3(("SRAM SHU%d\n", u1ShuffleIdx));
816 u1SramShuffleIdx = u1ShuffleIdx;
817 }
818 else
819 {
820 mcSHOW_DBG_MSG3(("CONF SHU0, DDR[%d]\n", p->frequency * 2));
821 u1SramShuffleIdx = u1BkShuffleIdx;
822 }
823
824 //mcSHOW_DBG_MSG(("shuf_golden_setting_anwer:%d %d\n", sizeof(shuf_golden_setting_anwer), sizeof(shuf_golden_setting_anwer[0])));
825 DramcDFSDirectJump(p, u1SramShuffleIdx);
826 DramcDFSDirectJump(p, u1SramShuffleIdx);
827
828 eStatus |= CheckGoldenField(p, shuf_golden_setting_anwer, sizeof(shuf_golden_setting_anwer));
829 }
830 }
831 else
832 {
833 mcSHOW_DBG_MSG3(("CONF SHU0, DDR[%d]\n", p->frequency * 2));
834 eStatus |= CheckGoldenField(p, shuf_golden_setting_anwer, sizeof(shuf_golden_setting_anwer));
835 }
836
837 mcSHOW_DBG_MSG3(("Golden setting check[End]\n"));
838
839 vSetPHY2ChannelMapping(p, backup_channel);
840 return eStatus;
841 }
842 #endif
843
844
HwSaveForSR(DRAMC_CTX_T * p)845 void HwSaveForSR(DRAMC_CTX_T *p)
846 {
847 vIO32WriteFldMulti_All(DRAMC_REG_SREF_DPD_CTRL, P_Fld(0, SREF_DPD_CTRL_GT_SYNC_MASK)
848 | P_Fld(1, SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN)
849 | P_Fld(1, SREF_DPD_CTRL_SREF2_OPTION)
850 | P_Fld(0, SREF_DPD_CTRL_SREF3_OPTION));
851
852 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0x0, MISC_DVFSCTL2_GT_SYNC_MASK_FOR_PHY);
853 }
854 //#endif
855
856
857 //#ifdef CLK_FREE_FUN_FOR_DRAMC_PSEL
858
ClkFreeRunForDramcPsel(DRAMC_CTX_T * p)859 void ClkFreeRunForDramcPsel(DRAMC_CTX_T *p)
860 {
861 vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0, P_Fld(0, TX_CG_SET0_PSEL_OPT1)
862 | P_Fld(0, TX_CG_SET0_PSEL_OPT2)
863 | P_Fld(0, TX_CG_SET0_PSEL_OPT3)
864 | P_Fld(0, TX_CG_SET0_PSELAR));
865 }
866 //#endif
867
868 #if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION
869 #if 0
870 static void EnableDllCg(DRAMC_CTX_T *p, U32 u4OnOff)
871 {
872 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DLL_ARPI2, u4OnOff, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0);
873 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DLL_ARPI2, u4OnOff, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1);
874 vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_DLL_ARPI2 + SHIFT_TO_CHB_ADDR, u4OnOff, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA);
875 }
876 #endif
DDR800semiPowerSavingOn(DRAMC_CTX_T * p,U8 next_shu_level,U8 u1OnOff)877 void DDR800semiPowerSavingOn(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff)
878 {
879 #if __Petrus_TO_BE_PORTING__
880 U8 u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_MISC_DVFSCTL, MISC_DVFSCTL_R_OTHER_SHU_GP);
881 U8 u1IsDdr800Semi = u4IO32ReadFldAlign(DDRPHY_REG_SHU_PLL1 + (SHU_GRP_DDRPHY_OFFSET * u1ShuLevel), SHU_PLL1_RG_RPHYPLL_DDR400_EN);
882
883 if (u1IsDdr800Semi != 1)
884 return;
885
886 if ((next_shu_level != SRAM_SHU9) && (u1OnOff == DISABLE))
887 {
888
889 EnableDllCg(p, DISABLE);
890 }
891 else if ((next_shu_level == SRAM_SHU9) && (u1OnOff == ENABLE))
892 {
893
894 EnableDllCg(p, ENABLE);
895 }
896 #endif
897 }
898 #endif
899 #if 0
900 void DramcDRS(DRAMC_CTX_T *p, U8 bEnable)
901 {
902
903 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DRSCTRL), P_Fld(0, DRSCTRL_DRSPB2AB_OPT)
904 | P_Fld(0, DRSCTRL_DRSMON_CLR)
905 | P_Fld(8, DRSCTRL_DRSDLY)
906 | P_Fld(0, DRSCTRL_DRSACKWAITREF)
907 | P_Fld(!bEnable, DRSCTRL_DRSDIS)
908 | P_Fld(1, DRSCTRL_DRSCLR_EN)
909 | P_Fld(3, DRSCTRL_DRS_CNTX)
910 | P_Fld(!gDRSEnableSelfWakeup, DRSCTRL_DRS_SELFWAKE_DMYRD_DIS)
911 | P_Fld(0, DRSCTRL_DRSOPT2));
912 }
913 #endif
914
915 #if 0
916 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
917 void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op)
918 {
919 U8 ucstatus = 0;
920 U32 uiTemp;
921 U32 u4TimeCnt;
922
923 u4TimeCnt = TIME_OUT_CNT;
924
925 mcSHOW_DBG_MSG(("[EnterSelfRefresh] %s\n", ((op == 1) ? "enter" : "exit")));
926
927 if (op == 1)
928 {
929
930 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 1, SREFCTRL_SRFPD_DIS);
931
932 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 1, SREFCTRL_SELFREF);
933 mcDELAY_US(2);
934 uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
935 while ((uiTemp == 0) && (u4TimeCnt > 0))
936 {
937 mcSHOW_DBG_MSG2(("Still not enter self refresh(%d)\n", u4TimeCnt));
938 mcDELAY_US(1);
939 uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
940 u4TimeCnt --;
941 }
942 }
943 else
944 {
945 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 0, SREFCTRL_SELFREF);
946
947 mcDELAY_US(2);
948 uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
949 while ((uiTemp != 0) && (u4TimeCnt > 0))
950 {
951 mcSHOW_DBG_MSG2(("Still not exit self refresh(%d)\n", u4TimeCnt));
952 mcDELAY_US(1);
953 uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
954 u4TimeCnt--;
955 }
956 }
957
958 if (u4TimeCnt == 0)
959 {
960 mcSHOW_DBG_MSG(("Self refresh fail\n"));
961 }
962 else
963 {
964 mcSHOW_DBG_MSG(("Self refresh done\n"));
965 }
966 }
967 #endif
968 #endif
969
970 //#if ENABLE_RX_DCM_DPHY
EnableRxDcmDPhy(DRAMC_CTX_T * p,U16 u2Freq)971 void EnableRxDcmDPhy(DRAMC_CTX_T *p, U16 u2Freq)
972 {
973 U8 u1PRECAL_CG_EN = 0;
974
975
976 if (u1IsPhaseMode(p) == TRUE)
977 u1PRECAL_CG_EN = 1;
978 else
979 u1PRECAL_CG_EN = 0;
980
981
982 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL,
983 P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DCM_OPT) |
984 P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT) |
985 P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT) |
986 P_Fld(0x0, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN) |
987 P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN) |
988 P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN) |
989 P_Fld(u1PRECAL_CG_EN, MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN) |
990 P_Fld(0x2, MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY) |
991 P_Fld(0x0, MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY));
992
993 #if RDSEL_TRACKING_EN
994 if(u2Freq >= RDSEL_TRACKING_TH)
995 {
996 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, 0x0, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN);
997 }
998 else
999 #endif
1000 {
1001 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, 0x1, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN);
1002 }
1003
1004 }
1005 //#endif
1006
1007 //#if CMD_PICG_NEW_MODE
EnableCmdPicgEffImprove(DRAMC_CTX_T * p)1008 void EnableCmdPicgEffImprove(DRAMC_CTX_T *p)
1009 {
1010 U16 u2Clk_Dyn_Gating_Sel = 0x4;
1011
1012 if (vGet_Div_Mode(p) == DIV4_MODE)
1013 {
1014 u2Clk_Dyn_Gating_Sel = 0x6;
1015 }
1016 else
1017 {
1018 u2Clk_Dyn_Gating_Sel = 0x5;
1019 }
1020
1021 vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | P_Fld(u2Clk_Dyn_Gating_Sel, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL));
1022 }
1023 //#endif
1024