xref: /aosp_15_r20/external/coreboot/src/soc/intel/meteorlake/include/soc/iomap.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _SOC_METEORLAKE_IOMAP_H_
4 #define _SOC_METEORLAKE_IOMAP_H_
5 
6 #include <soc/pcr_ids.h>
7 
8 /*
9  * Memory-mapped I/O registers.
10  */
11 #define PCH_PRESERVED_BASE_ADDRESS	0xfd800000
12 #define PCH_PRESERVED_BASE_SIZE	0x01000000
13 
14 #define MCH_BASE_ADDRESS	0xfedc0000
15 #define MCH_BASE_SIZE		0x20000
16 
17 #define DMI_BASE_ADDRESS	0xfeda0000
18 #define DMI_BASE_SIZE		0x1000
19 
20 #define EP_BASE_ADDRESS		0xfeda1000
21 #define EP_BASE_SIZE		0x1000
22 
23 #define EDRAM_BASE_ADDRESS	0xfed80000
24 #define EDRAM_BASE_SIZE		0x4000
25 
26 #define IOE_PWRM_BASE_ADDRESS	0xfe400000
27 #define IOE_PWRM_BASE_SIZE	0x10000
28 
29 #define PCH_PWRM_BASE_ADDRESS	0xfe000000
30 #define PCH_PWRM_BASE_SIZE	0x10000
31 
32 #define GPIO_BASE_SIZE		0x10000
33 
34 #define HECI1_BASE_ADDRESS	0xfeda2000
35 
36 #define VTD_BASE_ADDRESS	0xfc800000
37 #define VTD_BASE_SIZE		0x00002000
38 
39 #define GFXVT_BASE_ADDRESS	0xfc800000
40 #define GFXVT_BASE_SIZE		0x1000
41 
42 #define VTVC0_BASE_ADDRESS	0xfc801000
43 #define VTVC0_BASE_SIZE		0x1000
44 
45 #define UART_BASE_SIZE		0x1000
46 #define UART_BASE_0_ADDRESS	0xfe03e000
47 /* Both UART BAR 0 and 1 are 4KB in size */
48 #define UART_BASE_0_ADDR(x)	(UART_BASE_0_ADDRESS + (2 * \
49 					UART_BASE_SIZE * (x)))
50 #define UART_BASE(x)		UART_BASE_0_ADDR(x)
51 
52 #define EARLY_GSPI_BASE_ADDRESS 0xfe030000
53 
54 #define EARLY_I2C_BASE_ADDRESS	0xfe020000
55 #define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))
56 
57 #define SPI_BASE_ADDRESS	0xfe010000
58 
59 #define REG_BASE_ADDRESS	0xd0000000
60 #define REG_BASE_SIZE		(256 * MiB)
61 
62 #define P2SB_BAR		CONFIG_PCR_BASE_ADDRESS
63 #define P2SB_SIZE		(16 * MiB)
64 
65 #define IOE_PCR_ABOVE_4G_BASE_ADDR	CONFIG_IOE_PCR_BASE_ADDRESS
66 #define IOE_P2SB_BAR		IOE_PCR_ABOVE_4G_BASE_ADDR
67 #define IOE_P2SB_SIZE		(256 * MiB)
68 
69 #define IOM_BASE_ADDR		0x3fff0aa0000
70 #define IOM_BASE_SIZE		0x1600
71 #define IOM_BASE_ADDR_MAX	0x3fff0aa15ff
72 
73 /*
74  * I/O port address space
75  */
76 #define ACPI_BASE_ADDRESS	0x1800
77 #define ACPI_BASE_SIZE		0x100
78 
79 #define TCO_BASE_ADDRESS	0x400
80 #define TCO_BASE_SIZE		0x20
81 #endif
82