| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 121 static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) { in isDispOrCDisp8()
521 int ImmOffset = 0; in emitMemModRMByte() local
548 int ImmOffset = 0; in emitMemModRMByte() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 4232 unsigned ImmOffset; in splitBufferOffsets() local
4275 unsigned ImmOffset, Register VIndex, in updateBufferMMO()
4401 unsigned ImmOffset; in legalizeBufferStore() local
4473 unsigned ImmOffset, unsigned Format, in buildBufferLoad()
4538 unsigned ImmOffset; in legalizeBufferLoad() local
4740 unsigned ImmOffset; in legalizeBufferAtomic() local
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| H A D | AMDGPURegisterBankInfo.cpp | 1258 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1277 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1370 int64_t ImmOffset = 0; in applyMappingSBufferLoad() local
1809 unsigned ImmOffset; in splitBufferOffsets() local
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| H A D | AMDGPUISelDAGToDAG.cpp | 1648 int64_t ImmOffset = 0; in SelectGlobalSAddr() local
1821 int64_t ImmOffset = 0; in SelectScratchSVAddr() local
2418 int ImmOffset = 0; in SelectDS_GWS() local
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| H A D | AMDGPUInstructionSelector.cpp | 1611 unsigned ImmOffset; in selectDSGWSIntrinsic() local
3952 int64_t ImmOffset = 0; in selectGlobalSAddr() local
4063 int64_t ImmOffset = 0; in selectScratchSAddr() local
4139 int64_t ImmOffset = 0; in selectScratchSVAddr() local
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| H A D | SIISelLowering.cpp | 8495 unsigned ImmOffset = C1->getZExtValue(); in splitBufferOffsets() local
8536 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
8548 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 857 const int64_t ImmOffset = MFI.getObjectOffset(SaveIndex); in emitPrologue() local
1873 const int64_t ImmOffset = MFI.getObjectOffset(SaveIndex); in emitEpilogue() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandPseudoInsts.cpp | 715 int ImmOffset = MI.getOperand(2).getImm() + Offset; in expandSVESpillFill() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 923 unsigned ImmOffset = TotalConstOffset; in splitBufferOffsets() local
990 unsigned ImmOffset; in selectStoreIntrinsic() local
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| H A D | AMDGPURegisterBankInfo.cpp | 1301 unsigned ImmOffset; in splitBufferOffsets() local
1384 unsigned ImmOffset; in selectStoreIntrinsic() local
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| H A D | SIISelLowering.cpp | 7150 unsigned ImmOffset = C1->getZExtValue(); in splitBufferOffsets() local
7191 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
7202 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
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| H A D | AMDGPUISelDAGToDAG.cpp | 2286 int ImmOffset = 0; in SelectDS_GWS() local
|
| /aosp_15_r20/external/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 534 int ImmOffset = 0; in emitMemModRMByte() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 574 int ImmOffset = 0; in emitMemModRMByte() local
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1037 SDValue &ImmOffset, in SelectMUBUFIntrinsicVOffset()
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| /aosp_15_r20/external/swiftshader/third_party/subzero/src/ |
| H A D | IceInstMIPS32.cpp | 47 Operand *ImmOffset, AddrMode Mode) in OperandMIPS32Mem()
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| H A D | IceInstMIPS32.h | 175 Operand *const ImmOffset; variable
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| H A D | IceInstARM32.h | 157 ConstantInteger32 *ImmOffset; variable
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| H A D | IceInstARM32.cpp | 321 ConstantInteger32 *ImmOffset, AddrMode Mode) in OperandARM32Mem()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 1269 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, in splitMUBUFOffset()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 4055 SDValue Base, RegOffset, ImmOffset; in Select() local
4084 SDValue Base, RegOffset, ImmOffset; in Select() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 2566 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, in splitMUBUFOffset()
|