| /aosp_15_r20/external/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 2099 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); in PPCMaterializeInt() local
2119 unsigned ImmReg = createResultReg(RC); in PPCMaterializeInt() local
2273 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); in fastEmit_i() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 2211 Register ImmReg = createResultReg(&PPC::CRBITRCRegClass); in PPCMaterializeInt() local
2231 Register ImmReg = createResultReg(RC); in PPCMaterializeInt() local
2393 Register ImmReg = createResultReg(&PPC::CRBITRCRegClass); in fastEmit_i() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 2204 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); in PPCMaterializeInt() local
2224 unsigned ImmReg = createResultReg(RC); in PPCMaterializeInt() local
2386 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); in fastEmit_i() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 992 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeRead2Pair() local
1085 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeWrite2Pair() local
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| H A D | SIInstrInfo.cpp | 5672 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
5691 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
5701 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
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| H A D | R600ISelLowering.cpp | 2153 unsigned ImmReg = R600::ALU_LITERAL_X; in FoldOperand() local
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| H A D | AMDGPUInstructionSelector.cpp | 1662 Register ImmReg = MRI->createVirtualRegister(&RegRC); in selectG_PTR_MASK() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 1192 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeRead2Pair() local
1284 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeWrite2Pair() local
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| H A D | R600ISelLowering.cpp | 2035 unsigned ImmReg = R600::ALU_LITERAL_X; in FoldOperand() local
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| H A D | SIInstrInfo.cpp | 7222 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
7241 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
7262 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
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| H A D | AMDGPUInstructionSelector.cpp | 2208 Register ImmReg = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 475 unsigned ImmReg = createResultReg(RC); in ARMMaterializeInt() local
491 unsigned ImmReg = createResultReg(RC); in ARMMaterializeInt() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 464 Register ImmReg = createResultReg(RC); in ARMMaterializeInt() local
480 Register ImmReg = createResultReg(RC); in ARMMaterializeInt() local
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| /aosp_15_r20/external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 483 unsigned ImmReg = createResultReg(RC); in ARMMaterializeInt() local
499 unsigned ImmReg = createResultReg(RC); in ARMMaterializeInt() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4592 unsigned ImmReg = DstReg; in expandSgeImm() local
4622 unsigned ImmReg = DstReg; in expandSgtImm() local
4722 unsigned ImmReg = DstReg; in expandSleImm() local
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 2253 unsigned ImmReg = AMDGPU::ALU_LITERAL_X; in FoldOperand() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4573 unsigned ImmReg = DstReg; in expandSgeImm() local
4603 unsigned ImmReg = DstReg; in expandSgtImm() local
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| /aosp_15_r20/external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 1433 unsigned ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL); in processBlock() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 1479 unsigned ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL); in processBlock() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 1516 Register ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL); in processBlock() local
|