1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F4xx_LL_RCC_H
22 #define __STM32F4xx_LL_RCC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f4xx.h"
30
31 /** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35 #if defined(RCC)
36
37 /** @defgroup RCC_LL RCC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
44 * @{
45 */
46
47 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
48 static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
49 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
50
51 /**
52 * @}
53 */
54 /* Private constants ---------------------------------------------------------*/
55 /* Private macros ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
58 * @{
59 */
60 /**
61 * @}
62 */
63 #endif /*USE_FULL_LL_DRIVER*/
64 /* Exported types ------------------------------------------------------------*/
65 #if defined(USE_FULL_LL_DRIVER)
66 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
67 * @{
68 */
69
70 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
71 * @{
72 */
73
74 /**
75 * @brief RCC Clocks Frequency Structure
76 */
77 typedef struct
78 {
79 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
80 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
81 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
82 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
83 } LL_RCC_ClocksTypeDef;
84
85 /**
86 * @}
87 */
88
89 /**
90 * @}
91 */
92 #endif /* USE_FULL_LL_DRIVER */
93
94 /* Exported constants --------------------------------------------------------*/
95 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
96 * @{
97 */
98
99 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
100 * @brief Defines used to adapt values of different oscillators
101 * @note These values could be modified in the user environment according to
102 * HW set-up.
103 * @{
104 */
105 #if !defined (HSE_VALUE)
106 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
107 #endif /* HSE_VALUE */
108
109 #if !defined (HSI_VALUE)
110 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
111 #endif /* HSI_VALUE */
112
113 #if !defined (LSE_VALUE)
114 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
115 #endif /* LSE_VALUE */
116
117 #if !defined (LSI_VALUE)
118 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
119 #endif /* LSI_VALUE */
120
121 #if !defined (EXTERNAL_CLOCK_VALUE)
122 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
123 #endif /* EXTERNAL_CLOCK_VALUE */
124 /**
125 * @}
126 */
127
128 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
129 * @brief Flags defines which can be used with LL_RCC_WriteReg function
130 * @{
131 */
132 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
133 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
134 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
135 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
136 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
137 #if defined(RCC_PLLI2S_SUPPORT)
138 #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */
139 #endif /* RCC_PLLI2S_SUPPORT */
140 #if defined(RCC_PLLSAI_SUPPORT)
141 #define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */
142 #endif /* RCC_PLLSAI_SUPPORT */
143 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
144 /**
145 * @}
146 */
147
148 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
149 * @brief Flags defines which can be used with LL_RCC_ReadReg function
150 * @{
151 */
152 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
153 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
154 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
155 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
156 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
157 #if defined(RCC_PLLI2S_SUPPORT)
158 #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */
159 #endif /* RCC_PLLI2S_SUPPORT */
160 #if defined(RCC_PLLSAI_SUPPORT)
161 #define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */
162 #endif /* RCC_PLLSAI_SUPPORT */
163 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
164 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
165 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
166 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
167 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
168 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
169 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
170 #if defined(RCC_CSR_BORRSTF)
171 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
172 #endif /* RCC_CSR_BORRSTF */
173 /**
174 * @}
175 */
176
177 /** @defgroup RCC_LL_EC_IT IT Defines
178 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
179 * @{
180 */
181 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
182 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
183 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
184 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
185 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
186 #if defined(RCC_PLLI2S_SUPPORT)
187 #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */
188 #endif /* RCC_PLLI2S_SUPPORT */
189 #if defined(RCC_PLLSAI_SUPPORT)
190 #define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */
191 #endif /* RCC_PLLSAI_SUPPORT */
192 /**
193 * @}
194 */
195
196 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
197 * @{
198 */
199 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
200 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
201 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
202 #if defined(RCC_CFGR_SW_PLLR)
203 #define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /*!< PLLR selection as system clock */
204 #endif /* RCC_CFGR_SW_PLLR */
205 /**
206 * @}
207 */
208
209 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
210 * @{
211 */
212 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
213 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
214 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
215 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
216 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /*!< PLLR used as system clock */
217 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
218 /**
219 * @}
220 */
221
222 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
223 * @{
224 */
225 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
226 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
227 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
228 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
229 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
230 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
231 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
232 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
233 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
234 /**
235 * @}
236 */
237
238 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
239 * @{
240 */
241 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
242 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
243 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
244 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
245 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
246 /**
247 * @}
248 */
249
250 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
251 * @{
252 */
253 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
254 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
255 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
256 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
257 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
258 /**
259 * @}
260 */
261
262 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
263 * @{
264 */
265 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */
266 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */
267 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */
268 #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */
269 #if defined(RCC_CFGR_MCO2)
270 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */
271 #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */
272 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */
273 #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */
274 #endif /* RCC_CFGR_MCO2 */
275 /**
276 * @}
277 */
278
279 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
280 * @{
281 */
282 #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */
283 #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */
284 #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */
285 #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */
286 #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */
287 #if defined(RCC_CFGR_MCO2PRE)
288 #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */
289 #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */
290 #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */
291 #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */
292 #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */
293 #endif /* RCC_CFGR_MCO2PRE */
294 /**
295 * @}
296 */
297
298 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
299 * @{
300 */
301 #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */
302 #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */
303 #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */
304 #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */
305 #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */
306 #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */
307 #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */
308 #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */
309 #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */
310 #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */
311 #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */
312 #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */
313 #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */
314 #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */
315 #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */
316 #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */
317 #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */
318 #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */
319 #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */
320 #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */
321 #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */
322 #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */
323 #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */
324 #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */
325 #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */
326 #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */
327 #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */
328 #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */
329 #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */
330 #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */
331 #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */
332 /**
333 * @}
334 */
335
336 #if defined(USE_FULL_LL_DRIVER)
337 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
338 * @{
339 */
340 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
341 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
342 /**
343 * @}
344 */
345 #endif /* USE_FULL_LL_DRIVER */
346
347 #if defined(FMPI2C1)
348 /** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection
349 * @{
350 */
351 #define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as FMPI2C1 clock source */
352 #define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */
353 #define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */
354 /**
355 * @}
356 */
357 #endif /* FMPI2C1 */
358
359 #if defined(LPTIM1)
360 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
361 * @{
362 */
363 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */
364 #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */
365 #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */
366 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */
367 /**
368 * @}
369 */
370 #endif /* LPTIM1 */
371
372 #if defined(SAI1)
373 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
374 * @{
375 */
376 #if defined(RCC_DCKCFGR_SAI1SRC)
377 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */
378 #define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 clock source */
379 #define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /*!< PLL clock used as SAI1 clock source */
380 #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16)) /*!< External pin clock used as SAI1 clock source */
381 #endif /* RCC_DCKCFGR_SAI1SRC */
382 #if defined(RCC_DCKCFGR_SAI2SRC)
383 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */
384 #define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /*!< PLLI2S clock used as SAI2 clock source */
385 #define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /*!< PLL clock used as SAI2 clock source */
386 #define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16)) /*!< PLL Main clock used as SAI2 clock source */
387 #endif /* RCC_DCKCFGR_SAI2SRC */
388 #if defined(RCC_DCKCFGR_SAI1ASRC)
389 #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
390 #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block A clock source */
391 #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */
392 #define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */
393 #define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16)) /*!< PLL Main clock used as SAI1 block A clock source */
394 #else
395 #define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block A clock source */
396 #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */
397 #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */
398 #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
399 #endif /* RCC_DCKCFGR_SAI1ASRC */
400 #if defined(RCC_DCKCFGR_SAI1BSRC)
401 #if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)
402 #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block B clock source */
403 #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */
404 #define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */
405 #define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16)) /*!< PLL Main clock used as SAI1 block B clock source */
406 #else
407 #define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block B clock source */
408 #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */
409 #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */
410 #endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */
411 #endif /* RCC_DCKCFGR_SAI1BSRC */
412 /**
413 * @}
414 */
415 #endif /* SAI1 */
416
417 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
418 /** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection
419 * @{
420 */
421 #define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /*!< PLL 48M domain clock used as SDIO clock */
422 #if defined(RCC_DCKCFGR_SDIOSEL)
423 #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /*!< System clock clock used as SDIO clock */
424 #else
425 #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /*!< System clock clock used as SDIO clock */
426 #endif /* RCC_DCKCFGR_SDIOSEL */
427 /**
428 * @}
429 */
430 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
431
432 #if defined(DSI)
433 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
434 * @{
435 */
436 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */
437 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /*!< PLL clock used as DSI byte lane clock source */
438 /**
439 * @}
440 */
441 #endif /* DSI */
442
443 #if defined(CEC)
444 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
445 * @{
446 */
447 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */
448 #define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /*!< LSE oscillator clock used as CEC clock */
449 /**
450 * @}
451 */
452 #endif /* CEC */
453
454 /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
455 * @{
456 */
457 #if defined(RCC_CFGR_I2SSRC)
458 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */
459 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */
460 #endif /* RCC_CFGR_I2SSRC */
461 #if defined(RCC_DCKCFGR_I2SSRC)
462 #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U) /*!< PLL clock used as I2S1 clock source */
463 #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
464 #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16)) /*!< PLL Main clock used as I2S1 clock source */
465 #endif /* RCC_DCKCFGR_I2SSRC */
466 #if defined(RCC_DCKCFGR_I2S1SRC)
467 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U) /*!< PLLI2S clock used as I2S1 clock source */
468 #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
469 #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */
470 #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16)) /*!< PLL Main clock used as I2S1 clock source */
471 #endif /* RCC_DCKCFGR_I2S1SRC */
472 #if defined(RCC_DCKCFGR_I2S2SRC)
473 #define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U) /*!< PLLI2S clock used as I2S2 clock source */
474 #define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */
475 #define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */
476 #define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16)) /*!< PLL Main clock used as I2S2 clock source */
477 #endif /* RCC_DCKCFGR_I2S2SRC */
478 /**
479 * @}
480 */
481
482 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
483 /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
484 * @{
485 */
486 #if defined(RCC_DCKCFGR_CK48MSEL)
487 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
488 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
489 #endif /* RCC_DCKCFGR_CK48MSEL */
490 #if defined(RCC_DCKCFGR2_CK48MSEL)
491 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
492 #if defined(RCC_PLLSAI_SUPPORT)
493 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
494 #endif /* RCC_PLLSAI_SUPPORT */
495 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
496 #define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /*!< PLLI2S oscillator clock used as 48Mhz domain clock */
497 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
498 #endif /* RCC_DCKCFGR2_CK48MSEL */
499 /**
500 * @}
501 */
502
503 #if defined(RNG)
504 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
505 * @{
506 */
507 #define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as RNG clock source */
508 #if defined(RCC_PLLSAI_SUPPORT)
509 #define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as RNG clock source */
510 #endif /* RCC_PLLSAI_SUPPORT */
511 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
512 #define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as RNG clock source */
513 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
514 /**
515 * @}
516 */
517 #endif /* RNG */
518
519 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
520 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
521 * @{
522 */
523 #define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as USB clock source */
524 #if defined(RCC_PLLSAI_SUPPORT)
525 #define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as USB clock source */
526 #endif /* RCC_PLLSAI_SUPPORT */
527 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
528 #define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as USB clock source */
529 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
530 /**
531 * @}
532 */
533 #endif /* USB_OTG_FS || USB_OTG_HS */
534
535 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
536
537 #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
538 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
539 * @{
540 */
541 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM1 Audio clock source */
542 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */
543 #if defined(DFSDM2_Channel0)
544 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM2 Audio clock source */
545 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */
546 #endif /* DFSDM2_Channel0 */
547 /**
548 * @}
549 */
550
551 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
552 * @{
553 */
554 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */
555 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM1 clock */
556 #if defined(DFSDM2_Channel0)
557 #define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM2 clock */
558 #define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM2 clock */
559 #endif /* DFSDM2_Channel0 */
560 /**
561 * @}
562 */
563 #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
564
565 #if defined(FMPI2C1)
566 /** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source
567 * @{
568 */
569 #define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /*!< FMPI2C1 Clock source selection */
570 /**
571 * @}
572 */
573 #endif /* FMPI2C1 */
574
575 #if defined(SPDIFRX)
576 /** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection
577 * @{
578 */
579 #define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as SPDIFRX clock source */
580 #define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */
581 /**
582 * @}
583 */
584 #endif /* SPDIFRX */
585
586 #if defined(LPTIM1)
587 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
588 * @{
589 */
590 #define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */
591 /**
592 * @}
593 */
594 #endif /* LPTIM1 */
595
596 #if defined(SAI1)
597 /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
598 * @{
599 */
600 #if defined(RCC_DCKCFGR_SAI1ASRC)
601 #define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */
602 #endif /* RCC_DCKCFGR_SAI1ASRC */
603 #if defined(RCC_DCKCFGR_SAI1BSRC)
604 #define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */
605 #endif /* RCC_DCKCFGR_SAI1BSRC */
606 #if defined(RCC_DCKCFGR_SAI1SRC)
607 #define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /*!< SAI1 Clock source selection */
608 #endif /* RCC_DCKCFGR_SAI1SRC */
609 #if defined(RCC_DCKCFGR_SAI2SRC)
610 #define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /*!< SAI2 Clock source selection */
611 #endif /* RCC_DCKCFGR_SAI2SRC */
612 /**
613 * @}
614 */
615 #endif /* SAI1 */
616
617 #if defined(SDIO)
618 /** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source
619 * @{
620 */
621 #if defined(RCC_DCKCFGR_SDIOSEL)
622 #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /*!< SDIO Clock source selection */
623 #elif defined(RCC_DCKCFGR2_SDIOSEL)
624 #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /*!< SDIO Clock source selection */
625 #else
626 #define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< SDIO Clock source selection */
627 #endif
628 /**
629 * @}
630 */
631 #endif /* SDIO */
632
633 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
634 /** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
635 * @{
636 */
637 #if defined(RCC_DCKCFGR_CK48MSEL)
638 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /*!< CK48M Domain clock source selection */
639 #endif /* RCC_DCKCFGR_CK48MSEL */
640 #if defined(RCC_DCKCFGR2_CK48MSEL)
641 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */
642 #endif /* RCC_DCKCFGR_CK48MSEL */
643 /**
644 * @}
645 */
646 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
647
648 #if defined(RNG)
649 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
650 * @{
651 */
652 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
653 #define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */
654 #else
655 #define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< RNG Clock source selection */
656 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
657 /**
658 * @}
659 */
660 #endif /* RNG */
661
662 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
663 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
664 * @{
665 */
666 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
667 #define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */
668 #else
669 #define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< USB Clock source selection */
670 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
671 /**
672 * @}
673 */
674 #endif /* USB_OTG_FS || USB_OTG_HS */
675
676 #if defined(CEC)
677 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
678 * @{
679 */
680 #define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
681 /**
682 * @}
683 */
684 #endif /* CEC */
685
686 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
687 * @{
688 */
689 #if defined(RCC_CFGR_I2SSRC)
690 #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */
691 #endif /* RCC_CFGR_I2SSRC */
692 #if defined(RCC_DCKCFGR_I2SSRC)
693 #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /*!< I2S1 Clock source selection */
694 #endif /* RCC_DCKCFGR_I2SSRC */
695 #if defined(RCC_DCKCFGR_I2S1SRC)
696 #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */
697 #endif /* RCC_DCKCFGR_I2S1SRC */
698 #if defined(RCC_DCKCFGR_I2S2SRC)
699 #define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */
700 #endif /* RCC_DCKCFGR_I2S2SRC */
701 /**
702 * @}
703 */
704
705 #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
706 /** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
707 * @{
708 */
709 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */
710 #if defined(DFSDM2_Channel0)
711 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */
712 #endif /* DFSDM2_Channel0 */
713 /**
714 * @}
715 */
716
717 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
718 * @{
719 */
720 #define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */
721 #if defined(DFSDM2_Channel0)
722 #define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */
723 #endif /* DFSDM2_Channel0 */
724 /**
725 * @}
726 */
727 #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
728
729 #if defined(SPDIFRX)
730 /** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
731 * @{
732 */
733 #define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */
734 /**
735 * @}
736 */
737 #endif /* SPDIFRX */
738
739 #if defined(DSI)
740 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
741 * @{
742 */
743 #define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */
744 /**
745 * @}
746 */
747 #endif /* DSI */
748
749 #if defined(LTDC)
750 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
751 * @{
752 */
753 #define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */
754 /**
755 * @}
756 */
757 #endif /* LTDC */
758
759
760 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
761 * @{
762 */
763 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
764 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
765 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
766 #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
767 /**
768 * @}
769 */
770
771 #if defined(RCC_DCKCFGR_TIMPRE)
772 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
773 * @{
774 */
775 #define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */
776 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /*!< Timers clock to four time PCLK */
777 /**
778 * @}
779 */
780 #endif /* RCC_DCKCFGR_TIMPRE */
781
782 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
783 * @{
784 */
785 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
786 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
787 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
788 #define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U) /*!< I2S External pin input clock selected as PLLI2S entry clock source */
789 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
790 /**
791 * @}
792 */
793
794 /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
795 * @{
796 */
797 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */
798 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */
799 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */
800 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */
801 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */
802 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */
803 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */
804 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */
805 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */
806 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */
807 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */
808 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */
809 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */
810 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */
811 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */
812 #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */
813 #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */
814 #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */
815 #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */
816 #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */
817 #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */
818 #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */
819 #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */
820 #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */
821 #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */
822 #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */
823 #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */
824 #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */
825 #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */
826 #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */
827 #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */
828 #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */
829 #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */
830 #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */
831 #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */
832 #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */
833 #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */
834 #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */
835 #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */
836 #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */
837 #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */
838 #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */
839 #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */
840 #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */
841 #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */
842 #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */
843 #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */
844 #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */
845 #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */
846 #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */
847 #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */
848 #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */
849 #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */
850 #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */
851 #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */
852 #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */
853 #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */
854 #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */
855 #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */
856 #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */
857 #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */
858 #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */
859 /**
860 * @}
861 */
862
863 #if defined(RCC_PLLCFGR_PLLR)
864 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
865 * @{
866 */
867 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
868 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
869 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
870 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
871 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
872 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
873 /**
874 * @}
875 */
876 #endif /* RCC_PLLCFGR_PLLR */
877
878 #if defined(RCC_DCKCFGR_PLLDIVR)
879 /** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR)
880 * @{
881 */
882 #define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 1 */
883 #define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 2 */
884 #define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 3 */
885 #define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 4 */
886 #define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 5 */
887 #define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 6 */
888 #define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 7 */
889 #define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 8 */
890 #define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 9 */
891 #define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 10 */
892 #define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 11 */
893 #define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 12 */
894 #define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 13 */
895 #define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 14 */
896 #define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 15 */
897 #define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /*!< PLL division factor for PLLDIVR output by 16 */
898 #define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 17 */
899 #define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 18 */
900 #define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 19 */
901 #define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 20 */
902 #define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 21 */
903 #define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 22 */
904 #define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 23 */
905 #define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 24 */
906 #define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 25 */
907 #define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 26 */
908 #define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 27 */
909 #define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 28 */
910 #define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 29 */
911 #define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 30 */
912 #define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 31 */
913 /**
914 * @}
915 */
916 #endif /* RCC_DCKCFGR_PLLDIVR */
917
918 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
919 * @{
920 */
921 #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */
922 #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */
923 #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */
924 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */
925 /**
926 * @}
927 */
928
929 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
930 * @{
931 */
932 #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */
933 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
934 #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */
935 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
936 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
937 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
938 #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */
939 #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
940 #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
941 #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
942 #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
943 #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
944 #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
945 #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
946 /**
947 * @}
948 */
949
950 /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
951 * @{
952 */
953 #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */
954 #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */
955 /**
956 * @}
957 */
958
959 #if defined(RCC_PLLI2S_SUPPORT)
960 /** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM)
961 * @{
962 */
963 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
964 #define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */
965 #define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */
966 #define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */
967 #define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */
968 #define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */
969 #define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */
970 #define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */
971 #define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */
972 #define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */
973 #define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */
974 #define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */
975 #define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */
976 #define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */
977 #define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */
978 #define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */
979 #define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */
980 #define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */
981 #define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */
982 #define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */
983 #define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */
984 #define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */
985 #define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */
986 #define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */
987 #define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */
988 #define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */
989 #define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */
990 #define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */
991 #define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */
992 #define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */
993 #define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */
994 #define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */
995 #define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */
996 #define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */
997 #define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */
998 #define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */
999 #define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */
1000 #define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */
1001 #define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */
1002 #define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */
1003 #define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */
1004 #define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */
1005 #define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */
1006 #define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */
1007 #define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */
1008 #define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */
1009 #define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */
1010 #define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */
1011 #define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */
1012 #define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */
1013 #define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */
1014 #define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */
1015 #define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */
1016 #define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */
1017 #define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */
1018 #define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */
1019 #define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */
1020 #define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */
1021 #define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */
1022 #define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */
1023 #define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */
1024 #define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */
1025 #define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */
1026 #else
1027 #define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLI2S division factor for PLLI2SM output by 2 */
1028 #define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLI2S division factor for PLLI2SM output by 3 */
1029 #define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLI2S division factor for PLLI2SM output by 4 */
1030 #define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLI2S division factor for PLLI2SM output by 5 */
1031 #define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLI2S division factor for PLLI2SM output by 6 */
1032 #define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLI2S division factor for PLLI2SM output by 7 */
1033 #define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLI2S division factor for PLLI2SM output by 8 */
1034 #define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLI2S division factor for PLLI2SM output by 9 */
1035 #define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLI2S division factor for PLLI2SM output by 10 */
1036 #define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLI2S division factor for PLLI2SM output by 11 */
1037 #define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLI2S division factor for PLLI2SM output by 12 */
1038 #define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLI2S division factor for PLLI2SM output by 13 */
1039 #define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLI2S division factor for PLLI2SM output by 14 */
1040 #define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLI2S division factor for PLLI2SM output by 15 */
1041 #define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLI2S division factor for PLLI2SM output by 16 */
1042 #define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLI2S division factor for PLLI2SM output by 17 */
1043 #define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLI2S division factor for PLLI2SM output by 18 */
1044 #define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLI2S division factor for PLLI2SM output by 19 */
1045 #define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLI2S division factor for PLLI2SM output by 20 */
1046 #define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLI2S division factor for PLLI2SM output by 21 */
1047 #define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLI2S division factor for PLLI2SM output by 22 */
1048 #define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLI2S division factor for PLLI2SM output by 23 */
1049 #define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLI2S division factor for PLLI2SM output by 24 */
1050 #define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLI2S division factor for PLLI2SM output by 25 */
1051 #define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLI2S division factor for PLLI2SM output by 26 */
1052 #define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLI2S division factor for PLLI2SM output by 27 */
1053 #define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLI2S division factor for PLLI2SM output by 28 */
1054 #define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLI2S division factor for PLLI2SM output by 29 */
1055 #define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLI2S division factor for PLLI2SM output by 30 */
1056 #define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLI2S division factor for PLLI2SM output by 31 */
1057 #define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLI2S division factor for PLLI2SM output by 32 */
1058 #define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLI2S division factor for PLLI2SM output by 33 */
1059 #define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLI2S division factor for PLLI2SM output by 34 */
1060 #define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLI2S division factor for PLLI2SM output by 35 */
1061 #define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLI2S division factor for PLLI2SM output by 36 */
1062 #define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLI2S division factor for PLLI2SM output by 37 */
1063 #define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLI2S division factor for PLLI2SM output by 38 */
1064 #define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLI2S division factor for PLLI2SM output by 39 */
1065 #define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLI2S division factor for PLLI2SM output by 40 */
1066 #define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLI2S division factor for PLLI2SM output by 41 */
1067 #define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLI2S division factor for PLLI2SM output by 42 */
1068 #define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLI2S division factor for PLLI2SM output by 43 */
1069 #define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLI2S division factor for PLLI2SM output by 44 */
1070 #define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLI2S division factor for PLLI2SM output by 45 */
1071 #define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLI2S division factor for PLLI2SM output by 46 */
1072 #define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLI2S division factor for PLLI2SM output by 47 */
1073 #define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLI2S division factor for PLLI2SM output by 48 */
1074 #define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLI2S division factor for PLLI2SM output by 49 */
1075 #define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLI2S division factor for PLLI2SM output by 50 */
1076 #define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLI2S division factor for PLLI2SM output by 51 */
1077 #define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLI2S division factor for PLLI2SM output by 52 */
1078 #define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLI2S division factor for PLLI2SM output by 53 */
1079 #define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLI2S division factor for PLLI2SM output by 54 */
1080 #define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLI2S division factor for PLLI2SM output by 55 */
1081 #define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLI2S division factor for PLLI2SM output by 56 */
1082 #define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLI2S division factor for PLLI2SM output by 57 */
1083 #define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLI2S division factor for PLLI2SM output by 58 */
1084 #define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLI2S division factor for PLLI2SM output by 59 */
1085 #define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLI2S division factor for PLLI2SM output by 60 */
1086 #define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLI2S division factor for PLLI2SM output by 61 */
1087 #define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLI2S division factor for PLLI2SM output by 62 */
1088 #define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLI2S division factor for PLLI2SM output by 63 */
1089 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
1090 /**
1091 * @}
1092 */
1093
1094 #if defined(RCC_PLLI2SCFGR_PLLI2SQ)
1095 /** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
1096 * @{
1097 */
1098 #define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */
1099 #define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */
1100 #define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */
1101 #define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */
1102 #define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */
1103 #define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */
1104 #define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */
1105 #define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */
1106 #define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */
1107 #define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */
1108 #define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */
1109 #define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */
1110 #define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */
1111 #define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */
1112 /**
1113 * @}
1114 */
1115 #endif /* RCC_PLLI2SCFGR_PLLI2SQ */
1116
1117 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
1118 /** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
1119 * @{
1120 */
1121 #define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */
1122 #define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */
1123 #define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */
1124 #define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */
1125 #define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */
1126 #define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */
1127 #define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */
1128 #define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */
1129 #define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */
1130 #define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */
1131 #define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */
1132 #define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */
1133 #define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */
1134 #define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */
1135 #define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */
1136 #define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */
1137 #define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */
1138 #define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */
1139 #define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */
1140 #define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */
1141 #define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */
1142 #define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */
1143 #define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */
1144 #define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */
1145 #define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */
1146 #define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */
1147 #define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */
1148 #define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */
1149 #define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */
1150 #define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */
1151 #define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */
1152 #define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */
1153 /**
1154 * @}
1155 */
1156 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
1157
1158 #if defined(RCC_DCKCFGR_PLLI2SDIVR)
1159 /** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR)
1160 * @{
1161 */
1162 #define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */
1163 #define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */
1164 #define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */
1165 #define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */
1166 #define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */
1167 #define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */
1168 #define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */
1169 #define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */
1170 #define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */
1171 #define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */
1172 #define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */
1173 #define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */
1174 #define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */
1175 #define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */
1176 #define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */
1177 #define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */
1178 #define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */
1179 #define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */
1180 #define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */
1181 #define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */
1182 #define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */
1183 #define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */
1184 #define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */
1185 #define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */
1186 #define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */
1187 #define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */
1188 #define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */
1189 #define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */
1190 #define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */
1191 #define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */
1192 #define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */
1193 /**
1194 * @}
1195 */
1196 #endif /* RCC_DCKCFGR_PLLI2SDIVR */
1197
1198 /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
1199 * @{
1200 */
1201 #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */
1202 #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */
1203 #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */
1204 #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */
1205 #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */
1206 #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */
1207 /**
1208 * @}
1209 */
1210
1211 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
1212 /** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
1213 * @{
1214 */
1215 #define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */
1216 #define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */
1217 #define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */
1218 #define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */
1219 /**
1220 * @}
1221 */
1222 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
1223 #endif /* RCC_PLLI2S_SUPPORT */
1224
1225 #if defined(RCC_PLLSAI_SUPPORT)
1226 /** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM)
1227 * @{
1228 */
1229 #if defined(RCC_PLLSAICFGR_PLLSAIM)
1230 #define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */
1231 #define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */
1232 #define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */
1233 #define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */
1234 #define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */
1235 #define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */
1236 #define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */
1237 #define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */
1238 #define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */
1239 #define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */
1240 #define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */
1241 #define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */
1242 #define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */
1243 #define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */
1244 #define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */
1245 #define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */
1246 #define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */
1247 #define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */
1248 #define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */
1249 #define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */
1250 #define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */
1251 #define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */
1252 #define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */
1253 #define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */
1254 #define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */
1255 #define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */
1256 #define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */
1257 #define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */
1258 #define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */
1259 #define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */
1260 #define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */
1261 #define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */
1262 #define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */
1263 #define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */
1264 #define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */
1265 #define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */
1266 #define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */
1267 #define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */
1268 #define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */
1269 #define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */
1270 #define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */
1271 #define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */
1272 #define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */
1273 #define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */
1274 #define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */
1275 #define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */
1276 #define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */
1277 #define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */
1278 #define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */
1279 #define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */
1280 #define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */
1281 #define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */
1282 #define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */
1283 #define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */
1284 #define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */
1285 #define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */
1286 #define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */
1287 #define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */
1288 #define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */
1289 #define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */
1290 #define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */
1291 #define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */
1292 #else
1293 #define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLSAI division factor for PLLSAIM output by 2 */
1294 #define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLSAI division factor for PLLSAIM output by 3 */
1295 #define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLSAI division factor for PLLSAIM output by 4 */
1296 #define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLSAI division factor for PLLSAIM output by 5 */
1297 #define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLSAI division factor for PLLSAIM output by 6 */
1298 #define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLSAI division factor for PLLSAIM output by 7 */
1299 #define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLSAI division factor for PLLSAIM output by 8 */
1300 #define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLSAI division factor for PLLSAIM output by 9 */
1301 #define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLSAI division factor for PLLSAIM output by 10 */
1302 #define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLSAI division factor for PLLSAIM output by 11 */
1303 #define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLSAI division factor for PLLSAIM output by 12 */
1304 #define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLSAI division factor for PLLSAIM output by 13 */
1305 #define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLSAI division factor for PLLSAIM output by 14 */
1306 #define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLSAI division factor for PLLSAIM output by 15 */
1307 #define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLSAI division factor for PLLSAIM output by 16 */
1308 #define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLSAI division factor for PLLSAIM output by 17 */
1309 #define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLSAI division factor for PLLSAIM output by 18 */
1310 #define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLSAI division factor for PLLSAIM output by 19 */
1311 #define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLSAI division factor for PLLSAIM output by 20 */
1312 #define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLSAI division factor for PLLSAIM output by 21 */
1313 #define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLSAI division factor for PLLSAIM output by 22 */
1314 #define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLSAI division factor for PLLSAIM output by 23 */
1315 #define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLSAI division factor for PLLSAIM output by 24 */
1316 #define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLSAI division factor for PLLSAIM output by 25 */
1317 #define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLSAI division factor for PLLSAIM output by 26 */
1318 #define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLSAI division factor for PLLSAIM output by 27 */
1319 #define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLSAI division factor for PLLSAIM output by 28 */
1320 #define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLSAI division factor for PLLSAIM output by 29 */
1321 #define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLSAI division factor for PLLSAIM output by 30 */
1322 #define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLSAI division factor for PLLSAIM output by 31 */
1323 #define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLSAI division factor for PLLSAIM output by 32 */
1324 #define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLSAI division factor for PLLSAIM output by 33 */
1325 #define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLSAI division factor for PLLSAIM output by 34 */
1326 #define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLSAI division factor for PLLSAIM output by 35 */
1327 #define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLSAI division factor for PLLSAIM output by 36 */
1328 #define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLSAI division factor for PLLSAIM output by 37 */
1329 #define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLSAI division factor for PLLSAIM output by 38 */
1330 #define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLSAI division factor for PLLSAIM output by 39 */
1331 #define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLSAI division factor for PLLSAIM output by 40 */
1332 #define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLSAI division factor for PLLSAIM output by 41 */
1333 #define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLSAI division factor for PLLSAIM output by 42 */
1334 #define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLSAI division factor for PLLSAIM output by 43 */
1335 #define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLSAI division factor for PLLSAIM output by 44 */
1336 #define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLSAI division factor for PLLSAIM output by 45 */
1337 #define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLSAI division factor for PLLSAIM output by 46 */
1338 #define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLSAI division factor for PLLSAIM output by 47 */
1339 #define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLSAI division factor for PLLSAIM output by 48 */
1340 #define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLSAI division factor for PLLSAIM output by 49 */
1341 #define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLSAI division factor for PLLSAIM output by 50 */
1342 #define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLSAI division factor for PLLSAIM output by 51 */
1343 #define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLSAI division factor for PLLSAIM output by 52 */
1344 #define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLSAI division factor for PLLSAIM output by 53 */
1345 #define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLSAI division factor for PLLSAIM output by 54 */
1346 #define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLSAI division factor for PLLSAIM output by 55 */
1347 #define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLSAI division factor for PLLSAIM output by 56 */
1348 #define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLSAI division factor for PLLSAIM output by 57 */
1349 #define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLSAI division factor for PLLSAIM output by 58 */
1350 #define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLSAI division factor for PLLSAIM output by 59 */
1351 #define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLSAI division factor for PLLSAIM output by 60 */
1352 #define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLSAI division factor for PLLSAIM output by 61 */
1353 #define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLSAI division factor for PLLSAIM output by 62 */
1354 #define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLSAI division factor for PLLSAIM output by 63 */
1355 #endif /* RCC_PLLSAICFGR_PLLSAIM */
1356 /**
1357 * @}
1358 */
1359
1360 /** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
1361 * @{
1362 */
1363 #define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */
1364 #define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */
1365 #define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */
1366 #define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */
1367 #define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */
1368 #define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */
1369 #define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */
1370 #define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */
1371 #define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */
1372 #define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */
1373 #define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */
1374 #define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */
1375 #define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */
1376 #define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */
1377 /**
1378 * @}
1379 */
1380
1381 #if defined(RCC_DCKCFGR_PLLSAIDIVQ)
1382 /** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
1383 * @{
1384 */
1385 #define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */
1386 #define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */
1387 #define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */
1388 #define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */
1389 #define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */
1390 #define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */
1391 #define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */
1392 #define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */
1393 #define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */
1394 #define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */
1395 #define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */
1396 #define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */
1397 #define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */
1398 #define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */
1399 #define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */
1400 #define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */
1401 #define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */
1402 #define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */
1403 #define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */
1404 #define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */
1405 #define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */
1406 #define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */
1407 #define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */
1408 #define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */
1409 #define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */
1410 #define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */
1411 #define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */
1412 #define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */
1413 #define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */
1414 #define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */
1415 #define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */
1416 #define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */
1417 /**
1418 * @}
1419 */
1420 #endif /* RCC_DCKCFGR_PLLSAIDIVQ */
1421
1422 #if defined(RCC_PLLSAICFGR_PLLSAIR)
1423 /** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
1424 * @{
1425 */
1426 #define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */
1427 #define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */
1428 #define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */
1429 #define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */
1430 #define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */
1431 #define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */
1432 /**
1433 * @}
1434 */
1435 #endif /* RCC_PLLSAICFGR_PLLSAIR */
1436
1437 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
1438 /** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
1439 * @{
1440 */
1441 #define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */
1442 #define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */
1443 #define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */
1444 #define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */
1445 /**
1446 * @}
1447 */
1448 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
1449
1450 #if defined(RCC_PLLSAICFGR_PLLSAIP)
1451 /** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
1452 * @{
1453 */
1454 #define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */
1455 #define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */
1456 #define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */
1457 #define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */
1458 /**
1459 * @}
1460 */
1461 #endif /* RCC_PLLSAICFGR_PLLSAIP */
1462 #endif /* RCC_PLLSAI_SUPPORT */
1463 /**
1464 * @}
1465 */
1466
1467 /* Exported macro ------------------------------------------------------------*/
1468 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1469 * @{
1470 */
1471
1472 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1473 * @{
1474 */
1475
1476 /**
1477 * @brief Write a value in RCC register
1478 * @param __REG__ Register to be written
1479 * @param __VALUE__ Value to be written in the register
1480 * @retval None
1481 */
1482 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1483
1484 /**
1485 * @brief Read a value in RCC register
1486 * @param __REG__ Register to be read
1487 * @retval Register value
1488 */
1489 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1490 /**
1491 * @}
1492 */
1493
1494 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1495 * @{
1496 */
1497
1498 /**
1499 * @brief Helper macro to calculate the PLLCLK frequency on system domain
1500 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1501 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
1502 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1503 * @param __PLLM__ This parameter can be one of the following values:
1504 * @arg @ref LL_RCC_PLLM_DIV_2
1505 * @arg @ref LL_RCC_PLLM_DIV_3
1506 * @arg @ref LL_RCC_PLLM_DIV_4
1507 * @arg @ref LL_RCC_PLLM_DIV_5
1508 * @arg @ref LL_RCC_PLLM_DIV_6
1509 * @arg @ref LL_RCC_PLLM_DIV_7
1510 * @arg @ref LL_RCC_PLLM_DIV_8
1511 * @arg @ref LL_RCC_PLLM_DIV_9
1512 * @arg @ref LL_RCC_PLLM_DIV_10
1513 * @arg @ref LL_RCC_PLLM_DIV_11
1514 * @arg @ref LL_RCC_PLLM_DIV_12
1515 * @arg @ref LL_RCC_PLLM_DIV_13
1516 * @arg @ref LL_RCC_PLLM_DIV_14
1517 * @arg @ref LL_RCC_PLLM_DIV_15
1518 * @arg @ref LL_RCC_PLLM_DIV_16
1519 * @arg @ref LL_RCC_PLLM_DIV_17
1520 * @arg @ref LL_RCC_PLLM_DIV_18
1521 * @arg @ref LL_RCC_PLLM_DIV_19
1522 * @arg @ref LL_RCC_PLLM_DIV_20
1523 * @arg @ref LL_RCC_PLLM_DIV_21
1524 * @arg @ref LL_RCC_PLLM_DIV_22
1525 * @arg @ref LL_RCC_PLLM_DIV_23
1526 * @arg @ref LL_RCC_PLLM_DIV_24
1527 * @arg @ref LL_RCC_PLLM_DIV_25
1528 * @arg @ref LL_RCC_PLLM_DIV_26
1529 * @arg @ref LL_RCC_PLLM_DIV_27
1530 * @arg @ref LL_RCC_PLLM_DIV_28
1531 * @arg @ref LL_RCC_PLLM_DIV_29
1532 * @arg @ref LL_RCC_PLLM_DIV_30
1533 * @arg @ref LL_RCC_PLLM_DIV_31
1534 * @arg @ref LL_RCC_PLLM_DIV_32
1535 * @arg @ref LL_RCC_PLLM_DIV_33
1536 * @arg @ref LL_RCC_PLLM_DIV_34
1537 * @arg @ref LL_RCC_PLLM_DIV_35
1538 * @arg @ref LL_RCC_PLLM_DIV_36
1539 * @arg @ref LL_RCC_PLLM_DIV_37
1540 * @arg @ref LL_RCC_PLLM_DIV_38
1541 * @arg @ref LL_RCC_PLLM_DIV_39
1542 * @arg @ref LL_RCC_PLLM_DIV_40
1543 * @arg @ref LL_RCC_PLLM_DIV_41
1544 * @arg @ref LL_RCC_PLLM_DIV_42
1545 * @arg @ref LL_RCC_PLLM_DIV_43
1546 * @arg @ref LL_RCC_PLLM_DIV_44
1547 * @arg @ref LL_RCC_PLLM_DIV_45
1548 * @arg @ref LL_RCC_PLLM_DIV_46
1549 * @arg @ref LL_RCC_PLLM_DIV_47
1550 * @arg @ref LL_RCC_PLLM_DIV_48
1551 * @arg @ref LL_RCC_PLLM_DIV_49
1552 * @arg @ref LL_RCC_PLLM_DIV_50
1553 * @arg @ref LL_RCC_PLLM_DIV_51
1554 * @arg @ref LL_RCC_PLLM_DIV_52
1555 * @arg @ref LL_RCC_PLLM_DIV_53
1556 * @arg @ref LL_RCC_PLLM_DIV_54
1557 * @arg @ref LL_RCC_PLLM_DIV_55
1558 * @arg @ref LL_RCC_PLLM_DIV_56
1559 * @arg @ref LL_RCC_PLLM_DIV_57
1560 * @arg @ref LL_RCC_PLLM_DIV_58
1561 * @arg @ref LL_RCC_PLLM_DIV_59
1562 * @arg @ref LL_RCC_PLLM_DIV_60
1563 * @arg @ref LL_RCC_PLLM_DIV_61
1564 * @arg @ref LL_RCC_PLLM_DIV_62
1565 * @arg @ref LL_RCC_PLLM_DIV_63
1566 * @param __PLLN__ Between 50/192(*) and 432
1567 *
1568 * (*) value not defined in all devices.
1569 * @param __PLLP__ This parameter can be one of the following values:
1570 * @arg @ref LL_RCC_PLLP_DIV_2
1571 * @arg @ref LL_RCC_PLLP_DIV_4
1572 * @arg @ref LL_RCC_PLLP_DIV_6
1573 * @arg @ref LL_RCC_PLLP_DIV_8
1574 * @retval PLL clock frequency (in Hz)
1575 */
1576 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1577 ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
1578
1579 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
1580 /**
1581 * @brief Helper macro to calculate the PLLRCLK frequency on system domain
1582 * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1583 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1584 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1585 * @param __PLLM__ This parameter can be one of the following values:
1586 * @arg @ref LL_RCC_PLLM_DIV_2
1587 * @arg @ref LL_RCC_PLLM_DIV_3
1588 * @arg @ref LL_RCC_PLLM_DIV_4
1589 * @arg @ref LL_RCC_PLLM_DIV_5
1590 * @arg @ref LL_RCC_PLLM_DIV_6
1591 * @arg @ref LL_RCC_PLLM_DIV_7
1592 * @arg @ref LL_RCC_PLLM_DIV_8
1593 * @arg @ref LL_RCC_PLLM_DIV_9
1594 * @arg @ref LL_RCC_PLLM_DIV_10
1595 * @arg @ref LL_RCC_PLLM_DIV_11
1596 * @arg @ref LL_RCC_PLLM_DIV_12
1597 * @arg @ref LL_RCC_PLLM_DIV_13
1598 * @arg @ref LL_RCC_PLLM_DIV_14
1599 * @arg @ref LL_RCC_PLLM_DIV_15
1600 * @arg @ref LL_RCC_PLLM_DIV_16
1601 * @arg @ref LL_RCC_PLLM_DIV_17
1602 * @arg @ref LL_RCC_PLLM_DIV_18
1603 * @arg @ref LL_RCC_PLLM_DIV_19
1604 * @arg @ref LL_RCC_PLLM_DIV_20
1605 * @arg @ref LL_RCC_PLLM_DIV_21
1606 * @arg @ref LL_RCC_PLLM_DIV_22
1607 * @arg @ref LL_RCC_PLLM_DIV_23
1608 * @arg @ref LL_RCC_PLLM_DIV_24
1609 * @arg @ref LL_RCC_PLLM_DIV_25
1610 * @arg @ref LL_RCC_PLLM_DIV_26
1611 * @arg @ref LL_RCC_PLLM_DIV_27
1612 * @arg @ref LL_RCC_PLLM_DIV_28
1613 * @arg @ref LL_RCC_PLLM_DIV_29
1614 * @arg @ref LL_RCC_PLLM_DIV_30
1615 * @arg @ref LL_RCC_PLLM_DIV_31
1616 * @arg @ref LL_RCC_PLLM_DIV_32
1617 * @arg @ref LL_RCC_PLLM_DIV_33
1618 * @arg @ref LL_RCC_PLLM_DIV_34
1619 * @arg @ref LL_RCC_PLLM_DIV_35
1620 * @arg @ref LL_RCC_PLLM_DIV_36
1621 * @arg @ref LL_RCC_PLLM_DIV_37
1622 * @arg @ref LL_RCC_PLLM_DIV_38
1623 * @arg @ref LL_RCC_PLLM_DIV_39
1624 * @arg @ref LL_RCC_PLLM_DIV_40
1625 * @arg @ref LL_RCC_PLLM_DIV_41
1626 * @arg @ref LL_RCC_PLLM_DIV_42
1627 * @arg @ref LL_RCC_PLLM_DIV_43
1628 * @arg @ref LL_RCC_PLLM_DIV_44
1629 * @arg @ref LL_RCC_PLLM_DIV_45
1630 * @arg @ref LL_RCC_PLLM_DIV_46
1631 * @arg @ref LL_RCC_PLLM_DIV_47
1632 * @arg @ref LL_RCC_PLLM_DIV_48
1633 * @arg @ref LL_RCC_PLLM_DIV_49
1634 * @arg @ref LL_RCC_PLLM_DIV_50
1635 * @arg @ref LL_RCC_PLLM_DIV_51
1636 * @arg @ref LL_RCC_PLLM_DIV_52
1637 * @arg @ref LL_RCC_PLLM_DIV_53
1638 * @arg @ref LL_RCC_PLLM_DIV_54
1639 * @arg @ref LL_RCC_PLLM_DIV_55
1640 * @arg @ref LL_RCC_PLLM_DIV_56
1641 * @arg @ref LL_RCC_PLLM_DIV_57
1642 * @arg @ref LL_RCC_PLLM_DIV_58
1643 * @arg @ref LL_RCC_PLLM_DIV_59
1644 * @arg @ref LL_RCC_PLLM_DIV_60
1645 * @arg @ref LL_RCC_PLLM_DIV_61
1646 * @arg @ref LL_RCC_PLLM_DIV_62
1647 * @arg @ref LL_RCC_PLLM_DIV_63
1648 * @param __PLLN__ Between 50 and 432
1649 * @param __PLLR__ This parameter can be one of the following values:
1650 * @arg @ref LL_RCC_PLLR_DIV_2
1651 * @arg @ref LL_RCC_PLLR_DIV_3
1652 * @arg @ref LL_RCC_PLLR_DIV_4
1653 * @arg @ref LL_RCC_PLLR_DIV_5
1654 * @arg @ref LL_RCC_PLLR_DIV_6
1655 * @arg @ref LL_RCC_PLLR_DIV_7
1656 * @retval PLL clock frequency (in Hz)
1657 */
1658 #define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1659 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1660
1661 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
1662
1663 /**
1664 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
1665 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1666 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1667 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1668 * @param __PLLM__ This parameter can be one of the following values:
1669 * @arg @ref LL_RCC_PLLM_DIV_2
1670 * @arg @ref LL_RCC_PLLM_DIV_3
1671 * @arg @ref LL_RCC_PLLM_DIV_4
1672 * @arg @ref LL_RCC_PLLM_DIV_5
1673 * @arg @ref LL_RCC_PLLM_DIV_6
1674 * @arg @ref LL_RCC_PLLM_DIV_7
1675 * @arg @ref LL_RCC_PLLM_DIV_8
1676 * @arg @ref LL_RCC_PLLM_DIV_9
1677 * @arg @ref LL_RCC_PLLM_DIV_10
1678 * @arg @ref LL_RCC_PLLM_DIV_11
1679 * @arg @ref LL_RCC_PLLM_DIV_12
1680 * @arg @ref LL_RCC_PLLM_DIV_13
1681 * @arg @ref LL_RCC_PLLM_DIV_14
1682 * @arg @ref LL_RCC_PLLM_DIV_15
1683 * @arg @ref LL_RCC_PLLM_DIV_16
1684 * @arg @ref LL_RCC_PLLM_DIV_17
1685 * @arg @ref LL_RCC_PLLM_DIV_18
1686 * @arg @ref LL_RCC_PLLM_DIV_19
1687 * @arg @ref LL_RCC_PLLM_DIV_20
1688 * @arg @ref LL_RCC_PLLM_DIV_21
1689 * @arg @ref LL_RCC_PLLM_DIV_22
1690 * @arg @ref LL_RCC_PLLM_DIV_23
1691 * @arg @ref LL_RCC_PLLM_DIV_24
1692 * @arg @ref LL_RCC_PLLM_DIV_25
1693 * @arg @ref LL_RCC_PLLM_DIV_26
1694 * @arg @ref LL_RCC_PLLM_DIV_27
1695 * @arg @ref LL_RCC_PLLM_DIV_28
1696 * @arg @ref LL_RCC_PLLM_DIV_29
1697 * @arg @ref LL_RCC_PLLM_DIV_30
1698 * @arg @ref LL_RCC_PLLM_DIV_31
1699 * @arg @ref LL_RCC_PLLM_DIV_32
1700 * @arg @ref LL_RCC_PLLM_DIV_33
1701 * @arg @ref LL_RCC_PLLM_DIV_34
1702 * @arg @ref LL_RCC_PLLM_DIV_35
1703 * @arg @ref LL_RCC_PLLM_DIV_36
1704 * @arg @ref LL_RCC_PLLM_DIV_37
1705 * @arg @ref LL_RCC_PLLM_DIV_38
1706 * @arg @ref LL_RCC_PLLM_DIV_39
1707 * @arg @ref LL_RCC_PLLM_DIV_40
1708 * @arg @ref LL_RCC_PLLM_DIV_41
1709 * @arg @ref LL_RCC_PLLM_DIV_42
1710 * @arg @ref LL_RCC_PLLM_DIV_43
1711 * @arg @ref LL_RCC_PLLM_DIV_44
1712 * @arg @ref LL_RCC_PLLM_DIV_45
1713 * @arg @ref LL_RCC_PLLM_DIV_46
1714 * @arg @ref LL_RCC_PLLM_DIV_47
1715 * @arg @ref LL_RCC_PLLM_DIV_48
1716 * @arg @ref LL_RCC_PLLM_DIV_49
1717 * @arg @ref LL_RCC_PLLM_DIV_50
1718 * @arg @ref LL_RCC_PLLM_DIV_51
1719 * @arg @ref LL_RCC_PLLM_DIV_52
1720 * @arg @ref LL_RCC_PLLM_DIV_53
1721 * @arg @ref LL_RCC_PLLM_DIV_54
1722 * @arg @ref LL_RCC_PLLM_DIV_55
1723 * @arg @ref LL_RCC_PLLM_DIV_56
1724 * @arg @ref LL_RCC_PLLM_DIV_57
1725 * @arg @ref LL_RCC_PLLM_DIV_58
1726 * @arg @ref LL_RCC_PLLM_DIV_59
1727 * @arg @ref LL_RCC_PLLM_DIV_60
1728 * @arg @ref LL_RCC_PLLM_DIV_61
1729 * @arg @ref LL_RCC_PLLM_DIV_62
1730 * @arg @ref LL_RCC_PLLM_DIV_63
1731 * @param __PLLN__ Between 50/192(*) and 432
1732 *
1733 * (*) value not defined in all devices.
1734 * @param __PLLQ__ This parameter can be one of the following values:
1735 * @arg @ref LL_RCC_PLLQ_DIV_2
1736 * @arg @ref LL_RCC_PLLQ_DIV_3
1737 * @arg @ref LL_RCC_PLLQ_DIV_4
1738 * @arg @ref LL_RCC_PLLQ_DIV_5
1739 * @arg @ref LL_RCC_PLLQ_DIV_6
1740 * @arg @ref LL_RCC_PLLQ_DIV_7
1741 * @arg @ref LL_RCC_PLLQ_DIV_8
1742 * @arg @ref LL_RCC_PLLQ_DIV_9
1743 * @arg @ref LL_RCC_PLLQ_DIV_10
1744 * @arg @ref LL_RCC_PLLQ_DIV_11
1745 * @arg @ref LL_RCC_PLLQ_DIV_12
1746 * @arg @ref LL_RCC_PLLQ_DIV_13
1747 * @arg @ref LL_RCC_PLLQ_DIV_14
1748 * @arg @ref LL_RCC_PLLQ_DIV_15
1749 * @retval PLL clock frequency (in Hz)
1750 */
1751 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1752 ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
1753
1754 #if defined(DSI)
1755 /**
1756 * @brief Helper macro to calculate the PLLCLK frequency used on DSI
1757 * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1758 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1759 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1760 * @param __PLLM__ This parameter can be one of the following values:
1761 * @arg @ref LL_RCC_PLLM_DIV_2
1762 * @arg @ref LL_RCC_PLLM_DIV_3
1763 * @arg @ref LL_RCC_PLLM_DIV_4
1764 * @arg @ref LL_RCC_PLLM_DIV_5
1765 * @arg @ref LL_RCC_PLLM_DIV_6
1766 * @arg @ref LL_RCC_PLLM_DIV_7
1767 * @arg @ref LL_RCC_PLLM_DIV_8
1768 * @arg @ref LL_RCC_PLLM_DIV_9
1769 * @arg @ref LL_RCC_PLLM_DIV_10
1770 * @arg @ref LL_RCC_PLLM_DIV_11
1771 * @arg @ref LL_RCC_PLLM_DIV_12
1772 * @arg @ref LL_RCC_PLLM_DIV_13
1773 * @arg @ref LL_RCC_PLLM_DIV_14
1774 * @arg @ref LL_RCC_PLLM_DIV_15
1775 * @arg @ref LL_RCC_PLLM_DIV_16
1776 * @arg @ref LL_RCC_PLLM_DIV_17
1777 * @arg @ref LL_RCC_PLLM_DIV_18
1778 * @arg @ref LL_RCC_PLLM_DIV_19
1779 * @arg @ref LL_RCC_PLLM_DIV_20
1780 * @arg @ref LL_RCC_PLLM_DIV_21
1781 * @arg @ref LL_RCC_PLLM_DIV_22
1782 * @arg @ref LL_RCC_PLLM_DIV_23
1783 * @arg @ref LL_RCC_PLLM_DIV_24
1784 * @arg @ref LL_RCC_PLLM_DIV_25
1785 * @arg @ref LL_RCC_PLLM_DIV_26
1786 * @arg @ref LL_RCC_PLLM_DIV_27
1787 * @arg @ref LL_RCC_PLLM_DIV_28
1788 * @arg @ref LL_RCC_PLLM_DIV_29
1789 * @arg @ref LL_RCC_PLLM_DIV_30
1790 * @arg @ref LL_RCC_PLLM_DIV_31
1791 * @arg @ref LL_RCC_PLLM_DIV_32
1792 * @arg @ref LL_RCC_PLLM_DIV_33
1793 * @arg @ref LL_RCC_PLLM_DIV_34
1794 * @arg @ref LL_RCC_PLLM_DIV_35
1795 * @arg @ref LL_RCC_PLLM_DIV_36
1796 * @arg @ref LL_RCC_PLLM_DIV_37
1797 * @arg @ref LL_RCC_PLLM_DIV_38
1798 * @arg @ref LL_RCC_PLLM_DIV_39
1799 * @arg @ref LL_RCC_PLLM_DIV_40
1800 * @arg @ref LL_RCC_PLLM_DIV_41
1801 * @arg @ref LL_RCC_PLLM_DIV_42
1802 * @arg @ref LL_RCC_PLLM_DIV_43
1803 * @arg @ref LL_RCC_PLLM_DIV_44
1804 * @arg @ref LL_RCC_PLLM_DIV_45
1805 * @arg @ref LL_RCC_PLLM_DIV_46
1806 * @arg @ref LL_RCC_PLLM_DIV_47
1807 * @arg @ref LL_RCC_PLLM_DIV_48
1808 * @arg @ref LL_RCC_PLLM_DIV_49
1809 * @arg @ref LL_RCC_PLLM_DIV_50
1810 * @arg @ref LL_RCC_PLLM_DIV_51
1811 * @arg @ref LL_RCC_PLLM_DIV_52
1812 * @arg @ref LL_RCC_PLLM_DIV_53
1813 * @arg @ref LL_RCC_PLLM_DIV_54
1814 * @arg @ref LL_RCC_PLLM_DIV_55
1815 * @arg @ref LL_RCC_PLLM_DIV_56
1816 * @arg @ref LL_RCC_PLLM_DIV_57
1817 * @arg @ref LL_RCC_PLLM_DIV_58
1818 * @arg @ref LL_RCC_PLLM_DIV_59
1819 * @arg @ref LL_RCC_PLLM_DIV_60
1820 * @arg @ref LL_RCC_PLLM_DIV_61
1821 * @arg @ref LL_RCC_PLLM_DIV_62
1822 * @arg @ref LL_RCC_PLLM_DIV_63
1823 * @param __PLLN__ Between 50 and 432
1824 * @param __PLLR__ This parameter can be one of the following values:
1825 * @arg @ref LL_RCC_PLLR_DIV_2
1826 * @arg @ref LL_RCC_PLLR_DIV_3
1827 * @arg @ref LL_RCC_PLLR_DIV_4
1828 * @arg @ref LL_RCC_PLLR_DIV_5
1829 * @arg @ref LL_RCC_PLLR_DIV_6
1830 * @arg @ref LL_RCC_PLLR_DIV_7
1831 * @retval PLL clock frequency (in Hz)
1832 */
1833 #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1834 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1835 #endif /* DSI */
1836
1837 #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
1838 /**
1839 * @brief Helper macro to calculate the PLLCLK frequency used on I2S
1840 * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1841 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1842 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1843 * @param __PLLM__ This parameter can be one of the following values:
1844 * @arg @ref LL_RCC_PLLM_DIV_2
1845 * @arg @ref LL_RCC_PLLM_DIV_3
1846 * @arg @ref LL_RCC_PLLM_DIV_4
1847 * @arg @ref LL_RCC_PLLM_DIV_5
1848 * @arg @ref LL_RCC_PLLM_DIV_6
1849 * @arg @ref LL_RCC_PLLM_DIV_7
1850 * @arg @ref LL_RCC_PLLM_DIV_8
1851 * @arg @ref LL_RCC_PLLM_DIV_9
1852 * @arg @ref LL_RCC_PLLM_DIV_10
1853 * @arg @ref LL_RCC_PLLM_DIV_11
1854 * @arg @ref LL_RCC_PLLM_DIV_12
1855 * @arg @ref LL_RCC_PLLM_DIV_13
1856 * @arg @ref LL_RCC_PLLM_DIV_14
1857 * @arg @ref LL_RCC_PLLM_DIV_15
1858 * @arg @ref LL_RCC_PLLM_DIV_16
1859 * @arg @ref LL_RCC_PLLM_DIV_17
1860 * @arg @ref LL_RCC_PLLM_DIV_18
1861 * @arg @ref LL_RCC_PLLM_DIV_19
1862 * @arg @ref LL_RCC_PLLM_DIV_20
1863 * @arg @ref LL_RCC_PLLM_DIV_21
1864 * @arg @ref LL_RCC_PLLM_DIV_22
1865 * @arg @ref LL_RCC_PLLM_DIV_23
1866 * @arg @ref LL_RCC_PLLM_DIV_24
1867 * @arg @ref LL_RCC_PLLM_DIV_25
1868 * @arg @ref LL_RCC_PLLM_DIV_26
1869 * @arg @ref LL_RCC_PLLM_DIV_27
1870 * @arg @ref LL_RCC_PLLM_DIV_28
1871 * @arg @ref LL_RCC_PLLM_DIV_29
1872 * @arg @ref LL_RCC_PLLM_DIV_30
1873 * @arg @ref LL_RCC_PLLM_DIV_31
1874 * @arg @ref LL_RCC_PLLM_DIV_32
1875 * @arg @ref LL_RCC_PLLM_DIV_33
1876 * @arg @ref LL_RCC_PLLM_DIV_34
1877 * @arg @ref LL_RCC_PLLM_DIV_35
1878 * @arg @ref LL_RCC_PLLM_DIV_36
1879 * @arg @ref LL_RCC_PLLM_DIV_37
1880 * @arg @ref LL_RCC_PLLM_DIV_38
1881 * @arg @ref LL_RCC_PLLM_DIV_39
1882 * @arg @ref LL_RCC_PLLM_DIV_40
1883 * @arg @ref LL_RCC_PLLM_DIV_41
1884 * @arg @ref LL_RCC_PLLM_DIV_42
1885 * @arg @ref LL_RCC_PLLM_DIV_43
1886 * @arg @ref LL_RCC_PLLM_DIV_44
1887 * @arg @ref LL_RCC_PLLM_DIV_45
1888 * @arg @ref LL_RCC_PLLM_DIV_46
1889 * @arg @ref LL_RCC_PLLM_DIV_47
1890 * @arg @ref LL_RCC_PLLM_DIV_48
1891 * @arg @ref LL_RCC_PLLM_DIV_49
1892 * @arg @ref LL_RCC_PLLM_DIV_50
1893 * @arg @ref LL_RCC_PLLM_DIV_51
1894 * @arg @ref LL_RCC_PLLM_DIV_52
1895 * @arg @ref LL_RCC_PLLM_DIV_53
1896 * @arg @ref LL_RCC_PLLM_DIV_54
1897 * @arg @ref LL_RCC_PLLM_DIV_55
1898 * @arg @ref LL_RCC_PLLM_DIV_56
1899 * @arg @ref LL_RCC_PLLM_DIV_57
1900 * @arg @ref LL_RCC_PLLM_DIV_58
1901 * @arg @ref LL_RCC_PLLM_DIV_59
1902 * @arg @ref LL_RCC_PLLM_DIV_60
1903 * @arg @ref LL_RCC_PLLM_DIV_61
1904 * @arg @ref LL_RCC_PLLM_DIV_62
1905 * @arg @ref LL_RCC_PLLM_DIV_63
1906 * @param __PLLN__ Between 50 and 432
1907 * @param __PLLR__ This parameter can be one of the following values:
1908 * @arg @ref LL_RCC_PLLR_DIV_2
1909 * @arg @ref LL_RCC_PLLR_DIV_3
1910 * @arg @ref LL_RCC_PLLR_DIV_4
1911 * @arg @ref LL_RCC_PLLR_DIV_5
1912 * @arg @ref LL_RCC_PLLR_DIV_6
1913 * @arg @ref LL_RCC_PLLR_DIV_7
1914 * @retval PLL clock frequency (in Hz)
1915 */
1916 #define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1917 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1918 #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
1919
1920 #if defined(SPDIFRX)
1921 /**
1922 * @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX
1923 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1924 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1925 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1926 * @param __PLLM__ This parameter can be one of the following values:
1927 * @arg @ref LL_RCC_PLLM_DIV_2
1928 * @arg @ref LL_RCC_PLLM_DIV_3
1929 * @arg @ref LL_RCC_PLLM_DIV_4
1930 * @arg @ref LL_RCC_PLLM_DIV_5
1931 * @arg @ref LL_RCC_PLLM_DIV_6
1932 * @arg @ref LL_RCC_PLLM_DIV_7
1933 * @arg @ref LL_RCC_PLLM_DIV_8
1934 * @arg @ref LL_RCC_PLLM_DIV_9
1935 * @arg @ref LL_RCC_PLLM_DIV_10
1936 * @arg @ref LL_RCC_PLLM_DIV_11
1937 * @arg @ref LL_RCC_PLLM_DIV_12
1938 * @arg @ref LL_RCC_PLLM_DIV_13
1939 * @arg @ref LL_RCC_PLLM_DIV_14
1940 * @arg @ref LL_RCC_PLLM_DIV_15
1941 * @arg @ref LL_RCC_PLLM_DIV_16
1942 * @arg @ref LL_RCC_PLLM_DIV_17
1943 * @arg @ref LL_RCC_PLLM_DIV_18
1944 * @arg @ref LL_RCC_PLLM_DIV_19
1945 * @arg @ref LL_RCC_PLLM_DIV_20
1946 * @arg @ref LL_RCC_PLLM_DIV_21
1947 * @arg @ref LL_RCC_PLLM_DIV_22
1948 * @arg @ref LL_RCC_PLLM_DIV_23
1949 * @arg @ref LL_RCC_PLLM_DIV_24
1950 * @arg @ref LL_RCC_PLLM_DIV_25
1951 * @arg @ref LL_RCC_PLLM_DIV_26
1952 * @arg @ref LL_RCC_PLLM_DIV_27
1953 * @arg @ref LL_RCC_PLLM_DIV_28
1954 * @arg @ref LL_RCC_PLLM_DIV_29
1955 * @arg @ref LL_RCC_PLLM_DIV_30
1956 * @arg @ref LL_RCC_PLLM_DIV_31
1957 * @arg @ref LL_RCC_PLLM_DIV_32
1958 * @arg @ref LL_RCC_PLLM_DIV_33
1959 * @arg @ref LL_RCC_PLLM_DIV_34
1960 * @arg @ref LL_RCC_PLLM_DIV_35
1961 * @arg @ref LL_RCC_PLLM_DIV_36
1962 * @arg @ref LL_RCC_PLLM_DIV_37
1963 * @arg @ref LL_RCC_PLLM_DIV_38
1964 * @arg @ref LL_RCC_PLLM_DIV_39
1965 * @arg @ref LL_RCC_PLLM_DIV_40
1966 * @arg @ref LL_RCC_PLLM_DIV_41
1967 * @arg @ref LL_RCC_PLLM_DIV_42
1968 * @arg @ref LL_RCC_PLLM_DIV_43
1969 * @arg @ref LL_RCC_PLLM_DIV_44
1970 * @arg @ref LL_RCC_PLLM_DIV_45
1971 * @arg @ref LL_RCC_PLLM_DIV_46
1972 * @arg @ref LL_RCC_PLLM_DIV_47
1973 * @arg @ref LL_RCC_PLLM_DIV_48
1974 * @arg @ref LL_RCC_PLLM_DIV_49
1975 * @arg @ref LL_RCC_PLLM_DIV_50
1976 * @arg @ref LL_RCC_PLLM_DIV_51
1977 * @arg @ref LL_RCC_PLLM_DIV_52
1978 * @arg @ref LL_RCC_PLLM_DIV_53
1979 * @arg @ref LL_RCC_PLLM_DIV_54
1980 * @arg @ref LL_RCC_PLLM_DIV_55
1981 * @arg @ref LL_RCC_PLLM_DIV_56
1982 * @arg @ref LL_RCC_PLLM_DIV_57
1983 * @arg @ref LL_RCC_PLLM_DIV_58
1984 * @arg @ref LL_RCC_PLLM_DIV_59
1985 * @arg @ref LL_RCC_PLLM_DIV_60
1986 * @arg @ref LL_RCC_PLLM_DIV_61
1987 * @arg @ref LL_RCC_PLLM_DIV_62
1988 * @arg @ref LL_RCC_PLLM_DIV_63
1989 * @param __PLLN__ Between 50 and 432
1990 * @param __PLLR__ This parameter can be one of the following values:
1991 * @arg @ref LL_RCC_PLLR_DIV_2
1992 * @arg @ref LL_RCC_PLLR_DIV_3
1993 * @arg @ref LL_RCC_PLLR_DIV_4
1994 * @arg @ref LL_RCC_PLLR_DIV_5
1995 * @arg @ref LL_RCC_PLLR_DIV_6
1996 * @arg @ref LL_RCC_PLLR_DIV_7
1997 * @retval PLL clock frequency (in Hz)
1998 */
1999 #define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2000 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
2001 #endif /* SPDIFRX */
2002
2003 #if defined(RCC_PLLCFGR_PLLR)
2004 #if defined(SAI1)
2005 /**
2006 * @brief Helper macro to calculate the PLLCLK frequency used on SAI
2007 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
2008 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());
2009 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2010 * @param __PLLM__ This parameter can be one of the following values:
2011 * @arg @ref LL_RCC_PLLM_DIV_2
2012 * @arg @ref LL_RCC_PLLM_DIV_3
2013 * @arg @ref LL_RCC_PLLM_DIV_4
2014 * @arg @ref LL_RCC_PLLM_DIV_5
2015 * @arg @ref LL_RCC_PLLM_DIV_6
2016 * @arg @ref LL_RCC_PLLM_DIV_7
2017 * @arg @ref LL_RCC_PLLM_DIV_8
2018 * @arg @ref LL_RCC_PLLM_DIV_9
2019 * @arg @ref LL_RCC_PLLM_DIV_10
2020 * @arg @ref LL_RCC_PLLM_DIV_11
2021 * @arg @ref LL_RCC_PLLM_DIV_12
2022 * @arg @ref LL_RCC_PLLM_DIV_13
2023 * @arg @ref LL_RCC_PLLM_DIV_14
2024 * @arg @ref LL_RCC_PLLM_DIV_15
2025 * @arg @ref LL_RCC_PLLM_DIV_16
2026 * @arg @ref LL_RCC_PLLM_DIV_17
2027 * @arg @ref LL_RCC_PLLM_DIV_18
2028 * @arg @ref LL_RCC_PLLM_DIV_19
2029 * @arg @ref LL_RCC_PLLM_DIV_20
2030 * @arg @ref LL_RCC_PLLM_DIV_21
2031 * @arg @ref LL_RCC_PLLM_DIV_22
2032 * @arg @ref LL_RCC_PLLM_DIV_23
2033 * @arg @ref LL_RCC_PLLM_DIV_24
2034 * @arg @ref LL_RCC_PLLM_DIV_25
2035 * @arg @ref LL_RCC_PLLM_DIV_26
2036 * @arg @ref LL_RCC_PLLM_DIV_27
2037 * @arg @ref LL_RCC_PLLM_DIV_28
2038 * @arg @ref LL_RCC_PLLM_DIV_29
2039 * @arg @ref LL_RCC_PLLM_DIV_30
2040 * @arg @ref LL_RCC_PLLM_DIV_31
2041 * @arg @ref LL_RCC_PLLM_DIV_32
2042 * @arg @ref LL_RCC_PLLM_DIV_33
2043 * @arg @ref LL_RCC_PLLM_DIV_34
2044 * @arg @ref LL_RCC_PLLM_DIV_35
2045 * @arg @ref LL_RCC_PLLM_DIV_36
2046 * @arg @ref LL_RCC_PLLM_DIV_37
2047 * @arg @ref LL_RCC_PLLM_DIV_38
2048 * @arg @ref LL_RCC_PLLM_DIV_39
2049 * @arg @ref LL_RCC_PLLM_DIV_40
2050 * @arg @ref LL_RCC_PLLM_DIV_41
2051 * @arg @ref LL_RCC_PLLM_DIV_42
2052 * @arg @ref LL_RCC_PLLM_DIV_43
2053 * @arg @ref LL_RCC_PLLM_DIV_44
2054 * @arg @ref LL_RCC_PLLM_DIV_45
2055 * @arg @ref LL_RCC_PLLM_DIV_46
2056 * @arg @ref LL_RCC_PLLM_DIV_47
2057 * @arg @ref LL_RCC_PLLM_DIV_48
2058 * @arg @ref LL_RCC_PLLM_DIV_49
2059 * @arg @ref LL_RCC_PLLM_DIV_50
2060 * @arg @ref LL_RCC_PLLM_DIV_51
2061 * @arg @ref LL_RCC_PLLM_DIV_52
2062 * @arg @ref LL_RCC_PLLM_DIV_53
2063 * @arg @ref LL_RCC_PLLM_DIV_54
2064 * @arg @ref LL_RCC_PLLM_DIV_55
2065 * @arg @ref LL_RCC_PLLM_DIV_56
2066 * @arg @ref LL_RCC_PLLM_DIV_57
2067 * @arg @ref LL_RCC_PLLM_DIV_58
2068 * @arg @ref LL_RCC_PLLM_DIV_59
2069 * @arg @ref LL_RCC_PLLM_DIV_60
2070 * @arg @ref LL_RCC_PLLM_DIV_61
2071 * @arg @ref LL_RCC_PLLM_DIV_62
2072 * @arg @ref LL_RCC_PLLM_DIV_63
2073 * @param __PLLN__ Between 50 and 432
2074 * @param __PLLR__ This parameter can be one of the following values:
2075 * @arg @ref LL_RCC_PLLR_DIV_2
2076 * @arg @ref LL_RCC_PLLR_DIV_3
2077 * @arg @ref LL_RCC_PLLR_DIV_4
2078 * @arg @ref LL_RCC_PLLR_DIV_5
2079 * @arg @ref LL_RCC_PLLR_DIV_6
2080 * @arg @ref LL_RCC_PLLR_DIV_7
2081 * @param __PLLDIVR__ This parameter can be one of the following values:
2082 * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
2083 * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
2084 * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
2085 * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
2086 * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
2087 * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
2088 * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
2089 * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
2090 * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
2091 * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
2092 * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
2093 * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
2094 * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
2095 * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
2096 * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
2097 * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
2098 * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
2099 * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
2100 * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
2101 * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
2102 * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
2103 * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
2104 * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
2105 * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
2106 * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
2107 * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
2108 * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
2109 * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
2110 * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
2111 * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
2112 * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
2113 *
2114 * (*) value not defined in all devices.
2115 * @retval PLL clock frequency (in Hz)
2116 */
2117 #if defined(RCC_DCKCFGR_PLLDIVR)
2118 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2119 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
2120 #else
2121 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2122 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
2123 #endif /* RCC_DCKCFGR_PLLDIVR */
2124 #endif /* SAI1 */
2125 #endif /* RCC_PLLCFGR_PLLR */
2126
2127 #if defined(RCC_PLLSAI_SUPPORT)
2128 /**
2129 * @brief Helper macro to calculate the PLLSAI frequency used for SAI domain
2130 * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2131 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
2132 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2133 * @param __PLLM__ This parameter can be one of the following values:
2134 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2135 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2136 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2137 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2138 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2139 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2140 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2141 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2142 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2143 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2144 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2145 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2146 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2147 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2148 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2149 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2150 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2151 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2152 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2153 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2154 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2155 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2156 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2157 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2158 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2159 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2160 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2161 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2162 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2163 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2164 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2165 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2166 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2167 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2168 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2169 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2170 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2171 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2172 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2173 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2174 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2175 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2176 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2177 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2178 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2179 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2180 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2181 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2182 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2183 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2184 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2185 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2186 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2187 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2188 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2189 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2190 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2191 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2192 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2193 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2194 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2195 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2196 * @param __PLLSAIN__ Between 49/50(*) and 432
2197 *
2198 * (*) value not defined in all devices.
2199 * @param __PLLSAIQ__ This parameter can be one of the following values:
2200 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
2201 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
2202 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
2203 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
2204 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
2205 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
2206 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
2207 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
2208 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
2209 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
2210 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
2211 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
2212 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
2213 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
2214 * @param __PLLSAIDIVQ__ This parameter can be one of the following values:
2215 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
2216 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
2217 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
2218 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
2219 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
2220 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
2221 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
2222 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
2223 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
2224 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
2225 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
2226 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
2227 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
2228 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
2229 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
2230 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
2231 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
2232 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
2233 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
2234 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
2235 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
2236 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
2237 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
2238 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
2239 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
2240 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
2241 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
2242 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
2243 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
2244 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
2245 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
2246 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
2247 * @retval PLLSAI clock frequency (in Hz)
2248 */
2249 #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2250 (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))
2251
2252 #if defined(RCC_PLLSAICFGR_PLLSAIP)
2253 /**
2254 * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
2255 * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2256 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
2257 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2258 * @param __PLLM__ This parameter can be one of the following values:
2259 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2260 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2261 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2262 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2263 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2264 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2265 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2266 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2267 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2268 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2269 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2270 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2271 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2272 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2273 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2274 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2275 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2276 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2277 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2278 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2279 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2280 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2281 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2282 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2283 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2284 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2285 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2286 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2287 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2288 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2289 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2290 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2291 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2292 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2293 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2294 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2295 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2296 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2297 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2298 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2299 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2300 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2301 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2302 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2303 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2304 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2305 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2306 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2307 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2308 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2309 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2310 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2311 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2312 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2313 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2314 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2315 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2316 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2317 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2318 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2319 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2320 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2321 * @param __PLLSAIN__ Between 50 and 432
2322 * @param __PLLSAIP__ This parameter can be one of the following values:
2323 * @arg @ref LL_RCC_PLLSAIP_DIV_2
2324 * @arg @ref LL_RCC_PLLSAIP_DIV_4
2325 * @arg @ref LL_RCC_PLLSAIP_DIV_6
2326 * @arg @ref LL_RCC_PLLSAIP_DIV_8
2327 * @retval PLLSAI clock frequency (in Hz)
2328 */
2329 #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2330 ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))
2331 #endif /* RCC_PLLSAICFGR_PLLSAIP */
2332
2333 #if defined(LTDC)
2334 /**
2335 * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
2336 * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2337 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
2338 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2339 * @param __PLLM__ This parameter can be one of the following values:
2340 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2341 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2342 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2343 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2344 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2345 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2346 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2347 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2348 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2349 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2350 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2351 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2352 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2353 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2354 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2355 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2356 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2357 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2358 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2359 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2360 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2361 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2362 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2363 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2364 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2365 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2366 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2367 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2368 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2369 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2370 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2371 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2372 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2373 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2374 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2375 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2376 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2377 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2378 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2379 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2380 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2381 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2382 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2383 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2384 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2385 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2386 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2387 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2388 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2389 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2390 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2391 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2392 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2393 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2394 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2395 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2396 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2397 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2398 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2399 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2400 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2401 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2402 * @param __PLLSAIN__ Between 49/50(*) and 432
2403 *
2404 * (*) value not defined in all devices.
2405 * @param __PLLSAIR__ This parameter can be one of the following values:
2406 * @arg @ref LL_RCC_PLLSAIR_DIV_2
2407 * @arg @ref LL_RCC_PLLSAIR_DIV_3
2408 * @arg @ref LL_RCC_PLLSAIR_DIV_4
2409 * @arg @ref LL_RCC_PLLSAIR_DIV_5
2410 * @arg @ref LL_RCC_PLLSAIR_DIV_6
2411 * @arg @ref LL_RCC_PLLSAIR_DIV_7
2412 * @param __PLLSAIDIVR__ This parameter can be one of the following values:
2413 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
2414 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
2415 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
2416 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
2417 * @retval PLLSAI clock frequency (in Hz)
2418 */
2419 #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2420 (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))
2421 #endif /* LTDC */
2422 #endif /* RCC_PLLSAI_SUPPORT */
2423
2424 #if defined(RCC_PLLI2S_SUPPORT)
2425 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)
2426 /**
2427 * @brief Helper macro to calculate the PLLI2S frequency used for SAI domain
2428 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2429 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
2430 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2431 * @param __PLLM__ This parameter can be one of the following values:
2432 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2433 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2434 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2435 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2436 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2437 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2438 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2439 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2440 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2441 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2442 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2443 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2444 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2445 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2446 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2447 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2448 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2449 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2450 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2451 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2452 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2453 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2454 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2455 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2456 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2457 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2458 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2459 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2460 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2461 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2462 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2463 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2464 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2465 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2466 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2467 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2468 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2469 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2470 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2471 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2472 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2473 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2474 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2475 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2476 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2477 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2478 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2479 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2480 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2481 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2482 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2483 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2484 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2485 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2486 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2487 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2488 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2489 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2490 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2491 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2492 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2493 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2494 * @param __PLLI2SN__ Between 50/192(*) and 432
2495 *
2496 * (*) value not defined in all devices.
2497 * @param __PLLI2SQ_R__ This parameter can be one of the following values:
2498 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
2499 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
2500 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
2501 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
2502 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
2503 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
2504 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
2505 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
2506 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
2507 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
2508 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
2509 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
2510 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
2511 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
2512 * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
2513 * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
2514 * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
2515 * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
2516 * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
2517 * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
2518 *
2519 * (*) value not defined in all devices.
2520 * @param __PLLI2SDIVQ_R__ This parameter can be one of the following values:
2521 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
2522 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
2523 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
2524 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
2525 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
2526 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
2527 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
2528 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
2529 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
2530 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
2531 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
2532 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
2533 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
2534 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
2535 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
2536 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
2537 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
2538 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
2539 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
2540 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
2541 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
2542 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
2543 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
2544 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
2545 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
2546 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
2547 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
2548 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
2549 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
2550 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
2551 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
2552 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
2553 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
2554 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
2555 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
2556 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
2557 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
2558 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
2559 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
2560 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
2561 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
2562 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
2563 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
2564 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
2565 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
2566 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
2567 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
2568 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
2569 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
2570 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
2571 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
2572 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
2573 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
2574 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
2575 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
2576 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
2577 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
2578 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
2579 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
2580 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
2581 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
2582 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
2583 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
2584 *
2585 * (*) value not defined in all devices.
2586 * @retval PLLI2S clock frequency (in Hz)
2587 */
2588 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
2589 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2590 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))
2591 #else
2592 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2593 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))
2594
2595 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
2596 #endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */
2597
2598 #if defined(SPDIFRX)
2599 /**
2600 * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
2601 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2602 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
2603 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2604 * @param __PLLM__ This parameter can be one of the following values:
2605 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2606 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2607 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2608 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2609 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2610 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2611 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2612 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2613 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2614 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2615 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2616 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2617 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2618 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2619 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2620 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2621 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2622 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2623 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2624 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2625 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2626 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2627 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2628 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2629 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2630 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2631 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2632 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2633 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2634 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2635 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2636 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2637 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2638 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2639 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2640 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2641 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2642 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2643 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2644 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2645 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2646 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2647 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2648 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2649 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2650 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2651 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2652 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2653 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2654 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2655 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2656 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2657 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2658 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2659 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2660 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2661 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2662 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2663 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2664 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2665 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2666 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2667 * @param __PLLI2SN__ Between 50 and 432
2668 * @param __PLLI2SP__ This parameter can be one of the following values:
2669 * @arg @ref LL_RCC_PLLI2SP_DIV_2
2670 * @arg @ref LL_RCC_PLLI2SP_DIV_4
2671 * @arg @ref LL_RCC_PLLI2SP_DIV_6
2672 * @arg @ref LL_RCC_PLLI2SP_DIV_8
2673 * @retval PLLI2S clock frequency (in Hz)
2674 */
2675 #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2676 ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
2677
2678 #endif /* SPDIFRX */
2679
2680 /**
2681 * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
2682 * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2683 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
2684 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2685 * @param __PLLM__ This parameter can be one of the following values:
2686 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2687 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2688 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2689 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2690 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2691 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2692 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2693 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2694 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2695 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2696 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2697 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2698 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2699 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2700 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2701 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2702 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2703 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2704 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2705 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2706 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2707 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2708 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2709 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2710 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2711 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2712 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2713 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2714 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2715 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2716 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2717 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2718 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2719 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2720 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2721 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2722 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2723 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2724 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2725 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2726 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2727 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2728 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2729 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2730 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2731 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2732 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2733 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2734 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2735 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2736 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2737 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2738 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2739 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2740 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2741 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2742 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2743 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2744 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2745 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2746 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2747 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2748 * @param __PLLI2SN__ Between 50/192(*) and 432
2749 *
2750 * (*) value not defined in all devices.
2751 * @param __PLLI2SR__ This parameter can be one of the following values:
2752 * @arg @ref LL_RCC_PLLI2SR_DIV_2
2753 * @arg @ref LL_RCC_PLLI2SR_DIV_3
2754 * @arg @ref LL_RCC_PLLI2SR_DIV_4
2755 * @arg @ref LL_RCC_PLLI2SR_DIV_5
2756 * @arg @ref LL_RCC_PLLI2SR_DIV_6
2757 * @arg @ref LL_RCC_PLLI2SR_DIV_7
2758 * @retval PLLI2S clock frequency (in Hz)
2759 */
2760 #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2761 ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
2762
2763 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
2764 /**
2765 * @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain
2766 * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2767 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());
2768 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2769 * @param __PLLM__ This parameter can be one of the following values:
2770 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2771 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2772 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2773 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2774 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2775 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2776 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2777 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2778 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2779 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2780 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2781 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2782 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2783 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2784 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2785 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2786 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2787 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2788 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2789 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2790 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2791 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2792 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2793 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2794 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2795 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2796 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2797 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2798 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2799 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2800 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2801 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2802 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2803 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2804 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2805 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2806 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2807 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2808 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2809 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2810 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2811 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2812 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2813 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2814 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2815 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2816 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2817 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2818 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2819 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2820 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2821 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2822 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2823 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2824 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2825 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2826 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2827 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2828 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2829 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2830 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2831 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2832 * @param __PLLI2SN__ Between 50 and 432
2833 * @param __PLLI2SQ__ This parameter can be one of the following values:
2834 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
2835 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
2836 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
2837 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
2838 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
2839 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
2840 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
2841 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
2842 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
2843 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
2844 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
2845 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
2846 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
2847 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
2848 * @retval PLLI2S clock frequency (in Hz)
2849 */
2850 #define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2851 ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))
2852
2853 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
2854 #endif /* RCC_PLLI2S_SUPPORT */
2855
2856 /**
2857 * @brief Helper macro to calculate the HCLK frequency
2858 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
2859 * @param __AHBPRESCALER__ This parameter can be one of the following values:
2860 * @arg @ref LL_RCC_SYSCLK_DIV_1
2861 * @arg @ref LL_RCC_SYSCLK_DIV_2
2862 * @arg @ref LL_RCC_SYSCLK_DIV_4
2863 * @arg @ref LL_RCC_SYSCLK_DIV_8
2864 * @arg @ref LL_RCC_SYSCLK_DIV_16
2865 * @arg @ref LL_RCC_SYSCLK_DIV_64
2866 * @arg @ref LL_RCC_SYSCLK_DIV_128
2867 * @arg @ref LL_RCC_SYSCLK_DIV_256
2868 * @arg @ref LL_RCC_SYSCLK_DIV_512
2869 * @retval HCLK clock frequency (in Hz)
2870 */
2871 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
2872
2873 /**
2874 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
2875 * @param __HCLKFREQ__ HCLK frequency
2876 * @param __APB1PRESCALER__ This parameter can be one of the following values:
2877 * @arg @ref LL_RCC_APB1_DIV_1
2878 * @arg @ref LL_RCC_APB1_DIV_2
2879 * @arg @ref LL_RCC_APB1_DIV_4
2880 * @arg @ref LL_RCC_APB1_DIV_8
2881 * @arg @ref LL_RCC_APB1_DIV_16
2882 * @retval PCLK1 clock frequency (in Hz)
2883 */
2884 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
2885
2886 /**
2887 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
2888 * @param __HCLKFREQ__ HCLK frequency
2889 * @param __APB2PRESCALER__ This parameter can be one of the following values:
2890 * @arg @ref LL_RCC_APB2_DIV_1
2891 * @arg @ref LL_RCC_APB2_DIV_2
2892 * @arg @ref LL_RCC_APB2_DIV_4
2893 * @arg @ref LL_RCC_APB2_DIV_8
2894 * @arg @ref LL_RCC_APB2_DIV_16
2895 * @retval PCLK2 clock frequency (in Hz)
2896 */
2897 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
2898
2899 /**
2900 * @}
2901 */
2902
2903 /**
2904 * @}
2905 */
2906
2907 /* Exported functions --------------------------------------------------------*/
2908 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
2909 * @{
2910 */
2911
2912 /** @defgroup RCC_LL_EF_HSE HSE
2913 * @{
2914 */
2915
2916 /**
2917 * @brief Enable the Clock Security System.
2918 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
2919 * @retval None
2920 */
LL_RCC_HSE_EnableCSS(void)2921 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
2922 {
2923 SET_BIT(RCC->CR, RCC_CR_CSSON);
2924 }
2925
2926 /**
2927 * @brief Enable HSE external oscillator (HSE Bypass)
2928 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
2929 * @retval None
2930 */
LL_RCC_HSE_EnableBypass(void)2931 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
2932 {
2933 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
2934 }
2935
2936 /**
2937 * @brief Disable HSE external oscillator (HSE Bypass)
2938 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
2939 * @retval None
2940 */
LL_RCC_HSE_DisableBypass(void)2941 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
2942 {
2943 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
2944 }
2945
2946 /**
2947 * @brief Enable HSE crystal oscillator (HSE ON)
2948 * @rmtoll CR HSEON LL_RCC_HSE_Enable
2949 * @retval None
2950 */
LL_RCC_HSE_Enable(void)2951 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
2952 {
2953 SET_BIT(RCC->CR, RCC_CR_HSEON);
2954 }
2955
2956 /**
2957 * @brief Disable HSE crystal oscillator (HSE ON)
2958 * @rmtoll CR HSEON LL_RCC_HSE_Disable
2959 * @retval None
2960 */
LL_RCC_HSE_Disable(void)2961 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
2962 {
2963 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
2964 }
2965
2966 /**
2967 * @brief Check if HSE oscillator Ready
2968 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
2969 * @retval State of bit (1 or 0).
2970 */
LL_RCC_HSE_IsReady(void)2971 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
2972 {
2973 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
2974 }
2975
2976 /**
2977 * @}
2978 */
2979
2980 /** @defgroup RCC_LL_EF_HSI HSI
2981 * @{
2982 */
2983
2984 /**
2985 * @brief Enable HSI oscillator
2986 * @rmtoll CR HSION LL_RCC_HSI_Enable
2987 * @retval None
2988 */
LL_RCC_HSI_Enable(void)2989 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
2990 {
2991 SET_BIT(RCC->CR, RCC_CR_HSION);
2992 }
2993
2994 /**
2995 * @brief Disable HSI oscillator
2996 * @rmtoll CR HSION LL_RCC_HSI_Disable
2997 * @retval None
2998 */
LL_RCC_HSI_Disable(void)2999 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
3000 {
3001 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
3002 }
3003
3004 /**
3005 * @brief Check if HSI clock is ready
3006 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
3007 * @retval State of bit (1 or 0).
3008 */
LL_RCC_HSI_IsReady(void)3009 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
3010 {
3011 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
3012 }
3013
3014 /**
3015 * @brief Get HSI Calibration value
3016 * @note When HSITRIM is written, HSICAL is updated with the sum of
3017 * HSITRIM and the factory trim value
3018 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
3019 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
3020 */
LL_RCC_HSI_GetCalibration(void)3021 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
3022 {
3023 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
3024 }
3025
3026 /**
3027 * @brief Set HSI Calibration trimming
3028 * @note user-programmable trimming value that is added to the HSICAL
3029 * @note Default value is 16, which, when added to the HSICAL value,
3030 * should trim the HSI to 16 MHz +/- 1 %
3031 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
3032 * @param Value Between Min_Data = 0 and Max_Data = 31
3033 * @retval None
3034 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)3035 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
3036 {
3037 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
3038 }
3039
3040 /**
3041 * @brief Get HSI Calibration trimming
3042 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
3043 * @retval Between Min_Data = 0 and Max_Data = 31
3044 */
LL_RCC_HSI_GetCalibTrimming(void)3045 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
3046 {
3047 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
3048 }
3049
3050 /**
3051 * @}
3052 */
3053
3054 /** @defgroup RCC_LL_EF_LSE LSE
3055 * @{
3056 */
3057
3058 /**
3059 * @brief Enable Low Speed External (LSE) crystal.
3060 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
3061 * @retval None
3062 */
LL_RCC_LSE_Enable(void)3063 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
3064 {
3065 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
3066 }
3067
3068 /**
3069 * @brief Disable Low Speed External (LSE) crystal.
3070 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
3071 * @retval None
3072 */
LL_RCC_LSE_Disable(void)3073 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
3074 {
3075 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
3076 }
3077
3078 /**
3079 * @brief Enable external clock source (LSE bypass).
3080 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
3081 * @retval None
3082 */
LL_RCC_LSE_EnableBypass(void)3083 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
3084 {
3085 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
3086 }
3087
3088 /**
3089 * @brief Disable external clock source (LSE bypass).
3090 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
3091 * @retval None
3092 */
LL_RCC_LSE_DisableBypass(void)3093 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
3094 {
3095 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
3096 }
3097
3098 /**
3099 * @brief Check if LSE oscillator Ready
3100 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
3101 * @retval State of bit (1 or 0).
3102 */
LL_RCC_LSE_IsReady(void)3103 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
3104 {
3105 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
3106 }
3107
3108 #if defined(RCC_BDCR_LSEMOD)
3109 /**
3110 * @brief Enable LSE high drive mode.
3111 * @note LSE high drive mode can be enabled only when the LSE clock is disabled
3112 * @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode
3113 * @retval None
3114 */
LL_RCC_LSE_EnableHighDriveMode(void)3115 __STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)
3116 {
3117 SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
3118 }
3119
3120 /**
3121 * @brief Disable LSE high drive mode.
3122 * @note LSE high drive mode can be disabled only when the LSE clock is disabled
3123 * @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode
3124 * @retval None
3125 */
LL_RCC_LSE_DisableHighDriveMode(void)3126 __STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)
3127 {
3128 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
3129 }
3130 #endif /* RCC_BDCR_LSEMOD */
3131
3132 /**
3133 * @}
3134 */
3135
3136 /** @defgroup RCC_LL_EF_LSI LSI
3137 * @{
3138 */
3139
3140 /**
3141 * @brief Enable LSI Oscillator
3142 * @rmtoll CSR LSION LL_RCC_LSI_Enable
3143 * @retval None
3144 */
LL_RCC_LSI_Enable(void)3145 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
3146 {
3147 SET_BIT(RCC->CSR, RCC_CSR_LSION);
3148 }
3149
3150 /**
3151 * @brief Disable LSI Oscillator
3152 * @rmtoll CSR LSION LL_RCC_LSI_Disable
3153 * @retval None
3154 */
LL_RCC_LSI_Disable(void)3155 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
3156 {
3157 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
3158 }
3159
3160 /**
3161 * @brief Check if LSI is Ready
3162 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
3163 * @retval State of bit (1 or 0).
3164 */
LL_RCC_LSI_IsReady(void)3165 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
3166 {
3167 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
3168 }
3169
3170 /**
3171 * @}
3172 */
3173
3174 /** @defgroup RCC_LL_EF_System System
3175 * @{
3176 */
3177
3178 /**
3179 * @brief Configure the system clock source
3180 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
3181 * @param Source This parameter can be one of the following values:
3182 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
3183 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
3184 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
3185 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)
3186 *
3187 * (*) value not defined in all devices.
3188 * @retval None
3189 */
LL_RCC_SetSysClkSource(uint32_t Source)3190 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
3191 {
3192 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
3193 }
3194
3195 /**
3196 * @brief Get the system clock source
3197 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
3198 * @retval Returned value can be one of the following values:
3199 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
3200 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
3201 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
3202 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)
3203 *
3204 * (*) value not defined in all devices.
3205 */
LL_RCC_GetSysClkSource(void)3206 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
3207 {
3208 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
3209 }
3210
3211 /**
3212 * @brief Set AHB prescaler
3213 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
3214 * @param Prescaler This parameter can be one of the following values:
3215 * @arg @ref LL_RCC_SYSCLK_DIV_1
3216 * @arg @ref LL_RCC_SYSCLK_DIV_2
3217 * @arg @ref LL_RCC_SYSCLK_DIV_4
3218 * @arg @ref LL_RCC_SYSCLK_DIV_8
3219 * @arg @ref LL_RCC_SYSCLK_DIV_16
3220 * @arg @ref LL_RCC_SYSCLK_DIV_64
3221 * @arg @ref LL_RCC_SYSCLK_DIV_128
3222 * @arg @ref LL_RCC_SYSCLK_DIV_256
3223 * @arg @ref LL_RCC_SYSCLK_DIV_512
3224 * @retval None
3225 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)3226 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
3227 {
3228 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
3229 }
3230
3231 /**
3232 * @brief Set APB1 prescaler
3233 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
3234 * @param Prescaler This parameter can be one of the following values:
3235 * @arg @ref LL_RCC_APB1_DIV_1
3236 * @arg @ref LL_RCC_APB1_DIV_2
3237 * @arg @ref LL_RCC_APB1_DIV_4
3238 * @arg @ref LL_RCC_APB1_DIV_8
3239 * @arg @ref LL_RCC_APB1_DIV_16
3240 * @retval None
3241 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)3242 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
3243 {
3244 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
3245 }
3246
3247 /**
3248 * @brief Set APB2 prescaler
3249 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
3250 * @param Prescaler This parameter can be one of the following values:
3251 * @arg @ref LL_RCC_APB2_DIV_1
3252 * @arg @ref LL_RCC_APB2_DIV_2
3253 * @arg @ref LL_RCC_APB2_DIV_4
3254 * @arg @ref LL_RCC_APB2_DIV_8
3255 * @arg @ref LL_RCC_APB2_DIV_16
3256 * @retval None
3257 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)3258 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
3259 {
3260 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
3261 }
3262
3263 /**
3264 * @brief Get AHB prescaler
3265 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
3266 * @retval Returned value can be one of the following values:
3267 * @arg @ref LL_RCC_SYSCLK_DIV_1
3268 * @arg @ref LL_RCC_SYSCLK_DIV_2
3269 * @arg @ref LL_RCC_SYSCLK_DIV_4
3270 * @arg @ref LL_RCC_SYSCLK_DIV_8
3271 * @arg @ref LL_RCC_SYSCLK_DIV_16
3272 * @arg @ref LL_RCC_SYSCLK_DIV_64
3273 * @arg @ref LL_RCC_SYSCLK_DIV_128
3274 * @arg @ref LL_RCC_SYSCLK_DIV_256
3275 * @arg @ref LL_RCC_SYSCLK_DIV_512
3276 */
LL_RCC_GetAHBPrescaler(void)3277 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
3278 {
3279 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
3280 }
3281
3282 /**
3283 * @brief Get APB1 prescaler
3284 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
3285 * @retval Returned value can be one of the following values:
3286 * @arg @ref LL_RCC_APB1_DIV_1
3287 * @arg @ref LL_RCC_APB1_DIV_2
3288 * @arg @ref LL_RCC_APB1_DIV_4
3289 * @arg @ref LL_RCC_APB1_DIV_8
3290 * @arg @ref LL_RCC_APB1_DIV_16
3291 */
LL_RCC_GetAPB1Prescaler(void)3292 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
3293 {
3294 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
3295 }
3296
3297 /**
3298 * @brief Get APB2 prescaler
3299 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
3300 * @retval Returned value can be one of the following values:
3301 * @arg @ref LL_RCC_APB2_DIV_1
3302 * @arg @ref LL_RCC_APB2_DIV_2
3303 * @arg @ref LL_RCC_APB2_DIV_4
3304 * @arg @ref LL_RCC_APB2_DIV_8
3305 * @arg @ref LL_RCC_APB2_DIV_16
3306 */
LL_RCC_GetAPB2Prescaler(void)3307 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
3308 {
3309 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
3310 }
3311
3312 /**
3313 * @}
3314 */
3315
3316 /** @defgroup RCC_LL_EF_MCO MCO
3317 * @{
3318 */
3319
3320 #if defined(RCC_CFGR_MCO1EN)
3321 /**
3322 * @brief Enable MCO1 output
3323 * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable
3324 * @retval None
3325 */
LL_RCC_MCO1_Enable(void)3326 __STATIC_INLINE void LL_RCC_MCO1_Enable(void)
3327 {
3328 SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
3329 }
3330
3331 /**
3332 * @brief Disable MCO1 output
3333 * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable
3334 * @retval None
3335 */
LL_RCC_MCO1_Disable(void)3336 __STATIC_INLINE void LL_RCC_MCO1_Disable(void)
3337 {
3338 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
3339 }
3340 #endif /* RCC_CFGR_MCO1EN */
3341
3342 #if defined(RCC_CFGR_MCO2EN)
3343 /**
3344 * @brief Enable MCO2 output
3345 * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable
3346 * @retval None
3347 */
LL_RCC_MCO2_Enable(void)3348 __STATIC_INLINE void LL_RCC_MCO2_Enable(void)
3349 {
3350 SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
3351 }
3352
3353 /**
3354 * @brief Disable MCO2 output
3355 * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable
3356 * @retval None
3357 */
LL_RCC_MCO2_Disable(void)3358 __STATIC_INLINE void LL_RCC_MCO2_Disable(void)
3359 {
3360 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
3361 }
3362 #endif /* RCC_CFGR_MCO2EN */
3363
3364 /**
3365 * @brief Configure MCOx
3366 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
3367 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
3368 * CFGR MCO2 LL_RCC_ConfigMCO\n
3369 * CFGR MCO2PRE LL_RCC_ConfigMCO
3370 * @param MCOxSource This parameter can be one of the following values:
3371 * @arg @ref LL_RCC_MCO1SOURCE_HSI
3372 * @arg @ref LL_RCC_MCO1SOURCE_LSE
3373 * @arg @ref LL_RCC_MCO1SOURCE_HSE
3374 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
3375 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
3376 * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
3377 * @arg @ref LL_RCC_MCO2SOURCE_HSE
3378 * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
3379 * @param MCOxPrescaler This parameter can be one of the following values:
3380 * @arg @ref LL_RCC_MCO1_DIV_1
3381 * @arg @ref LL_RCC_MCO1_DIV_2
3382 * @arg @ref LL_RCC_MCO1_DIV_3
3383 * @arg @ref LL_RCC_MCO1_DIV_4
3384 * @arg @ref LL_RCC_MCO1_DIV_5
3385 * @arg @ref LL_RCC_MCO2_DIV_1
3386 * @arg @ref LL_RCC_MCO2_DIV_2
3387 * @arg @ref LL_RCC_MCO2_DIV_3
3388 * @arg @ref LL_RCC_MCO2_DIV_4
3389 * @arg @ref LL_RCC_MCO2_DIV_5
3390 * @retval None
3391 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)3392 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
3393 {
3394 MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U));
3395 }
3396
3397 /**
3398 * @}
3399 */
3400
3401 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
3402 * @{
3403 */
3404 #if defined(FMPI2C1)
3405 /**
3406 * @brief Configure FMPI2C clock source
3407 * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource
3408 * @param FMPI2CxSource This parameter can be one of the following values:
3409 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
3410 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
3411 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
3412 * @retval None
3413 */
LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)3414 __STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)
3415 {
3416 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);
3417 }
3418 #endif /* FMPI2C1 */
3419
3420 #if defined(LPTIM1)
3421 /**
3422 * @brief Configure LPTIMx clock source
3423 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
3424 * @param LPTIMxSource This parameter can be one of the following values:
3425 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3426 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
3427 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3428 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3429 * @retval None
3430 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)3431 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
3432 {
3433 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
3434 }
3435 #endif /* LPTIM1 */
3436
3437 #if defined(SAI1)
3438 /**
3439 * @brief Configure SAIx clock source
3440 * @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n
3441 * DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n
3442 * DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n
3443 * DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource
3444 * @param SAIxSource This parameter can be one of the following values:
3445 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
3446 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
3447 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
3448 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
3449 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
3450 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
3451 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
3452 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
3453 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
3454 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
3455 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
3456 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
3457 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
3458 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
3459 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
3460 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
3461 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
3462 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
3463 *
3464 * (*) value not defined in all devices.
3465 * @retval None
3466 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)3467 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
3468 {
3469 MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
3470 }
3471 #endif /* SAI1 */
3472
3473 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
3474 /**
3475 * @brief Configure SDIO clock source
3476 * @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n
3477 * DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource
3478 * @param SDIOxSource This parameter can be one of the following values:
3479 * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
3480 * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
3481 * @retval None
3482 */
LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)3483 __STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)
3484 {
3485 #if defined(RCC_DCKCFGR_SDIOSEL)
3486 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);
3487 #else
3488 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);
3489 #endif /* RCC_DCKCFGR_SDIOSEL */
3490 }
3491 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
3492
3493 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
3494 /**
3495 * @brief Configure 48Mhz domain clock source
3496 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n
3497 * DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
3498 * @param CK48MxSource This parameter can be one of the following values:
3499 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
3500 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
3501 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
3502 *
3503 * (*) value not defined in all devices.
3504 * @retval None
3505 */
LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)3506 __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
3507 {
3508 #if defined(RCC_DCKCFGR_CK48MSEL)
3509 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);
3510 #else
3511 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
3512 #endif /* RCC_DCKCFGR_CK48MSEL */
3513 }
3514
3515 #if defined(RNG)
3516 /**
3517 * @brief Configure RNG clock source
3518 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n
3519 * DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
3520 * @param RNGxSource This parameter can be one of the following values:
3521 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
3522 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
3523 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
3524 *
3525 * (*) value not defined in all devices.
3526 * @retval None
3527 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)3528 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
3529 {
3530 #if defined(RCC_DCKCFGR_CK48MSEL)
3531 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);
3532 #else
3533 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
3534 #endif /* RCC_DCKCFGR_CK48MSEL */
3535 }
3536 #endif /* RNG */
3537
3538 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
3539 /**
3540 * @brief Configure USB clock source
3541 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n
3542 * DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
3543 * @param USBxSource This parameter can be one of the following values:
3544 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
3545 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
3546 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
3547 *
3548 * (*) value not defined in all devices.
3549 * @retval None
3550 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)3551 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
3552 {
3553 #if defined(RCC_DCKCFGR_CK48MSEL)
3554 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);
3555 #else
3556 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
3557 #endif /* RCC_DCKCFGR_CK48MSEL */
3558 }
3559 #endif /* USB_OTG_FS || USB_OTG_HS */
3560 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
3561
3562 #if defined(CEC)
3563 /**
3564 * @brief Configure CEC clock source
3565 * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
3566 * @param Source This parameter can be one of the following values:
3567 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
3568 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3569 * @retval None
3570 */
LL_RCC_SetCECClockSource(uint32_t Source)3571 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
3572 {
3573 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
3574 }
3575 #endif /* CEC */
3576
3577 /**
3578 * @brief Configure I2S clock source
3579 * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n
3580 * DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n
3581 * DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n
3582 * DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource
3583 * @param Source This parameter can be one of the following values:
3584 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
3585 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
3586 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
3587 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
3588 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
3589 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
3590 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
3591 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
3592 *
3593 * (*) value not defined in all devices.
3594 * @retval None
3595 */
LL_RCC_SetI2SClockSource(uint32_t Source)3596 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
3597 {
3598 #if defined(RCC_CFGR_I2SSRC)
3599 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
3600 #else
3601 MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));
3602 #endif /* RCC_CFGR_I2SSRC */
3603 }
3604
3605 #if defined(DSI)
3606 /**
3607 * @brief Configure DSI clock source
3608 * @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource
3609 * @param Source This parameter can be one of the following values:
3610 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3611 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
3612 * @retval None
3613 */
LL_RCC_SetDSIClockSource(uint32_t Source)3614 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
3615 {
3616 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);
3617 }
3618 #endif /* DSI */
3619
3620 #if defined(DFSDM1_Channel0)
3621 /**
3622 * @brief Configure DFSDM Audio clock source
3623 * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n
3624 * DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource
3625 * @param Source This parameter can be one of the following values:
3626 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
3627 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
3628 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
3629 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
3630 *
3631 * (*) value not defined in all devices.
3632 * @retval None
3633 */
LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)3634 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
3635 {
3636 MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));
3637 }
3638
3639 /**
3640 * @brief Configure DFSDM Kernel clock source
3641 * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource
3642 * @param Source This parameter can be one of the following values:
3643 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3644 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3645 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
3646 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
3647 *
3648 * (*) value not defined in all devices.
3649 * @retval None
3650 */
LL_RCC_SetDFSDMClockSource(uint32_t Source)3651 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
3652 {
3653 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);
3654 }
3655 #endif /* DFSDM1_Channel0 */
3656
3657 #if defined(SPDIFRX)
3658 /**
3659 * @brief Configure SPDIFRX clock source
3660 * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource
3661 * @param SPDIFRXxSource This parameter can be one of the following values:
3662 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
3663 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
3664 *
3665 * (*) value not defined in all devices.
3666 * @retval None
3667 */
LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)3668 __STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)
3669 {
3670 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);
3671 }
3672 #endif /* SPDIFRX */
3673
3674 #if defined(FMPI2C1)
3675 /**
3676 * @brief Get FMPI2C clock source
3677 * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource
3678 * @param FMPI2Cx This parameter can be one of the following values:
3679 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
3680 * @retval Returned value can be one of the following values:
3681 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
3682 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
3683 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
3684 */
LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)3685 __STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)
3686 {
3687 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));
3688 }
3689 #endif /* FMPI2C1 */
3690
3691 #if defined(LPTIM1)
3692 /**
3693 * @brief Get LPTIMx clock source
3694 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
3695 * @param LPTIMx This parameter can be one of the following values:
3696 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3697 * @retval Returned value can be one of the following values:
3698 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3699 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
3700 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3701 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3702 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)3703 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
3704 {
3705 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
3706 }
3707 #endif /* LPTIM1 */
3708
3709 #if defined(SAI1)
3710 /**
3711 * @brief Get SAIx clock source
3712 * @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n
3713 * DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n
3714 * DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n
3715 * DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource
3716 * @param SAIx This parameter can be one of the following values:
3717 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
3718 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
3719 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
3720 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
3721 *
3722 * (*) value not defined in all devices.
3723 * @retval Returned value can be one of the following values:
3724 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
3725 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
3726 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
3727 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
3728 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
3729 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
3730 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
3731 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
3732 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
3733 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
3734 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
3735 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
3736 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
3737 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
3738 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
3739 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
3740 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
3741 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
3742 *
3743 * (*) value not defined in all devices.
3744 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)3745 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
3746 {
3747 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx);
3748 }
3749 #endif /* SAI1 */
3750
3751 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
3752 /**
3753 * @brief Get SDIOx clock source
3754 * @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n
3755 * DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource
3756 * @param SDIOx This parameter can be one of the following values:
3757 * @arg @ref LL_RCC_SDIO_CLKSOURCE
3758 * @retval Returned value can be one of the following values:
3759 * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
3760 * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
3761 */
LL_RCC_GetSDIOClockSource(uint32_t SDIOx)3762 __STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)
3763 {
3764 #if defined(RCC_DCKCFGR_SDIOSEL)
3765 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));
3766 #else
3767 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));
3768 #endif /* RCC_DCKCFGR_SDIOSEL */
3769 }
3770 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
3771
3772 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
3773 /**
3774 * @brief Get 48Mhz domain clock source
3775 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n
3776 * DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
3777 * @param CK48Mx This parameter can be one of the following values:
3778 * @arg @ref LL_RCC_CK48M_CLKSOURCE
3779 * @retval Returned value can be one of the following values:
3780 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
3781 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
3782 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
3783 *
3784 * (*) value not defined in all devices.
3785 */
LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)3786 __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
3787 {
3788 #if defined(RCC_DCKCFGR_CK48MSEL)
3789 return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));
3790 #else
3791 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
3792 #endif /* RCC_DCKCFGR_CK48MSEL */
3793 }
3794
3795 #if defined(RNG)
3796 /**
3797 * @brief Get RNGx clock source
3798 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n
3799 * DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
3800 * @param RNGx This parameter can be one of the following values:
3801 * @arg @ref LL_RCC_RNG_CLKSOURCE
3802 * @retval Returned value can be one of the following values:
3803 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
3804 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
3805 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
3806 *
3807 * (*) value not defined in all devices.
3808 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)3809 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
3810 {
3811 #if defined(RCC_DCKCFGR_CK48MSEL)
3812 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));
3813 #else
3814 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
3815 #endif /* RCC_DCKCFGR_CK48MSEL */
3816 }
3817 #endif /* RNG */
3818
3819 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
3820 /**
3821 * @brief Get USBx clock source
3822 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n
3823 * DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
3824 * @param USBx This parameter can be one of the following values:
3825 * @arg @ref LL_RCC_USB_CLKSOURCE
3826 * @retval Returned value can be one of the following values:
3827 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
3828 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
3829 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
3830 *
3831 * (*) value not defined in all devices.
3832 */
LL_RCC_GetUSBClockSource(uint32_t USBx)3833 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
3834 {
3835 #if defined(RCC_DCKCFGR_CK48MSEL)
3836 return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));
3837 #else
3838 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
3839 #endif /* RCC_DCKCFGR_CK48MSEL */
3840 }
3841 #endif /* USB_OTG_FS || USB_OTG_HS */
3842 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
3843
3844 #if defined(CEC)
3845 /**
3846 * @brief Get CEC Clock Source
3847 * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
3848 * @param CECx This parameter can be one of the following values:
3849 * @arg @ref LL_RCC_CEC_CLKSOURCE
3850 * @retval Returned value can be one of the following values:
3851 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
3852 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3853 */
LL_RCC_GetCECClockSource(uint32_t CECx)3854 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
3855 {
3856 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
3857 }
3858 #endif /* CEC */
3859
3860 /**
3861 * @brief Get I2S Clock Source
3862 * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n
3863 * DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n
3864 * DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n
3865 * DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource
3866 * @param I2Sx This parameter can be one of the following values:
3867 * @arg @ref LL_RCC_I2S1_CLKSOURCE
3868 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
3869 * @retval Returned value can be one of the following values:
3870 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
3871 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
3872 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
3873 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
3874 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
3875 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
3876 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
3877 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
3878 *
3879 * (*) value not defined in all devices.
3880 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)3881 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
3882 {
3883 #if defined(RCC_CFGR_I2SSRC)
3884 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
3885 #else
3886 return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx);
3887 #endif /* RCC_CFGR_I2SSRC */
3888 }
3889
3890 #if defined(DFSDM1_Channel0)
3891 /**
3892 * @brief Get DFSDM Audio Clock Source
3893 * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n
3894 * DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource
3895 * @param DFSDMx This parameter can be one of the following values:
3896 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
3897 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
3898 * @retval Returned value can be one of the following values:
3899 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
3900 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
3901 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
3902 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
3903 *
3904 * (*) value not defined in all devices.
3905 */
LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)3906 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
3907 {
3908 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx);
3909 }
3910
3911 /**
3912 * @brief Get DFSDM Audio Clock Source
3913 * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource
3914 * @param DFSDMx This parameter can be one of the following values:
3915 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
3916 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
3917 * @retval Returned value can be one of the following values:
3918 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3919 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3920 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
3921 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
3922 *
3923 * (*) value not defined in all devices.
3924 */
LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)3925 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
3926 {
3927 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));
3928 }
3929 #endif /* DFSDM1_Channel0 */
3930
3931 #if defined(SPDIFRX)
3932 /**
3933 * @brief Get SPDIFRX clock source
3934 * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource
3935 * @param SPDIFRXx This parameter can be one of the following values:
3936 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
3937 * @retval Returned value can be one of the following values:
3938 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
3939 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
3940 *
3941 * (*) value not defined in all devices.
3942 */
LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)3943 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)
3944 {
3945 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));
3946 }
3947 #endif /* SPDIFRX */
3948
3949 #if defined(DSI)
3950 /**
3951 * @brief Get DSI Clock Source
3952 * @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource
3953 * @param DSIx This parameter can be one of the following values:
3954 * @arg @ref LL_RCC_DSI_CLKSOURCE
3955 * @retval Returned value can be one of the following values:
3956 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3957 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
3958 */
LL_RCC_GetDSIClockSource(uint32_t DSIx)3959 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
3960 {
3961 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));
3962 }
3963 #endif /* DSI */
3964
3965 /**
3966 * @}
3967 */
3968
3969 /** @defgroup RCC_LL_EF_RTC RTC
3970 * @{
3971 */
3972
3973 /**
3974 * @brief Set RTC Clock Source
3975 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
3976 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
3977 * set). The BDRST bit can be used to reset them.
3978 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
3979 * @param Source This parameter can be one of the following values:
3980 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3981 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3982 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3983 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
3984 * @retval None
3985 */
LL_RCC_SetRTCClockSource(uint32_t Source)3986 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
3987 {
3988 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
3989 }
3990
3991 /**
3992 * @brief Get RTC Clock Source
3993 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
3994 * @retval Returned value can be one of the following values:
3995 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3996 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3997 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3998 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
3999 */
LL_RCC_GetRTCClockSource(void)4000 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
4001 {
4002 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
4003 }
4004
4005 /**
4006 * @brief Enable RTC
4007 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
4008 * @retval None
4009 */
LL_RCC_EnableRTC(void)4010 __STATIC_INLINE void LL_RCC_EnableRTC(void)
4011 {
4012 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4013 }
4014
4015 /**
4016 * @brief Disable RTC
4017 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
4018 * @retval None
4019 */
LL_RCC_DisableRTC(void)4020 __STATIC_INLINE void LL_RCC_DisableRTC(void)
4021 {
4022 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4023 }
4024
4025 /**
4026 * @brief Check if RTC has been enabled or not
4027 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
4028 * @retval State of bit (1 or 0).
4029 */
LL_RCC_IsEnabledRTC(void)4030 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
4031 {
4032 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
4033 }
4034
4035 /**
4036 * @brief Force the Backup domain reset
4037 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
4038 * @retval None
4039 */
LL_RCC_ForceBackupDomainReset(void)4040 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
4041 {
4042 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4043 }
4044
4045 /**
4046 * @brief Release the Backup domain reset
4047 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
4048 * @retval None
4049 */
LL_RCC_ReleaseBackupDomainReset(void)4050 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
4051 {
4052 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4053 }
4054
4055 /**
4056 * @brief Set HSE Prescalers for RTC Clock
4057 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
4058 * @param Prescaler This parameter can be one of the following values:
4059 * @arg @ref LL_RCC_RTC_NOCLOCK
4060 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4061 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4062 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4063 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4064 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4065 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4066 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4067 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4068 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4069 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4070 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4071 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4072 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4073 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4074 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4075 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4076 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4077 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4078 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4079 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4080 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4081 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4082 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4083 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4084 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4085 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4086 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4087 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4088 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4089 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4090 * @retval None
4091 */
LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)4092 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
4093 {
4094 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
4095 }
4096
4097 /**
4098 * @brief Get HSE Prescalers for RTC Clock
4099 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
4100 * @retval Returned value can be one of the following values:
4101 * @arg @ref LL_RCC_RTC_NOCLOCK
4102 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4103 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4104 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4105 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4106 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4107 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4108 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4109 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4110 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4111 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4112 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4113 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4114 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4115 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4116 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4117 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4118 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4119 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4120 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4121 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4122 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4123 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4124 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4125 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4126 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4127 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4128 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4129 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4130 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4131 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4132 */
LL_RCC_GetRTC_HSEPrescaler(void)4133 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
4134 {
4135 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
4136 }
4137
4138 /**
4139 * @}
4140 */
4141
4142 #if defined(RCC_DCKCFGR_TIMPRE)
4143 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
4144 * @{
4145 */
4146
4147 /**
4148 * @brief Set Timers Clock Prescalers
4149 * @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler
4150 * @param Prescaler This parameter can be one of the following values:
4151 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4152 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4153 * @retval None
4154 */
LL_RCC_SetTIMPrescaler(uint32_t Prescaler)4155 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
4156 {
4157 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);
4158 }
4159
4160 /**
4161 * @brief Get Timers Clock Prescalers
4162 * @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler
4163 * @retval Returned value can be one of the following values:
4164 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4165 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4166 */
LL_RCC_GetTIMPrescaler(void)4167 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
4168 {
4169 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));
4170 }
4171
4172 /**
4173 * @}
4174 */
4175 #endif /* RCC_DCKCFGR_TIMPRE */
4176
4177 /** @defgroup RCC_LL_EF_PLL PLL
4178 * @{
4179 */
4180
4181 /**
4182 * @brief Enable PLL
4183 * @rmtoll CR PLLON LL_RCC_PLL_Enable
4184 * @retval None
4185 */
LL_RCC_PLL_Enable(void)4186 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
4187 {
4188 SET_BIT(RCC->CR, RCC_CR_PLLON);
4189 }
4190
4191 /**
4192 * @brief Disable PLL
4193 * @note Cannot be disabled if the PLL clock is used as the system clock
4194 * @rmtoll CR PLLON LL_RCC_PLL_Disable
4195 * @retval None
4196 */
LL_RCC_PLL_Disable(void)4197 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
4198 {
4199 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
4200 }
4201
4202 /**
4203 * @brief Check if PLL Ready
4204 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
4205 * @retval State of bit (1 or 0).
4206 */
LL_RCC_PLL_IsReady(void)4207 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
4208 {
4209 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
4210 }
4211
4212 /**
4213 * @brief Configure PLL used for SYSCLK Domain
4214 * @note PLL Source and PLLM Divider can be written only when PLL,
4215 * PLLI2S and PLLSAI(*) are disabled
4216 * @note PLLN/PLLP can be written only when PLL is disabled
4217 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
4218 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
4219 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
4220 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n
4221 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
4222 * @param Source This parameter can be one of the following values:
4223 * @arg @ref LL_RCC_PLLSOURCE_HSI
4224 * @arg @ref LL_RCC_PLLSOURCE_HSE
4225 * @param PLLM This parameter can be one of the following values:
4226 * @arg @ref LL_RCC_PLLM_DIV_2
4227 * @arg @ref LL_RCC_PLLM_DIV_3
4228 * @arg @ref LL_RCC_PLLM_DIV_4
4229 * @arg @ref LL_RCC_PLLM_DIV_5
4230 * @arg @ref LL_RCC_PLLM_DIV_6
4231 * @arg @ref LL_RCC_PLLM_DIV_7
4232 * @arg @ref LL_RCC_PLLM_DIV_8
4233 * @arg @ref LL_RCC_PLLM_DIV_9
4234 * @arg @ref LL_RCC_PLLM_DIV_10
4235 * @arg @ref LL_RCC_PLLM_DIV_11
4236 * @arg @ref LL_RCC_PLLM_DIV_12
4237 * @arg @ref LL_RCC_PLLM_DIV_13
4238 * @arg @ref LL_RCC_PLLM_DIV_14
4239 * @arg @ref LL_RCC_PLLM_DIV_15
4240 * @arg @ref LL_RCC_PLLM_DIV_16
4241 * @arg @ref LL_RCC_PLLM_DIV_17
4242 * @arg @ref LL_RCC_PLLM_DIV_18
4243 * @arg @ref LL_RCC_PLLM_DIV_19
4244 * @arg @ref LL_RCC_PLLM_DIV_20
4245 * @arg @ref LL_RCC_PLLM_DIV_21
4246 * @arg @ref LL_RCC_PLLM_DIV_22
4247 * @arg @ref LL_RCC_PLLM_DIV_23
4248 * @arg @ref LL_RCC_PLLM_DIV_24
4249 * @arg @ref LL_RCC_PLLM_DIV_25
4250 * @arg @ref LL_RCC_PLLM_DIV_26
4251 * @arg @ref LL_RCC_PLLM_DIV_27
4252 * @arg @ref LL_RCC_PLLM_DIV_28
4253 * @arg @ref LL_RCC_PLLM_DIV_29
4254 * @arg @ref LL_RCC_PLLM_DIV_30
4255 * @arg @ref LL_RCC_PLLM_DIV_31
4256 * @arg @ref LL_RCC_PLLM_DIV_32
4257 * @arg @ref LL_RCC_PLLM_DIV_33
4258 * @arg @ref LL_RCC_PLLM_DIV_34
4259 * @arg @ref LL_RCC_PLLM_DIV_35
4260 * @arg @ref LL_RCC_PLLM_DIV_36
4261 * @arg @ref LL_RCC_PLLM_DIV_37
4262 * @arg @ref LL_RCC_PLLM_DIV_38
4263 * @arg @ref LL_RCC_PLLM_DIV_39
4264 * @arg @ref LL_RCC_PLLM_DIV_40
4265 * @arg @ref LL_RCC_PLLM_DIV_41
4266 * @arg @ref LL_RCC_PLLM_DIV_42
4267 * @arg @ref LL_RCC_PLLM_DIV_43
4268 * @arg @ref LL_RCC_PLLM_DIV_44
4269 * @arg @ref LL_RCC_PLLM_DIV_45
4270 * @arg @ref LL_RCC_PLLM_DIV_46
4271 * @arg @ref LL_RCC_PLLM_DIV_47
4272 * @arg @ref LL_RCC_PLLM_DIV_48
4273 * @arg @ref LL_RCC_PLLM_DIV_49
4274 * @arg @ref LL_RCC_PLLM_DIV_50
4275 * @arg @ref LL_RCC_PLLM_DIV_51
4276 * @arg @ref LL_RCC_PLLM_DIV_52
4277 * @arg @ref LL_RCC_PLLM_DIV_53
4278 * @arg @ref LL_RCC_PLLM_DIV_54
4279 * @arg @ref LL_RCC_PLLM_DIV_55
4280 * @arg @ref LL_RCC_PLLM_DIV_56
4281 * @arg @ref LL_RCC_PLLM_DIV_57
4282 * @arg @ref LL_RCC_PLLM_DIV_58
4283 * @arg @ref LL_RCC_PLLM_DIV_59
4284 * @arg @ref LL_RCC_PLLM_DIV_60
4285 * @arg @ref LL_RCC_PLLM_DIV_61
4286 * @arg @ref LL_RCC_PLLM_DIV_62
4287 * @arg @ref LL_RCC_PLLM_DIV_63
4288 * @param PLLN Between 50/192(*) and 432
4289 *
4290 * (*) value not defined in all devices.
4291 * @param PLLP_R This parameter can be one of the following values:
4292 * @arg @ref LL_RCC_PLLP_DIV_2
4293 * @arg @ref LL_RCC_PLLP_DIV_4
4294 * @arg @ref LL_RCC_PLLP_DIV_6
4295 * @arg @ref LL_RCC_PLLP_DIV_8
4296 * @arg @ref LL_RCC_PLLR_DIV_2 (*)
4297 * @arg @ref LL_RCC_PLLR_DIV_3 (*)
4298 * @arg @ref LL_RCC_PLLR_DIV_4 (*)
4299 * @arg @ref LL_RCC_PLLR_DIV_5 (*)
4300 * @arg @ref LL_RCC_PLLR_DIV_6 (*)
4301 * @arg @ref LL_RCC_PLLR_DIV_7 (*)
4302 *
4303 * (*) value not defined in all devices.
4304 * @retval None
4305 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP_R)4306 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
4307 {
4308 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN,
4309 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos);
4310 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);
4311 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
4312 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);
4313 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
4314 }
4315
4316 /**
4317 * @brief Configure PLL used for 48Mhz domain clock
4318 * @note PLL Source and PLLM Divider can be written only when PLL,
4319 * PLLI2S and PLLSAI(*) are disabled
4320 * @note PLLN/PLLQ can be written only when PLL is disabled
4321 * @note This can be selected for USB, RNG, SDIO
4322 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
4323 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
4324 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
4325 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
4326 * @param Source This parameter can be one of the following values:
4327 * @arg @ref LL_RCC_PLLSOURCE_HSI
4328 * @arg @ref LL_RCC_PLLSOURCE_HSE
4329 * @param PLLM This parameter can be one of the following values:
4330 * @arg @ref LL_RCC_PLLM_DIV_2
4331 * @arg @ref LL_RCC_PLLM_DIV_3
4332 * @arg @ref LL_RCC_PLLM_DIV_4
4333 * @arg @ref LL_RCC_PLLM_DIV_5
4334 * @arg @ref LL_RCC_PLLM_DIV_6
4335 * @arg @ref LL_RCC_PLLM_DIV_7
4336 * @arg @ref LL_RCC_PLLM_DIV_8
4337 * @arg @ref LL_RCC_PLLM_DIV_9
4338 * @arg @ref LL_RCC_PLLM_DIV_10
4339 * @arg @ref LL_RCC_PLLM_DIV_11
4340 * @arg @ref LL_RCC_PLLM_DIV_12
4341 * @arg @ref LL_RCC_PLLM_DIV_13
4342 * @arg @ref LL_RCC_PLLM_DIV_14
4343 * @arg @ref LL_RCC_PLLM_DIV_15
4344 * @arg @ref LL_RCC_PLLM_DIV_16
4345 * @arg @ref LL_RCC_PLLM_DIV_17
4346 * @arg @ref LL_RCC_PLLM_DIV_18
4347 * @arg @ref LL_RCC_PLLM_DIV_19
4348 * @arg @ref LL_RCC_PLLM_DIV_20
4349 * @arg @ref LL_RCC_PLLM_DIV_21
4350 * @arg @ref LL_RCC_PLLM_DIV_22
4351 * @arg @ref LL_RCC_PLLM_DIV_23
4352 * @arg @ref LL_RCC_PLLM_DIV_24
4353 * @arg @ref LL_RCC_PLLM_DIV_25
4354 * @arg @ref LL_RCC_PLLM_DIV_26
4355 * @arg @ref LL_RCC_PLLM_DIV_27
4356 * @arg @ref LL_RCC_PLLM_DIV_28
4357 * @arg @ref LL_RCC_PLLM_DIV_29
4358 * @arg @ref LL_RCC_PLLM_DIV_30
4359 * @arg @ref LL_RCC_PLLM_DIV_31
4360 * @arg @ref LL_RCC_PLLM_DIV_32
4361 * @arg @ref LL_RCC_PLLM_DIV_33
4362 * @arg @ref LL_RCC_PLLM_DIV_34
4363 * @arg @ref LL_RCC_PLLM_DIV_35
4364 * @arg @ref LL_RCC_PLLM_DIV_36
4365 * @arg @ref LL_RCC_PLLM_DIV_37
4366 * @arg @ref LL_RCC_PLLM_DIV_38
4367 * @arg @ref LL_RCC_PLLM_DIV_39
4368 * @arg @ref LL_RCC_PLLM_DIV_40
4369 * @arg @ref LL_RCC_PLLM_DIV_41
4370 * @arg @ref LL_RCC_PLLM_DIV_42
4371 * @arg @ref LL_RCC_PLLM_DIV_43
4372 * @arg @ref LL_RCC_PLLM_DIV_44
4373 * @arg @ref LL_RCC_PLLM_DIV_45
4374 * @arg @ref LL_RCC_PLLM_DIV_46
4375 * @arg @ref LL_RCC_PLLM_DIV_47
4376 * @arg @ref LL_RCC_PLLM_DIV_48
4377 * @arg @ref LL_RCC_PLLM_DIV_49
4378 * @arg @ref LL_RCC_PLLM_DIV_50
4379 * @arg @ref LL_RCC_PLLM_DIV_51
4380 * @arg @ref LL_RCC_PLLM_DIV_52
4381 * @arg @ref LL_RCC_PLLM_DIV_53
4382 * @arg @ref LL_RCC_PLLM_DIV_54
4383 * @arg @ref LL_RCC_PLLM_DIV_55
4384 * @arg @ref LL_RCC_PLLM_DIV_56
4385 * @arg @ref LL_RCC_PLLM_DIV_57
4386 * @arg @ref LL_RCC_PLLM_DIV_58
4387 * @arg @ref LL_RCC_PLLM_DIV_59
4388 * @arg @ref LL_RCC_PLLM_DIV_60
4389 * @arg @ref LL_RCC_PLLM_DIV_61
4390 * @arg @ref LL_RCC_PLLM_DIV_62
4391 * @arg @ref LL_RCC_PLLM_DIV_63
4392 * @param PLLN Between 50/192(*) and 432
4393 *
4394 * (*) value not defined in all devices.
4395 * @param PLLQ This parameter can be one of the following values:
4396 * @arg @ref LL_RCC_PLLQ_DIV_2
4397 * @arg @ref LL_RCC_PLLQ_DIV_3
4398 * @arg @ref LL_RCC_PLLQ_DIV_4
4399 * @arg @ref LL_RCC_PLLQ_DIV_5
4400 * @arg @ref LL_RCC_PLLQ_DIV_6
4401 * @arg @ref LL_RCC_PLLQ_DIV_7
4402 * @arg @ref LL_RCC_PLLQ_DIV_8
4403 * @arg @ref LL_RCC_PLLQ_DIV_9
4404 * @arg @ref LL_RCC_PLLQ_DIV_10
4405 * @arg @ref LL_RCC_PLLQ_DIV_11
4406 * @arg @ref LL_RCC_PLLQ_DIV_12
4407 * @arg @ref LL_RCC_PLLQ_DIV_13
4408 * @arg @ref LL_RCC_PLLQ_DIV_14
4409 * @arg @ref LL_RCC_PLLQ_DIV_15
4410 * @retval None
4411 */
LL_RCC_PLL_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)4412 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
4413 {
4414 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
4415 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
4416 }
4417
4418 #if defined(DSI)
4419 /**
4420 * @brief Configure PLL used for DSI clock
4421 * @note PLL Source and PLLM Divider can be written only when PLL,
4422 * PLLI2S and PLLSAI are disabled
4423 * @note PLLN/PLLR can be written only when PLL is disabled
4424 * @note This can be selected for DSI
4425 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
4426 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
4427 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
4428 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
4429 * @param Source This parameter can be one of the following values:
4430 * @arg @ref LL_RCC_PLLSOURCE_HSI
4431 * @arg @ref LL_RCC_PLLSOURCE_HSE
4432 * @param PLLM This parameter can be one of the following values:
4433 * @arg @ref LL_RCC_PLLM_DIV_2
4434 * @arg @ref LL_RCC_PLLM_DIV_3
4435 * @arg @ref LL_RCC_PLLM_DIV_4
4436 * @arg @ref LL_RCC_PLLM_DIV_5
4437 * @arg @ref LL_RCC_PLLM_DIV_6
4438 * @arg @ref LL_RCC_PLLM_DIV_7
4439 * @arg @ref LL_RCC_PLLM_DIV_8
4440 * @arg @ref LL_RCC_PLLM_DIV_9
4441 * @arg @ref LL_RCC_PLLM_DIV_10
4442 * @arg @ref LL_RCC_PLLM_DIV_11
4443 * @arg @ref LL_RCC_PLLM_DIV_12
4444 * @arg @ref LL_RCC_PLLM_DIV_13
4445 * @arg @ref LL_RCC_PLLM_DIV_14
4446 * @arg @ref LL_RCC_PLLM_DIV_15
4447 * @arg @ref LL_RCC_PLLM_DIV_16
4448 * @arg @ref LL_RCC_PLLM_DIV_17
4449 * @arg @ref LL_RCC_PLLM_DIV_18
4450 * @arg @ref LL_RCC_PLLM_DIV_19
4451 * @arg @ref LL_RCC_PLLM_DIV_20
4452 * @arg @ref LL_RCC_PLLM_DIV_21
4453 * @arg @ref LL_RCC_PLLM_DIV_22
4454 * @arg @ref LL_RCC_PLLM_DIV_23
4455 * @arg @ref LL_RCC_PLLM_DIV_24
4456 * @arg @ref LL_RCC_PLLM_DIV_25
4457 * @arg @ref LL_RCC_PLLM_DIV_26
4458 * @arg @ref LL_RCC_PLLM_DIV_27
4459 * @arg @ref LL_RCC_PLLM_DIV_28
4460 * @arg @ref LL_RCC_PLLM_DIV_29
4461 * @arg @ref LL_RCC_PLLM_DIV_30
4462 * @arg @ref LL_RCC_PLLM_DIV_31
4463 * @arg @ref LL_RCC_PLLM_DIV_32
4464 * @arg @ref LL_RCC_PLLM_DIV_33
4465 * @arg @ref LL_RCC_PLLM_DIV_34
4466 * @arg @ref LL_RCC_PLLM_DIV_35
4467 * @arg @ref LL_RCC_PLLM_DIV_36
4468 * @arg @ref LL_RCC_PLLM_DIV_37
4469 * @arg @ref LL_RCC_PLLM_DIV_38
4470 * @arg @ref LL_RCC_PLLM_DIV_39
4471 * @arg @ref LL_RCC_PLLM_DIV_40
4472 * @arg @ref LL_RCC_PLLM_DIV_41
4473 * @arg @ref LL_RCC_PLLM_DIV_42
4474 * @arg @ref LL_RCC_PLLM_DIV_43
4475 * @arg @ref LL_RCC_PLLM_DIV_44
4476 * @arg @ref LL_RCC_PLLM_DIV_45
4477 * @arg @ref LL_RCC_PLLM_DIV_46
4478 * @arg @ref LL_RCC_PLLM_DIV_47
4479 * @arg @ref LL_RCC_PLLM_DIV_48
4480 * @arg @ref LL_RCC_PLLM_DIV_49
4481 * @arg @ref LL_RCC_PLLM_DIV_50
4482 * @arg @ref LL_RCC_PLLM_DIV_51
4483 * @arg @ref LL_RCC_PLLM_DIV_52
4484 * @arg @ref LL_RCC_PLLM_DIV_53
4485 * @arg @ref LL_RCC_PLLM_DIV_54
4486 * @arg @ref LL_RCC_PLLM_DIV_55
4487 * @arg @ref LL_RCC_PLLM_DIV_56
4488 * @arg @ref LL_RCC_PLLM_DIV_57
4489 * @arg @ref LL_RCC_PLLM_DIV_58
4490 * @arg @ref LL_RCC_PLLM_DIV_59
4491 * @arg @ref LL_RCC_PLLM_DIV_60
4492 * @arg @ref LL_RCC_PLLM_DIV_61
4493 * @arg @ref LL_RCC_PLLM_DIV_62
4494 * @arg @ref LL_RCC_PLLM_DIV_63
4495 * @param PLLN Between 50 and 432
4496 * @param PLLR This parameter can be one of the following values:
4497 * @arg @ref LL_RCC_PLLR_DIV_2
4498 * @arg @ref LL_RCC_PLLR_DIV_3
4499 * @arg @ref LL_RCC_PLLR_DIV_4
4500 * @arg @ref LL_RCC_PLLR_DIV_5
4501 * @arg @ref LL_RCC_PLLR_DIV_6
4502 * @arg @ref LL_RCC_PLLR_DIV_7
4503 * @retval None
4504 */
LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4505 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4506 {
4507 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4508 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4509 }
4510 #endif /* DSI */
4511
4512 #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
4513 /**
4514 * @brief Configure PLL used for I2S clock
4515 * @note PLL Source and PLLM Divider can be written only when PLL,
4516 * PLLI2S and PLLSAI are disabled
4517 * @note PLLN/PLLR can be written only when PLL is disabled
4518 * @note This can be selected for I2S
4519 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n
4520 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n
4521 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n
4522 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S
4523 * @param Source This parameter can be one of the following values:
4524 * @arg @ref LL_RCC_PLLSOURCE_HSI
4525 * @arg @ref LL_RCC_PLLSOURCE_HSE
4526 * @param PLLM This parameter can be one of the following values:
4527 * @arg @ref LL_RCC_PLLM_DIV_2
4528 * @arg @ref LL_RCC_PLLM_DIV_3
4529 * @arg @ref LL_RCC_PLLM_DIV_4
4530 * @arg @ref LL_RCC_PLLM_DIV_5
4531 * @arg @ref LL_RCC_PLLM_DIV_6
4532 * @arg @ref LL_RCC_PLLM_DIV_7
4533 * @arg @ref LL_RCC_PLLM_DIV_8
4534 * @arg @ref LL_RCC_PLLM_DIV_9
4535 * @arg @ref LL_RCC_PLLM_DIV_10
4536 * @arg @ref LL_RCC_PLLM_DIV_11
4537 * @arg @ref LL_RCC_PLLM_DIV_12
4538 * @arg @ref LL_RCC_PLLM_DIV_13
4539 * @arg @ref LL_RCC_PLLM_DIV_14
4540 * @arg @ref LL_RCC_PLLM_DIV_15
4541 * @arg @ref LL_RCC_PLLM_DIV_16
4542 * @arg @ref LL_RCC_PLLM_DIV_17
4543 * @arg @ref LL_RCC_PLLM_DIV_18
4544 * @arg @ref LL_RCC_PLLM_DIV_19
4545 * @arg @ref LL_RCC_PLLM_DIV_20
4546 * @arg @ref LL_RCC_PLLM_DIV_21
4547 * @arg @ref LL_RCC_PLLM_DIV_22
4548 * @arg @ref LL_RCC_PLLM_DIV_23
4549 * @arg @ref LL_RCC_PLLM_DIV_24
4550 * @arg @ref LL_RCC_PLLM_DIV_25
4551 * @arg @ref LL_RCC_PLLM_DIV_26
4552 * @arg @ref LL_RCC_PLLM_DIV_27
4553 * @arg @ref LL_RCC_PLLM_DIV_28
4554 * @arg @ref LL_RCC_PLLM_DIV_29
4555 * @arg @ref LL_RCC_PLLM_DIV_30
4556 * @arg @ref LL_RCC_PLLM_DIV_31
4557 * @arg @ref LL_RCC_PLLM_DIV_32
4558 * @arg @ref LL_RCC_PLLM_DIV_33
4559 * @arg @ref LL_RCC_PLLM_DIV_34
4560 * @arg @ref LL_RCC_PLLM_DIV_35
4561 * @arg @ref LL_RCC_PLLM_DIV_36
4562 * @arg @ref LL_RCC_PLLM_DIV_37
4563 * @arg @ref LL_RCC_PLLM_DIV_38
4564 * @arg @ref LL_RCC_PLLM_DIV_39
4565 * @arg @ref LL_RCC_PLLM_DIV_40
4566 * @arg @ref LL_RCC_PLLM_DIV_41
4567 * @arg @ref LL_RCC_PLLM_DIV_42
4568 * @arg @ref LL_RCC_PLLM_DIV_43
4569 * @arg @ref LL_RCC_PLLM_DIV_44
4570 * @arg @ref LL_RCC_PLLM_DIV_45
4571 * @arg @ref LL_RCC_PLLM_DIV_46
4572 * @arg @ref LL_RCC_PLLM_DIV_47
4573 * @arg @ref LL_RCC_PLLM_DIV_48
4574 * @arg @ref LL_RCC_PLLM_DIV_49
4575 * @arg @ref LL_RCC_PLLM_DIV_50
4576 * @arg @ref LL_RCC_PLLM_DIV_51
4577 * @arg @ref LL_RCC_PLLM_DIV_52
4578 * @arg @ref LL_RCC_PLLM_DIV_53
4579 * @arg @ref LL_RCC_PLLM_DIV_54
4580 * @arg @ref LL_RCC_PLLM_DIV_55
4581 * @arg @ref LL_RCC_PLLM_DIV_56
4582 * @arg @ref LL_RCC_PLLM_DIV_57
4583 * @arg @ref LL_RCC_PLLM_DIV_58
4584 * @arg @ref LL_RCC_PLLM_DIV_59
4585 * @arg @ref LL_RCC_PLLM_DIV_60
4586 * @arg @ref LL_RCC_PLLM_DIV_61
4587 * @arg @ref LL_RCC_PLLM_DIV_62
4588 * @arg @ref LL_RCC_PLLM_DIV_63
4589 * @param PLLN Between 50 and 432
4590 * @param PLLR This parameter can be one of the following values:
4591 * @arg @ref LL_RCC_PLLR_DIV_2
4592 * @arg @ref LL_RCC_PLLR_DIV_3
4593 * @arg @ref LL_RCC_PLLR_DIV_4
4594 * @arg @ref LL_RCC_PLLR_DIV_5
4595 * @arg @ref LL_RCC_PLLR_DIV_6
4596 * @arg @ref LL_RCC_PLLR_DIV_7
4597 * @retval None
4598 */
LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4599 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4600 {
4601 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4602 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4603 }
4604 #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
4605
4606 #if defined(SPDIFRX)
4607 /**
4608 * @brief Configure PLL used for SPDIFRX clock
4609 * @note PLL Source and PLLM Divider can be written only when PLL,
4610 * PLLI2S and PLLSAI are disabled
4611 * @note PLLN/PLLR can be written only when PLL is disabled
4612 * @note This can be selected for SPDIFRX
4613 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4614 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4615 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4616 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX
4617 * @param Source This parameter can be one of the following values:
4618 * @arg @ref LL_RCC_PLLSOURCE_HSI
4619 * @arg @ref LL_RCC_PLLSOURCE_HSE
4620 * @param PLLM This parameter can be one of the following values:
4621 * @arg @ref LL_RCC_PLLM_DIV_2
4622 * @arg @ref LL_RCC_PLLM_DIV_3
4623 * @arg @ref LL_RCC_PLLM_DIV_4
4624 * @arg @ref LL_RCC_PLLM_DIV_5
4625 * @arg @ref LL_RCC_PLLM_DIV_6
4626 * @arg @ref LL_RCC_PLLM_DIV_7
4627 * @arg @ref LL_RCC_PLLM_DIV_8
4628 * @arg @ref LL_RCC_PLLM_DIV_9
4629 * @arg @ref LL_RCC_PLLM_DIV_10
4630 * @arg @ref LL_RCC_PLLM_DIV_11
4631 * @arg @ref LL_RCC_PLLM_DIV_12
4632 * @arg @ref LL_RCC_PLLM_DIV_13
4633 * @arg @ref LL_RCC_PLLM_DIV_14
4634 * @arg @ref LL_RCC_PLLM_DIV_15
4635 * @arg @ref LL_RCC_PLLM_DIV_16
4636 * @arg @ref LL_RCC_PLLM_DIV_17
4637 * @arg @ref LL_RCC_PLLM_DIV_18
4638 * @arg @ref LL_RCC_PLLM_DIV_19
4639 * @arg @ref LL_RCC_PLLM_DIV_20
4640 * @arg @ref LL_RCC_PLLM_DIV_21
4641 * @arg @ref LL_RCC_PLLM_DIV_22
4642 * @arg @ref LL_RCC_PLLM_DIV_23
4643 * @arg @ref LL_RCC_PLLM_DIV_24
4644 * @arg @ref LL_RCC_PLLM_DIV_25
4645 * @arg @ref LL_RCC_PLLM_DIV_26
4646 * @arg @ref LL_RCC_PLLM_DIV_27
4647 * @arg @ref LL_RCC_PLLM_DIV_28
4648 * @arg @ref LL_RCC_PLLM_DIV_29
4649 * @arg @ref LL_RCC_PLLM_DIV_30
4650 * @arg @ref LL_RCC_PLLM_DIV_31
4651 * @arg @ref LL_RCC_PLLM_DIV_32
4652 * @arg @ref LL_RCC_PLLM_DIV_33
4653 * @arg @ref LL_RCC_PLLM_DIV_34
4654 * @arg @ref LL_RCC_PLLM_DIV_35
4655 * @arg @ref LL_RCC_PLLM_DIV_36
4656 * @arg @ref LL_RCC_PLLM_DIV_37
4657 * @arg @ref LL_RCC_PLLM_DIV_38
4658 * @arg @ref LL_RCC_PLLM_DIV_39
4659 * @arg @ref LL_RCC_PLLM_DIV_40
4660 * @arg @ref LL_RCC_PLLM_DIV_41
4661 * @arg @ref LL_RCC_PLLM_DIV_42
4662 * @arg @ref LL_RCC_PLLM_DIV_43
4663 * @arg @ref LL_RCC_PLLM_DIV_44
4664 * @arg @ref LL_RCC_PLLM_DIV_45
4665 * @arg @ref LL_RCC_PLLM_DIV_46
4666 * @arg @ref LL_RCC_PLLM_DIV_47
4667 * @arg @ref LL_RCC_PLLM_DIV_48
4668 * @arg @ref LL_RCC_PLLM_DIV_49
4669 * @arg @ref LL_RCC_PLLM_DIV_50
4670 * @arg @ref LL_RCC_PLLM_DIV_51
4671 * @arg @ref LL_RCC_PLLM_DIV_52
4672 * @arg @ref LL_RCC_PLLM_DIV_53
4673 * @arg @ref LL_RCC_PLLM_DIV_54
4674 * @arg @ref LL_RCC_PLLM_DIV_55
4675 * @arg @ref LL_RCC_PLLM_DIV_56
4676 * @arg @ref LL_RCC_PLLM_DIV_57
4677 * @arg @ref LL_RCC_PLLM_DIV_58
4678 * @arg @ref LL_RCC_PLLM_DIV_59
4679 * @arg @ref LL_RCC_PLLM_DIV_60
4680 * @arg @ref LL_RCC_PLLM_DIV_61
4681 * @arg @ref LL_RCC_PLLM_DIV_62
4682 * @arg @ref LL_RCC_PLLM_DIV_63
4683 * @param PLLN Between 50 and 432
4684 * @param PLLR This parameter can be one of the following values:
4685 * @arg @ref LL_RCC_PLLR_DIV_2
4686 * @arg @ref LL_RCC_PLLR_DIV_3
4687 * @arg @ref LL_RCC_PLLR_DIV_4
4688 * @arg @ref LL_RCC_PLLR_DIV_5
4689 * @arg @ref LL_RCC_PLLR_DIV_6
4690 * @arg @ref LL_RCC_PLLR_DIV_7
4691 * @retval None
4692 */
LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4693 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4694 {
4695 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4696 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4697 }
4698 #endif /* SPDIFRX */
4699
4700 #if defined(RCC_PLLCFGR_PLLR)
4701 #if defined(SAI1)
4702 /**
4703 * @brief Configure PLL used for SAI clock
4704 * @note PLL Source and PLLM Divider can be written only when PLL,
4705 * PLLI2S and PLLSAI are disabled
4706 * @note PLLN/PLLR can be written only when PLL is disabled
4707 * @note This can be selected for SAI
4708 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
4709 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
4710 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
4711 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n
4712 * DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI
4713 * @param Source This parameter can be one of the following values:
4714 * @arg @ref LL_RCC_PLLSOURCE_HSI
4715 * @arg @ref LL_RCC_PLLSOURCE_HSE
4716 * @param PLLM This parameter can be one of the following values:
4717 * @arg @ref LL_RCC_PLLM_DIV_2
4718 * @arg @ref LL_RCC_PLLM_DIV_3
4719 * @arg @ref LL_RCC_PLLM_DIV_4
4720 * @arg @ref LL_RCC_PLLM_DIV_5
4721 * @arg @ref LL_RCC_PLLM_DIV_6
4722 * @arg @ref LL_RCC_PLLM_DIV_7
4723 * @arg @ref LL_RCC_PLLM_DIV_8
4724 * @arg @ref LL_RCC_PLLM_DIV_9
4725 * @arg @ref LL_RCC_PLLM_DIV_10
4726 * @arg @ref LL_RCC_PLLM_DIV_11
4727 * @arg @ref LL_RCC_PLLM_DIV_12
4728 * @arg @ref LL_RCC_PLLM_DIV_13
4729 * @arg @ref LL_RCC_PLLM_DIV_14
4730 * @arg @ref LL_RCC_PLLM_DIV_15
4731 * @arg @ref LL_RCC_PLLM_DIV_16
4732 * @arg @ref LL_RCC_PLLM_DIV_17
4733 * @arg @ref LL_RCC_PLLM_DIV_18
4734 * @arg @ref LL_RCC_PLLM_DIV_19
4735 * @arg @ref LL_RCC_PLLM_DIV_20
4736 * @arg @ref LL_RCC_PLLM_DIV_21
4737 * @arg @ref LL_RCC_PLLM_DIV_22
4738 * @arg @ref LL_RCC_PLLM_DIV_23
4739 * @arg @ref LL_RCC_PLLM_DIV_24
4740 * @arg @ref LL_RCC_PLLM_DIV_25
4741 * @arg @ref LL_RCC_PLLM_DIV_26
4742 * @arg @ref LL_RCC_PLLM_DIV_27
4743 * @arg @ref LL_RCC_PLLM_DIV_28
4744 * @arg @ref LL_RCC_PLLM_DIV_29
4745 * @arg @ref LL_RCC_PLLM_DIV_30
4746 * @arg @ref LL_RCC_PLLM_DIV_31
4747 * @arg @ref LL_RCC_PLLM_DIV_32
4748 * @arg @ref LL_RCC_PLLM_DIV_33
4749 * @arg @ref LL_RCC_PLLM_DIV_34
4750 * @arg @ref LL_RCC_PLLM_DIV_35
4751 * @arg @ref LL_RCC_PLLM_DIV_36
4752 * @arg @ref LL_RCC_PLLM_DIV_37
4753 * @arg @ref LL_RCC_PLLM_DIV_38
4754 * @arg @ref LL_RCC_PLLM_DIV_39
4755 * @arg @ref LL_RCC_PLLM_DIV_40
4756 * @arg @ref LL_RCC_PLLM_DIV_41
4757 * @arg @ref LL_RCC_PLLM_DIV_42
4758 * @arg @ref LL_RCC_PLLM_DIV_43
4759 * @arg @ref LL_RCC_PLLM_DIV_44
4760 * @arg @ref LL_RCC_PLLM_DIV_45
4761 * @arg @ref LL_RCC_PLLM_DIV_46
4762 * @arg @ref LL_RCC_PLLM_DIV_47
4763 * @arg @ref LL_RCC_PLLM_DIV_48
4764 * @arg @ref LL_RCC_PLLM_DIV_49
4765 * @arg @ref LL_RCC_PLLM_DIV_50
4766 * @arg @ref LL_RCC_PLLM_DIV_51
4767 * @arg @ref LL_RCC_PLLM_DIV_52
4768 * @arg @ref LL_RCC_PLLM_DIV_53
4769 * @arg @ref LL_RCC_PLLM_DIV_54
4770 * @arg @ref LL_RCC_PLLM_DIV_55
4771 * @arg @ref LL_RCC_PLLM_DIV_56
4772 * @arg @ref LL_RCC_PLLM_DIV_57
4773 * @arg @ref LL_RCC_PLLM_DIV_58
4774 * @arg @ref LL_RCC_PLLM_DIV_59
4775 * @arg @ref LL_RCC_PLLM_DIV_60
4776 * @arg @ref LL_RCC_PLLM_DIV_61
4777 * @arg @ref LL_RCC_PLLM_DIV_62
4778 * @arg @ref LL_RCC_PLLM_DIV_63
4779 * @param PLLN Between 50 and 432
4780 * @param PLLR This parameter can be one of the following values:
4781 * @arg @ref LL_RCC_PLLR_DIV_2
4782 * @arg @ref LL_RCC_PLLR_DIV_3
4783 * @arg @ref LL_RCC_PLLR_DIV_4
4784 * @arg @ref LL_RCC_PLLR_DIV_5
4785 * @arg @ref LL_RCC_PLLR_DIV_6
4786 * @arg @ref LL_RCC_PLLR_DIV_7
4787 * @param PLLDIVR This parameter can be one of the following values:
4788 * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
4789 * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
4790 * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
4791 * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
4792 * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
4793 * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
4794 * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
4795 * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
4796 * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
4797 * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
4798 * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
4799 * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
4800 * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
4801 * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
4802 * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
4803 * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
4804 * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
4805 * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
4806 * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
4807 * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
4808 * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
4809 * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
4810 * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
4811 * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
4812 * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
4813 * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
4814 * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
4815 * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
4816 * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
4817 * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
4818 * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
4819 *
4820 * (*) value not defined in all devices.
4821 * @retval None
4822 */
4823 #if defined(RCC_DCKCFGR_PLLDIVR)
LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR,uint32_t PLLDIVR)4824 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
4825 #else
4826 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4827 #endif /* RCC_DCKCFGR_PLLDIVR */
4828 {
4829 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4830 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4831 #if defined(RCC_DCKCFGR_PLLDIVR)
4832 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);
4833 #endif /* RCC_DCKCFGR_PLLDIVR */
4834 }
4835 #endif /* SAI1 */
4836 #endif /* RCC_PLLCFGR_PLLR */
4837
4838 /**
4839 * @brief Configure PLL clock source
4840 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
4841 * @param PLLSource This parameter can be one of the following values:
4842 * @arg @ref LL_RCC_PLLSOURCE_HSI
4843 * @arg @ref LL_RCC_PLLSOURCE_HSE
4844 * @retval None
4845 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)4846 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
4847 {
4848 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
4849 }
4850
4851 /**
4852 * @brief Get the oscillator used as PLL clock source.
4853 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
4854 * @retval Returned value can be one of the following values:
4855 * @arg @ref LL_RCC_PLLSOURCE_HSI
4856 * @arg @ref LL_RCC_PLLSOURCE_HSE
4857 */
LL_RCC_PLL_GetMainSource(void)4858 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
4859 {
4860 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
4861 }
4862
4863 /**
4864 * @brief Get Main PLL multiplication factor for VCO
4865 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
4866 * @retval Between 50/192(*) and 432
4867 *
4868 * (*) value not defined in all devices.
4869 */
LL_RCC_PLL_GetN(void)4870 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
4871 {
4872 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
4873 }
4874
4875 /**
4876 * @brief Get Main PLL division factor for PLLP
4877 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
4878 * @retval Returned value can be one of the following values:
4879 * @arg @ref LL_RCC_PLLP_DIV_2
4880 * @arg @ref LL_RCC_PLLP_DIV_4
4881 * @arg @ref LL_RCC_PLLP_DIV_6
4882 * @arg @ref LL_RCC_PLLP_DIV_8
4883 */
LL_RCC_PLL_GetP(void)4884 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
4885 {
4886 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
4887 }
4888
4889 /**
4890 * @brief Get Main PLL division factor for PLLQ
4891 * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
4892 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
4893 * @retval Returned value can be one of the following values:
4894 * @arg @ref LL_RCC_PLLQ_DIV_2
4895 * @arg @ref LL_RCC_PLLQ_DIV_3
4896 * @arg @ref LL_RCC_PLLQ_DIV_4
4897 * @arg @ref LL_RCC_PLLQ_DIV_5
4898 * @arg @ref LL_RCC_PLLQ_DIV_6
4899 * @arg @ref LL_RCC_PLLQ_DIV_7
4900 * @arg @ref LL_RCC_PLLQ_DIV_8
4901 * @arg @ref LL_RCC_PLLQ_DIV_9
4902 * @arg @ref LL_RCC_PLLQ_DIV_10
4903 * @arg @ref LL_RCC_PLLQ_DIV_11
4904 * @arg @ref LL_RCC_PLLQ_DIV_12
4905 * @arg @ref LL_RCC_PLLQ_DIV_13
4906 * @arg @ref LL_RCC_PLLQ_DIV_14
4907 * @arg @ref LL_RCC_PLLQ_DIV_15
4908 */
LL_RCC_PLL_GetQ(void)4909 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
4910 {
4911 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
4912 }
4913
4914 #if defined(RCC_PLLCFGR_PLLR)
4915 /**
4916 * @brief Get Main PLL division factor for PLLR
4917 * @note used for PLLCLK (system clock)
4918 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
4919 * @retval Returned value can be one of the following values:
4920 * @arg @ref LL_RCC_PLLR_DIV_2
4921 * @arg @ref LL_RCC_PLLR_DIV_3
4922 * @arg @ref LL_RCC_PLLR_DIV_4
4923 * @arg @ref LL_RCC_PLLR_DIV_5
4924 * @arg @ref LL_RCC_PLLR_DIV_6
4925 * @arg @ref LL_RCC_PLLR_DIV_7
4926 */
LL_RCC_PLL_GetR(void)4927 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
4928 {
4929 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
4930 }
4931 #endif /* RCC_PLLCFGR_PLLR */
4932
4933 #if defined(RCC_DCKCFGR_PLLDIVR)
4934 /**
4935 * @brief Get Main PLL division factor for PLLDIVR
4936 * @note used for PLLSAICLK (SAI1 and SAI2 clock)
4937 * @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR
4938 * @retval Returned value can be one of the following values:
4939 * @arg @ref LL_RCC_PLLDIVR_DIV_1
4940 * @arg @ref LL_RCC_PLLDIVR_DIV_2
4941 * @arg @ref LL_RCC_PLLDIVR_DIV_3
4942 * @arg @ref LL_RCC_PLLDIVR_DIV_4
4943 * @arg @ref LL_RCC_PLLDIVR_DIV_5
4944 * @arg @ref LL_RCC_PLLDIVR_DIV_6
4945 * @arg @ref LL_RCC_PLLDIVR_DIV_7
4946 * @arg @ref LL_RCC_PLLDIVR_DIV_8
4947 * @arg @ref LL_RCC_PLLDIVR_DIV_9
4948 * @arg @ref LL_RCC_PLLDIVR_DIV_10
4949 * @arg @ref LL_RCC_PLLDIVR_DIV_11
4950 * @arg @ref LL_RCC_PLLDIVR_DIV_12
4951 * @arg @ref LL_RCC_PLLDIVR_DIV_13
4952 * @arg @ref LL_RCC_PLLDIVR_DIV_14
4953 * @arg @ref LL_RCC_PLLDIVR_DIV_15
4954 * @arg @ref LL_RCC_PLLDIVR_DIV_16
4955 * @arg @ref LL_RCC_PLLDIVR_DIV_17
4956 * @arg @ref LL_RCC_PLLDIVR_DIV_18
4957 * @arg @ref LL_RCC_PLLDIVR_DIV_19
4958 * @arg @ref LL_RCC_PLLDIVR_DIV_20
4959 * @arg @ref LL_RCC_PLLDIVR_DIV_21
4960 * @arg @ref LL_RCC_PLLDIVR_DIV_22
4961 * @arg @ref LL_RCC_PLLDIVR_DIV_23
4962 * @arg @ref LL_RCC_PLLDIVR_DIV_24
4963 * @arg @ref LL_RCC_PLLDIVR_DIV_25
4964 * @arg @ref LL_RCC_PLLDIVR_DIV_26
4965 * @arg @ref LL_RCC_PLLDIVR_DIV_27
4966 * @arg @ref LL_RCC_PLLDIVR_DIV_28
4967 * @arg @ref LL_RCC_PLLDIVR_DIV_29
4968 * @arg @ref LL_RCC_PLLDIVR_DIV_30
4969 * @arg @ref LL_RCC_PLLDIVR_DIV_31
4970 */
LL_RCC_PLL_GetDIVR(void)4971 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)
4972 {
4973 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));
4974 }
4975 #endif /* RCC_DCKCFGR_PLLDIVR */
4976
4977 /**
4978 * @brief Get Division factor for the main PLL and other PLL
4979 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
4980 * @retval Returned value can be one of the following values:
4981 * @arg @ref LL_RCC_PLLM_DIV_2
4982 * @arg @ref LL_RCC_PLLM_DIV_3
4983 * @arg @ref LL_RCC_PLLM_DIV_4
4984 * @arg @ref LL_RCC_PLLM_DIV_5
4985 * @arg @ref LL_RCC_PLLM_DIV_6
4986 * @arg @ref LL_RCC_PLLM_DIV_7
4987 * @arg @ref LL_RCC_PLLM_DIV_8
4988 * @arg @ref LL_RCC_PLLM_DIV_9
4989 * @arg @ref LL_RCC_PLLM_DIV_10
4990 * @arg @ref LL_RCC_PLLM_DIV_11
4991 * @arg @ref LL_RCC_PLLM_DIV_12
4992 * @arg @ref LL_RCC_PLLM_DIV_13
4993 * @arg @ref LL_RCC_PLLM_DIV_14
4994 * @arg @ref LL_RCC_PLLM_DIV_15
4995 * @arg @ref LL_RCC_PLLM_DIV_16
4996 * @arg @ref LL_RCC_PLLM_DIV_17
4997 * @arg @ref LL_RCC_PLLM_DIV_18
4998 * @arg @ref LL_RCC_PLLM_DIV_19
4999 * @arg @ref LL_RCC_PLLM_DIV_20
5000 * @arg @ref LL_RCC_PLLM_DIV_21
5001 * @arg @ref LL_RCC_PLLM_DIV_22
5002 * @arg @ref LL_RCC_PLLM_DIV_23
5003 * @arg @ref LL_RCC_PLLM_DIV_24
5004 * @arg @ref LL_RCC_PLLM_DIV_25
5005 * @arg @ref LL_RCC_PLLM_DIV_26
5006 * @arg @ref LL_RCC_PLLM_DIV_27
5007 * @arg @ref LL_RCC_PLLM_DIV_28
5008 * @arg @ref LL_RCC_PLLM_DIV_29
5009 * @arg @ref LL_RCC_PLLM_DIV_30
5010 * @arg @ref LL_RCC_PLLM_DIV_31
5011 * @arg @ref LL_RCC_PLLM_DIV_32
5012 * @arg @ref LL_RCC_PLLM_DIV_33
5013 * @arg @ref LL_RCC_PLLM_DIV_34
5014 * @arg @ref LL_RCC_PLLM_DIV_35
5015 * @arg @ref LL_RCC_PLLM_DIV_36
5016 * @arg @ref LL_RCC_PLLM_DIV_37
5017 * @arg @ref LL_RCC_PLLM_DIV_38
5018 * @arg @ref LL_RCC_PLLM_DIV_39
5019 * @arg @ref LL_RCC_PLLM_DIV_40
5020 * @arg @ref LL_RCC_PLLM_DIV_41
5021 * @arg @ref LL_RCC_PLLM_DIV_42
5022 * @arg @ref LL_RCC_PLLM_DIV_43
5023 * @arg @ref LL_RCC_PLLM_DIV_44
5024 * @arg @ref LL_RCC_PLLM_DIV_45
5025 * @arg @ref LL_RCC_PLLM_DIV_46
5026 * @arg @ref LL_RCC_PLLM_DIV_47
5027 * @arg @ref LL_RCC_PLLM_DIV_48
5028 * @arg @ref LL_RCC_PLLM_DIV_49
5029 * @arg @ref LL_RCC_PLLM_DIV_50
5030 * @arg @ref LL_RCC_PLLM_DIV_51
5031 * @arg @ref LL_RCC_PLLM_DIV_52
5032 * @arg @ref LL_RCC_PLLM_DIV_53
5033 * @arg @ref LL_RCC_PLLM_DIV_54
5034 * @arg @ref LL_RCC_PLLM_DIV_55
5035 * @arg @ref LL_RCC_PLLM_DIV_56
5036 * @arg @ref LL_RCC_PLLM_DIV_57
5037 * @arg @ref LL_RCC_PLLM_DIV_58
5038 * @arg @ref LL_RCC_PLLM_DIV_59
5039 * @arg @ref LL_RCC_PLLM_DIV_60
5040 * @arg @ref LL_RCC_PLLM_DIV_61
5041 * @arg @ref LL_RCC_PLLM_DIV_62
5042 * @arg @ref LL_RCC_PLLM_DIV_63
5043 */
LL_RCC_PLL_GetDivider(void)5044 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
5045 {
5046 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
5047 }
5048
5049 /**
5050 * @brief Configure Spread Spectrum used for PLL
5051 * @note These bits must be written before enabling PLL
5052 * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
5053 * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
5054 * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
5055 * @param Mod Between Min_Data=0 and Max_Data=8191
5056 * @param Inc Between Min_Data=0 and Max_Data=32767
5057 * @param Sel This parameter can be one of the following values:
5058 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
5059 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
5060 * @retval None
5061 */
LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod,uint32_t Inc,uint32_t Sel)5062 __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
5063 {
5064 MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
5065 }
5066
5067 /**
5068 * @brief Get Spread Spectrum Modulation Period for PLL
5069 * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
5070 * @retval Between Min_Data=0 and Max_Data=8191
5071 */
LL_RCC_PLL_GetPeriodModulation(void)5072 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
5073 {
5074 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
5075 }
5076
5077 /**
5078 * @brief Get Spread Spectrum Incrementation Step for PLL
5079 * @note Must be written before enabling PLL
5080 * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
5081 * @retval Between Min_Data=0 and Max_Data=32767
5082 */
LL_RCC_PLL_GetStepIncrementation(void)5083 __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
5084 {
5085 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
5086 }
5087
5088 /**
5089 * @brief Get Spread Spectrum Selection for PLL
5090 * @note Must be written before enabling PLL
5091 * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
5092 * @retval Returned value can be one of the following values:
5093 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
5094 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
5095 */
LL_RCC_PLL_GetSpreadSelection(void)5096 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
5097 {
5098 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
5099 }
5100
5101 /**
5102 * @brief Enable Spread Spectrum for PLL.
5103 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
5104 * @retval None
5105 */
LL_RCC_PLL_SpreadSpectrum_Enable(void)5106 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
5107 {
5108 SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
5109 }
5110
5111 /**
5112 * @brief Disable Spread Spectrum for PLL.
5113 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
5114 * @retval None
5115 */
LL_RCC_PLL_SpreadSpectrum_Disable(void)5116 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
5117 {
5118 CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
5119 }
5120
5121 /**
5122 * @}
5123 */
5124
5125 #if defined(RCC_PLLI2S_SUPPORT)
5126 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S
5127 * @{
5128 */
5129
5130 /**
5131 * @brief Enable PLLI2S
5132 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
5133 * @retval None
5134 */
LL_RCC_PLLI2S_Enable(void)5135 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
5136 {
5137 SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
5138 }
5139
5140 /**
5141 * @brief Disable PLLI2S
5142 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
5143 * @retval None
5144 */
LL_RCC_PLLI2S_Disable(void)5145 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
5146 {
5147 CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
5148 }
5149
5150 /**
5151 * @brief Check if PLLI2S Ready
5152 * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
5153 * @retval State of bit (1 or 0).
5154 */
LL_RCC_PLLI2S_IsReady(void)5155 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
5156 {
5157 return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
5158 }
5159
5160 #if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR))
5161 /**
5162 * @brief Configure PLLI2S used for SAI domain clock
5163 * @note PLL Source and PLLM Divider can be written only when PLL,
5164 * PLLI2S and PLLSAI(*) are disabled
5165 * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled
5166 * @note This can be selected for SAI
5167 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
5168 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
5169 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
5170 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n
5171 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
5172 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
5173 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n
5174 * DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
5175 * DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI
5176 * @param Source This parameter can be one of the following values:
5177 * @arg @ref LL_RCC_PLLSOURCE_HSI
5178 * @arg @ref LL_RCC_PLLSOURCE_HSE
5179 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5180 *
5181 * (*) value not defined in all devices.
5182 * @param PLLM This parameter can be one of the following values:
5183 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5184 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5185 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5186 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5187 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5188 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5189 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5190 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5191 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5192 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5193 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5194 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5195 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5196 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5197 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5198 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5199 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5200 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5201 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5202 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5203 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5204 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5205 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5206 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5207 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5208 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5209 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5210 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5211 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5212 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5213 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5214 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5215 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5216 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5217 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5218 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5219 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5220 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5221 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5222 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5223 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5224 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5225 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5226 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5227 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5228 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5229 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5230 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5231 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5232 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5233 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5234 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5235 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5236 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5237 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5238 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5239 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5240 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5241 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5242 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5243 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5244 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5245 * @param PLLN Between 50/192(*) and 432
5246 *
5247 * (*) value not defined in all devices.
5248 * @param PLLQ_R This parameter can be one of the following values:
5249 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
5250 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
5251 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
5252 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
5253 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
5254 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
5255 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
5256 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
5257 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
5258 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
5259 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
5260 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
5261 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
5262 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
5263 * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
5264 * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
5265 * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
5266 * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
5267 * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
5268 * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
5269 *
5270 * (*) value not defined in all devices.
5271 * @param PLLDIVQ_R This parameter can be one of the following values:
5272 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
5273 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
5274 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
5275 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
5276 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
5277 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
5278 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
5279 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
5280 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
5281 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
5282 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
5283 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
5284 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
5285 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
5286 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
5287 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
5288 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
5289 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
5290 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
5291 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
5292 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
5293 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
5294 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
5295 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
5296 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
5297 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
5298 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
5299 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
5300 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
5301 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
5302 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
5303 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
5304 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
5305 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
5306 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
5307 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
5308 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
5309 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
5310 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
5311 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
5312 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
5313 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
5314 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
5315 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
5316 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
5317 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
5318 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
5319 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
5320 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
5321 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
5322 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
5323 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
5324 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
5325 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
5326 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
5327 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
5328 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
5329 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
5330 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
5331 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
5332 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
5333 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
5334 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
5335 *
5336 * (*) value not defined in all devices.
5337 * @retval None
5338 */
LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ_R,uint32_t PLLDIVQ_R)5339 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
5340 {
5341 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5342 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5343 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5344 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5345 #else
5346 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5347 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5348 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);
5349 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
5350 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);
5351 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);
5352 #else
5353 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);
5354 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);
5355 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
5356 }
5357 #endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */
5358
5359 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
5360 /**
5361 * @brief Configure PLLI2S used for 48Mhz domain clock
5362 * @note PLL Source and PLLM Divider can be written only when PLL,
5363 * PLLI2S and PLLSAI(*) are disabled
5364 * @note PLLN/PLLQ can be written only when PLLI2S is disabled
5365 * @note This can be selected for RNG, USB, SDIO
5366 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
5367 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
5368 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n
5369 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n
5370 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n
5371 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M
5372 * @param Source This parameter can be one of the following values:
5373 * @arg @ref LL_RCC_PLLSOURCE_HSI
5374 * @arg @ref LL_RCC_PLLSOURCE_HSE
5375 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5376 *
5377 * (*) value not defined in all devices.
5378 * @param PLLM This parameter can be one of the following values:
5379 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5380 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5381 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5382 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5383 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5384 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5385 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5386 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5387 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5388 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5389 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5390 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5391 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5392 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5393 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5394 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5395 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5396 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5397 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5398 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5399 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5400 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5401 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5402 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5403 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5404 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5405 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5406 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5407 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5408 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5409 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5410 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5411 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5412 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5413 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5414 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5415 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5416 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5417 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5418 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5419 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5420 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5421 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5422 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5423 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5424 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5425 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5426 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5427 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5428 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5429 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5430 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5431 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5432 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5433 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5434 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5435 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5436 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5437 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5438 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5439 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5440 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5441 * @param PLLN Between 50 and 432
5442 * @param PLLQ This parameter can be one of the following values:
5443 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
5444 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
5445 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
5446 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
5447 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
5448 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
5449 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
5450 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
5451 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
5452 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
5453 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
5454 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
5455 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
5456 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
5457 * @retval None
5458 */
LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)5459 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
5460 {
5461 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5462 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5463 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5464 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5465 #else
5466 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5467 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5468 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);
5469 }
5470 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
5471
5472 #if defined(SPDIFRX)
5473 /**
5474 * @brief Configure PLLI2S used for SPDIFRX domain clock
5475 * @note PLL Source and PLLM Divider can be written only when PLL,
5476 * PLLI2S and PLLSAI(*) are disabled
5477 * @note PLLN/PLLP can be written only when PLLI2S is disabled
5478 * @note This can be selected for SPDIFRX
5479 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5480 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5481 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5482 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5483 * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
5484 * @param Source This parameter can be one of the following values:
5485 * @arg @ref LL_RCC_PLLSOURCE_HSI
5486 * @arg @ref LL_RCC_PLLSOURCE_HSE
5487 * @param PLLM This parameter can be one of the following values:
5488 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5489 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5490 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5491 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5492 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5493 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5494 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5495 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5496 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5497 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5498 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5499 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5500 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5501 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5502 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5503 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5504 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5505 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5506 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5507 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5508 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5509 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5510 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5511 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5512 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5513 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5514 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5515 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5516 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5517 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5518 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5519 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5520 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5521 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5522 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5523 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5524 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5525 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5526 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5527 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5528 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5529 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5530 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5531 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5532 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5533 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5534 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5535 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5536 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5537 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5538 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5539 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5540 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5541 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5542 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5543 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5544 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5545 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5546 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5547 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5548 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5549 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5550 * @param PLLN Between 50 and 432
5551 * @param PLLP This parameter can be one of the following values:
5552 * @arg @ref LL_RCC_PLLI2SP_DIV_2
5553 * @arg @ref LL_RCC_PLLI2SP_DIV_4
5554 * @arg @ref LL_RCC_PLLI2SP_DIV_6
5555 * @arg @ref LL_RCC_PLLI2SP_DIV_8
5556 * @retval None
5557 */
LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)5558 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
5559 {
5560 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
5561 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5562 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5563 #else
5564 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5565 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5566 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);
5567 }
5568 #endif /* SPDIFRX */
5569
5570 /**
5571 * @brief Configure PLLI2S used for I2S1 domain clock
5572 * @note PLL Source and PLLM Divider can be written only when PLL,
5573 * PLLI2S and PLLSAI(*) are disabled
5574 * @note PLLN/PLLR can be written only when PLLI2S is disabled
5575 * @note This can be selected for I2S
5576 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
5577 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
5578 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
5579 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n
5580 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
5581 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
5582 * @param Source This parameter can be one of the following values:
5583 * @arg @ref LL_RCC_PLLSOURCE_HSI
5584 * @arg @ref LL_RCC_PLLSOURCE_HSE
5585 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5586 *
5587 * (*) value not defined in all devices.
5588 * @param PLLM This parameter can be one of the following values:
5589 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5590 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5591 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5592 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5593 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5594 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5595 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5596 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5597 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5598 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5599 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5600 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5601 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5602 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5603 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5604 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5605 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5606 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5607 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5608 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5609 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5610 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5611 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5612 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5613 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5614 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5615 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5616 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5617 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5618 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5619 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5620 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5621 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5622 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5623 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5624 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5625 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5626 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5627 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5628 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5629 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5630 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5631 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5632 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5633 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5634 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5635 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5636 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5637 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5638 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5639 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5640 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5641 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5642 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5643 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5644 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5645 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5646 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5647 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5648 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5649 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5650 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5651 * @param PLLN Between 50/192(*) and 432
5652 *
5653 * (*) value not defined in all devices.
5654 * @param PLLR This parameter can be one of the following values:
5655 * @arg @ref LL_RCC_PLLI2SR_DIV_2
5656 * @arg @ref LL_RCC_PLLI2SR_DIV_3
5657 * @arg @ref LL_RCC_PLLI2SR_DIV_4
5658 * @arg @ref LL_RCC_PLLI2SR_DIV_5
5659 * @arg @ref LL_RCC_PLLI2SR_DIV_6
5660 * @arg @ref LL_RCC_PLLI2SR_DIV_7
5661 * @retval None
5662 */
LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)5663 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
5664 {
5665 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5666 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5667 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5668 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5669 #else
5670 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5671 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5672 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
5673 }
5674
5675 /**
5676 * @brief Get I2SPLL multiplication factor for VCO
5677 * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
5678 * @retval Between 50/192(*) and 432
5679 *
5680 * (*) value not defined in all devices.
5681 */
LL_RCC_PLLI2S_GetN(void)5682 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
5683 {
5684 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
5685 }
5686
5687 #if defined(RCC_PLLI2SCFGR_PLLI2SQ)
5688 /**
5689 * @brief Get I2SPLL division factor for PLLI2SQ
5690 * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
5691 * @retval Returned value can be one of the following values:
5692 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
5693 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
5694 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
5695 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
5696 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
5697 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
5698 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
5699 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
5700 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
5701 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
5702 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
5703 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
5704 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
5705 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
5706 */
LL_RCC_PLLI2S_GetQ(void)5707 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
5708 {
5709 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
5710 }
5711 #endif /* RCC_PLLI2SCFGR_PLLI2SQ */
5712
5713 /**
5714 * @brief Get I2SPLL division factor for PLLI2SR
5715 * @note used for PLLI2SCLK (I2S clock)
5716 * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
5717 * @retval Returned value can be one of the following values:
5718 * @arg @ref LL_RCC_PLLI2SR_DIV_2
5719 * @arg @ref LL_RCC_PLLI2SR_DIV_3
5720 * @arg @ref LL_RCC_PLLI2SR_DIV_4
5721 * @arg @ref LL_RCC_PLLI2SR_DIV_5
5722 * @arg @ref LL_RCC_PLLI2SR_DIV_6
5723 * @arg @ref LL_RCC_PLLI2SR_DIV_7
5724 */
LL_RCC_PLLI2S_GetR(void)5725 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
5726 {
5727 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
5728 }
5729
5730 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
5731 /**
5732 * @brief Get I2SPLL division factor for PLLI2SP
5733 * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
5734 * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
5735 * @retval Returned value can be one of the following values:
5736 * @arg @ref LL_RCC_PLLI2SP_DIV_2
5737 * @arg @ref LL_RCC_PLLI2SP_DIV_4
5738 * @arg @ref LL_RCC_PLLI2SP_DIV_6
5739 * @arg @ref LL_RCC_PLLI2SP_DIV_8
5740 */
LL_RCC_PLLI2S_GetP(void)5741 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
5742 {
5743 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
5744 }
5745 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
5746
5747 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
5748 /**
5749 * @brief Get I2SPLL division factor for PLLI2SDIVQ
5750 * @note used PLLSAICLK selected (SAI clock)
5751 * @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
5752 * @retval Returned value can be one of the following values:
5753 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
5754 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
5755 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
5756 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
5757 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
5758 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
5759 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
5760 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
5761 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
5762 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
5763 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
5764 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
5765 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
5766 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
5767 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
5768 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
5769 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
5770 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
5771 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
5772 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
5773 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
5774 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
5775 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
5776 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
5777 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
5778 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
5779 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
5780 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
5781 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
5782 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
5783 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
5784 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
5785 */
LL_RCC_PLLI2S_GetDIVQ(void)5786 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
5787 {
5788 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));
5789 }
5790 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
5791
5792 #if defined(RCC_DCKCFGR_PLLI2SDIVR)
5793 /**
5794 * @brief Get I2SPLL division factor for PLLI2SDIVR
5795 * @note used PLLSAICLK selected (SAI clock)
5796 * @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR
5797 * @retval Returned value can be one of the following values:
5798 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1
5799 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2
5800 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3
5801 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4
5802 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5
5803 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6
5804 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7
5805 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8
5806 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9
5807 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10
5808 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11
5809 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12
5810 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13
5811 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14
5812 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15
5813 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16
5814 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17
5815 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18
5816 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19
5817 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20
5818 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21
5819 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22
5820 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23
5821 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24
5822 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25
5823 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26
5824 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27
5825 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28
5826 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29
5827 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30
5828 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31
5829 */
LL_RCC_PLLI2S_GetDIVR(void)5830 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)
5831 {
5832 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));
5833 }
5834 #endif /* RCC_DCKCFGR_PLLI2SDIVR */
5835
5836 /**
5837 * @brief Get division factor for PLLI2S input clock
5838 * @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n
5839 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider
5840 * @retval Returned value can be one of the following values:
5841 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5842 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5843 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5844 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5845 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5846 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5847 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5848 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5849 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5850 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5851 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5852 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5853 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5854 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5855 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5856 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5857 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5858 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5859 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5860 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5861 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5862 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5863 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5864 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5865 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5866 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5867 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5868 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5869 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5870 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5871 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5872 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5873 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5874 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5875 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5876 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5877 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5878 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5879 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5880 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5881 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5882 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5883 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5884 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5885 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5886 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5887 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5888 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5889 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5890 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5891 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5892 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5893 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5894 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5895 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5896 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5897 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5898 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5899 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5900 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5901 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5902 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5903 */
LL_RCC_PLLI2S_GetDivider(void)5904 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
5905 {
5906 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5907 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));
5908 #else
5909 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
5910 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5911 }
5912
5913 /**
5914 * @brief Get the oscillator used as PLL clock source.
5915 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n
5916 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource
5917 * @retval Returned value can be one of the following values:
5918 * @arg @ref LL_RCC_PLLSOURCE_HSI
5919 * @arg @ref LL_RCC_PLLSOURCE_HSE
5920 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5921 *
5922 * (*) value not defined in all devices.
5923 */
LL_RCC_PLLI2S_GetMainSource(void)5924 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
5925 {
5926 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
5927 register uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
5928 register uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
5929 register uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
5930 return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1);
5931 #else
5932 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
5933 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
5934 }
5935
5936 /**
5937 * @}
5938 */
5939 #endif /* RCC_PLLI2S_SUPPORT */
5940
5941 #if defined(RCC_PLLSAI_SUPPORT)
5942 /** @defgroup RCC_LL_EF_PLLSAI PLLSAI
5943 * @{
5944 */
5945
5946 /**
5947 * @brief Enable PLLSAI
5948 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
5949 * @retval None
5950 */
LL_RCC_PLLSAI_Enable(void)5951 __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
5952 {
5953 SET_BIT(RCC->CR, RCC_CR_PLLSAION);
5954 }
5955
5956 /**
5957 * @brief Disable PLLSAI
5958 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
5959 * @retval None
5960 */
LL_RCC_PLLSAI_Disable(void)5961 __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
5962 {
5963 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
5964 }
5965
5966 /**
5967 * @brief Check if PLLSAI Ready
5968 * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
5969 * @retval State of bit (1 or 0).
5970 */
LL_RCC_PLLSAI_IsReady(void)5971 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
5972 {
5973 return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
5974 }
5975
5976 /**
5977 * @brief Configure PLLSAI used for SAI domain clock
5978 * @note PLL Source and PLLM Divider can be written only when PLL,
5979 * PLLI2S and PLLSAI(*) are disabled
5980 * @note PLLN/PLLQ can be written only when PLLSAI is disabled
5981 * @note This can be selected for SAI
5982 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
5983 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
5984 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n
5985 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
5986 * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
5987 * DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
5988 * @param Source This parameter can be one of the following values:
5989 * @arg @ref LL_RCC_PLLSOURCE_HSI
5990 * @arg @ref LL_RCC_PLLSOURCE_HSE
5991 * @param PLLM This parameter can be one of the following values:
5992 * @arg @ref LL_RCC_PLLSAIM_DIV_2
5993 * @arg @ref LL_RCC_PLLSAIM_DIV_3
5994 * @arg @ref LL_RCC_PLLSAIM_DIV_4
5995 * @arg @ref LL_RCC_PLLSAIM_DIV_5
5996 * @arg @ref LL_RCC_PLLSAIM_DIV_6
5997 * @arg @ref LL_RCC_PLLSAIM_DIV_7
5998 * @arg @ref LL_RCC_PLLSAIM_DIV_8
5999 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6000 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6001 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6002 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6003 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6004 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6005 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6006 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6007 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6008 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6009 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6010 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6011 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6012 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6013 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6014 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6015 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6016 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6017 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6018 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6019 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6020 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6021 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6022 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6023 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6024 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6025 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6026 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6027 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6028 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6029 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6030 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6031 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6032 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6033 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6034 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6035 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6036 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6037 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6038 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6039 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6040 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6041 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6042 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6043 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6044 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6045 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6046 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6047 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6048 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6049 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6050 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6051 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6052 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6053 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6054 * @param PLLN Between 49/50(*) and 432
6055 *
6056 * (*) value not defined in all devices.
6057 * @param PLLQ This parameter can be one of the following values:
6058 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
6059 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
6060 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
6061 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
6062 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
6063 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
6064 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
6065 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
6066 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
6067 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
6068 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
6069 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
6070 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
6071 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
6072 * @param PLLDIVQ This parameter can be one of the following values:
6073 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
6074 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
6075 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
6076 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
6077 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
6078 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
6079 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
6080 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
6081 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
6082 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
6083 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
6084 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
6085 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
6086 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
6087 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
6088 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
6089 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
6090 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
6091 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
6092 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
6093 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
6094 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
6095 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
6096 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
6097 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
6098 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
6099 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
6100 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
6101 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
6102 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
6103 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
6104 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
6105 * @retval None
6106 */
LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ,uint32_t PLLDIVQ)6107 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
6108 {
6109 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
6110 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6111 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
6112 #else
6113 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
6114 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6115 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);
6116 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);
6117 }
6118
6119 #if defined(RCC_PLLSAICFGR_PLLSAIP)
6120 /**
6121 * @brief Configure PLLSAI used for 48Mhz domain clock
6122 * @note PLL Source and PLLM Divider can be written only when PLL,
6123 * PLLI2S and PLLSAI(*) are disabled
6124 * @note PLLN/PLLP can be written only when PLLSAI is disabled
6125 * @note This can be selected for USB, RNG, SDIO
6126 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
6127 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
6128 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n
6129 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
6130 * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
6131 * @param Source This parameter can be one of the following values:
6132 * @arg @ref LL_RCC_PLLSOURCE_HSI
6133 * @arg @ref LL_RCC_PLLSOURCE_HSE
6134 * @param PLLM This parameter can be one of the following values:
6135 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6136 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6137 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6138 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6139 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6140 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6141 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6142 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6143 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6144 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6145 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6146 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6147 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6148 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6149 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6150 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6151 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6152 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6153 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6154 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6155 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6156 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6157 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6158 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6159 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6160 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6161 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6162 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6163 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6164 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6165 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6166 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6167 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6168 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6169 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6170 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6171 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6172 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6173 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6174 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6175 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6176 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6177 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6178 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6179 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6180 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6181 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6182 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6183 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6184 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6185 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6186 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6187 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6188 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6189 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6190 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6191 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6192 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6193 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6194 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6195 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6196 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6197 * @param PLLN Between 50 and 432
6198 * @param PLLP This parameter can be one of the following values:
6199 * @arg @ref LL_RCC_PLLSAIP_DIV_2
6200 * @arg @ref LL_RCC_PLLSAIP_DIV_4
6201 * @arg @ref LL_RCC_PLLSAIP_DIV_6
6202 * @arg @ref LL_RCC_PLLSAIP_DIV_8
6203 * @retval None
6204 */
LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)6205 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
6206 {
6207 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
6208 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6209 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
6210 #else
6211 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
6212 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6213 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);
6214 }
6215 #endif /* RCC_PLLSAICFGR_PLLSAIP */
6216
6217 #if defined(LTDC)
6218 /**
6219 * @brief Configure PLLSAI used for LTDC domain clock
6220 * @note PLL Source and PLLM Divider can be written only when PLL,
6221 * PLLI2S and PLLSAI(*) are disabled
6222 * @note PLLN/PLLR can be written only when PLLSAI is disabled
6223 * @note This can be selected for LTDC
6224 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6225 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6226 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6227 * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6228 * DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
6229 * @param Source This parameter can be one of the following values:
6230 * @arg @ref LL_RCC_PLLSOURCE_HSI
6231 * @arg @ref LL_RCC_PLLSOURCE_HSE
6232 * @param PLLM This parameter can be one of the following values:
6233 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6234 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6235 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6236 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6237 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6238 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6239 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6240 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6241 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6242 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6243 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6244 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6245 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6246 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6247 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6248 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6249 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6250 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6251 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6252 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6253 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6254 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6255 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6256 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6257 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6258 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6259 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6260 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6261 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6262 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6263 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6264 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6265 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6266 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6267 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6268 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6269 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6270 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6271 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6272 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6273 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6274 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6275 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6276 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6277 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6278 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6279 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6280 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6281 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6282 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6283 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6284 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6285 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6286 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6287 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6288 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6289 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6290 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6291 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6292 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6293 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6294 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6295 * @param PLLN Between 49/50(*) and 432
6296 *
6297 * (*) value not defined in all devices.
6298 * @param PLLR This parameter can be one of the following values:
6299 * @arg @ref LL_RCC_PLLSAIR_DIV_2
6300 * @arg @ref LL_RCC_PLLSAIR_DIV_3
6301 * @arg @ref LL_RCC_PLLSAIR_DIV_4
6302 * @arg @ref LL_RCC_PLLSAIR_DIV_5
6303 * @arg @ref LL_RCC_PLLSAIR_DIV_6
6304 * @arg @ref LL_RCC_PLLSAIR_DIV_7
6305 * @param PLLDIVR This parameter can be one of the following values:
6306 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
6307 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
6308 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
6309 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
6310 * @retval None
6311 */
LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR,uint32_t PLLDIVR)6312 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
6313 {
6314 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
6315 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);
6316 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);
6317 }
6318 #endif /* LTDC */
6319
6320 /**
6321 * @brief Get division factor for PLLSAI input clock
6322 * @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n
6323 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider
6324 * @retval Returned value can be one of the following values:
6325 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6326 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6327 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6328 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6329 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6330 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6331 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6332 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6333 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6334 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6335 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6336 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6337 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6338 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6339 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6340 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6341 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6342 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6343 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6344 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6345 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6346 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6347 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6348 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6349 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6350 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6351 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6352 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6353 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6354 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6355 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6356 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6357 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6358 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6359 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6360 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6361 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6362 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6363 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6364 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6365 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6366 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6367 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6368 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6369 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6370 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6371 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6372 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6373 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6374 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6375 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6376 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6377 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6378 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6379 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6380 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6381 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6382 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6383 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6384 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6385 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6386 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6387 */
LL_RCC_PLLSAI_GetDivider(void)6388 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)
6389 {
6390 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6391 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));
6392 #else
6393 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
6394 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6395 }
6396
6397 /**
6398 * @brief Get SAIPLL multiplication factor for VCO
6399 * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
6400 * @retval Between 49/50(*) and 432
6401 *
6402 * (*) value not defined in all devices.
6403 */
LL_RCC_PLLSAI_GetN(void)6404 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
6405 {
6406 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
6407 }
6408
6409 /**
6410 * @brief Get SAIPLL division factor for PLLSAIQ
6411 * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
6412 * @retval Returned value can be one of the following values:
6413 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
6414 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
6415 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
6416 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
6417 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
6418 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
6419 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
6420 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
6421 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
6422 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
6423 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
6424 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
6425 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
6426 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
6427 */
LL_RCC_PLLSAI_GetQ(void)6428 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
6429 {
6430 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
6431 }
6432
6433 #if defined(RCC_PLLSAICFGR_PLLSAIR)
6434 /**
6435 * @brief Get SAIPLL division factor for PLLSAIR
6436 * @note used for PLLSAICLK (SAI clock)
6437 * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
6438 * @retval Returned value can be one of the following values:
6439 * @arg @ref LL_RCC_PLLSAIR_DIV_2
6440 * @arg @ref LL_RCC_PLLSAIR_DIV_3
6441 * @arg @ref LL_RCC_PLLSAIR_DIV_4
6442 * @arg @ref LL_RCC_PLLSAIR_DIV_5
6443 * @arg @ref LL_RCC_PLLSAIR_DIV_6
6444 * @arg @ref LL_RCC_PLLSAIR_DIV_7
6445 */
LL_RCC_PLLSAI_GetR(void)6446 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
6447 {
6448 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
6449 }
6450 #endif /* RCC_PLLSAICFGR_PLLSAIR */
6451
6452 #if defined(RCC_PLLSAICFGR_PLLSAIP)
6453 /**
6454 * @brief Get SAIPLL division factor for PLLSAIP
6455 * @note used for PLL48MCLK (48M domain clock)
6456 * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
6457 * @retval Returned value can be one of the following values:
6458 * @arg @ref LL_RCC_PLLSAIP_DIV_2
6459 * @arg @ref LL_RCC_PLLSAIP_DIV_4
6460 * @arg @ref LL_RCC_PLLSAIP_DIV_6
6461 * @arg @ref LL_RCC_PLLSAIP_DIV_8
6462 */
LL_RCC_PLLSAI_GetP(void)6463 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
6464 {
6465 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
6466 }
6467 #endif /* RCC_PLLSAICFGR_PLLSAIP */
6468
6469 /**
6470 * @brief Get SAIPLL division factor for PLLSAIDIVQ
6471 * @note used PLLSAICLK selected (SAI clock)
6472 * @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
6473 * @retval Returned value can be one of the following values:
6474 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
6475 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
6476 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
6477 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
6478 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
6479 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
6480 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
6481 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
6482 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
6483 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
6484 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
6485 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
6486 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
6487 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
6488 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
6489 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
6490 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
6491 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
6492 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
6493 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
6494 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
6495 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
6496 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
6497 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
6498 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
6499 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
6500 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
6501 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
6502 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
6503 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
6504 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
6505 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
6506 */
LL_RCC_PLLSAI_GetDIVQ(void)6507 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
6508 {
6509 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));
6510 }
6511
6512 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
6513 /**
6514 * @brief Get SAIPLL division factor for PLLSAIDIVR
6515 * @note used for LTDC domain clock
6516 * @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
6517 * @retval Returned value can be one of the following values:
6518 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
6519 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
6520 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
6521 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
6522 */
LL_RCC_PLLSAI_GetDIVR(void)6523 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
6524 {
6525 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));
6526 }
6527 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
6528
6529 /**
6530 * @}
6531 */
6532 #endif /* RCC_PLLSAI_SUPPORT */
6533
6534 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
6535 * @{
6536 */
6537
6538 /**
6539 * @brief Clear LSI ready interrupt flag
6540 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
6541 * @retval None
6542 */
LL_RCC_ClearFlag_LSIRDY(void)6543 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
6544 {
6545 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
6546 }
6547
6548 /**
6549 * @brief Clear LSE ready interrupt flag
6550 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
6551 * @retval None
6552 */
LL_RCC_ClearFlag_LSERDY(void)6553 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
6554 {
6555 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
6556 }
6557
6558 /**
6559 * @brief Clear HSI ready interrupt flag
6560 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
6561 * @retval None
6562 */
LL_RCC_ClearFlag_HSIRDY(void)6563 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
6564 {
6565 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
6566 }
6567
6568 /**
6569 * @brief Clear HSE ready interrupt flag
6570 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
6571 * @retval None
6572 */
LL_RCC_ClearFlag_HSERDY(void)6573 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
6574 {
6575 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
6576 }
6577
6578 /**
6579 * @brief Clear PLL ready interrupt flag
6580 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
6581 * @retval None
6582 */
LL_RCC_ClearFlag_PLLRDY(void)6583 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
6584 {
6585 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
6586 }
6587
6588 #if defined(RCC_PLLI2S_SUPPORT)
6589 /**
6590 * @brief Clear PLLI2S ready interrupt flag
6591 * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
6592 * @retval None
6593 */
LL_RCC_ClearFlag_PLLI2SRDY(void)6594 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
6595 {
6596 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
6597 }
6598
6599 #endif /* RCC_PLLI2S_SUPPORT */
6600
6601 #if defined(RCC_PLLSAI_SUPPORT)
6602 /**
6603 * @brief Clear PLLSAI ready interrupt flag
6604 * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
6605 * @retval None
6606 */
LL_RCC_ClearFlag_PLLSAIRDY(void)6607 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
6608 {
6609 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
6610 }
6611
6612 #endif /* RCC_PLLSAI_SUPPORT */
6613
6614 /**
6615 * @brief Clear Clock security system interrupt flag
6616 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
6617 * @retval None
6618 */
LL_RCC_ClearFlag_HSECSS(void)6619 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
6620 {
6621 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
6622 }
6623
6624 /**
6625 * @brief Check if LSI ready interrupt occurred or not
6626 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
6627 * @retval State of bit (1 or 0).
6628 */
LL_RCC_IsActiveFlag_LSIRDY(void)6629 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
6630 {
6631 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
6632 }
6633
6634 /**
6635 * @brief Check if LSE ready interrupt occurred or not
6636 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
6637 * @retval State of bit (1 or 0).
6638 */
LL_RCC_IsActiveFlag_LSERDY(void)6639 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
6640 {
6641 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
6642 }
6643
6644 /**
6645 * @brief Check if HSI ready interrupt occurred or not
6646 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
6647 * @retval State of bit (1 or 0).
6648 */
LL_RCC_IsActiveFlag_HSIRDY(void)6649 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
6650 {
6651 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
6652 }
6653
6654 /**
6655 * @brief Check if HSE ready interrupt occurred or not
6656 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
6657 * @retval State of bit (1 or 0).
6658 */
LL_RCC_IsActiveFlag_HSERDY(void)6659 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
6660 {
6661 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
6662 }
6663
6664 /**
6665 * @brief Check if PLL ready interrupt occurred or not
6666 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
6667 * @retval State of bit (1 or 0).
6668 */
LL_RCC_IsActiveFlag_PLLRDY(void)6669 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
6670 {
6671 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
6672 }
6673
6674 #if defined(RCC_PLLI2S_SUPPORT)
6675 /**
6676 * @brief Check if PLLI2S ready interrupt occurred or not
6677 * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
6678 * @retval State of bit (1 or 0).
6679 */
LL_RCC_IsActiveFlag_PLLI2SRDY(void)6680 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
6681 {
6682 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
6683 }
6684 #endif /* RCC_PLLI2S_SUPPORT */
6685
6686 #if defined(RCC_PLLSAI_SUPPORT)
6687 /**
6688 * @brief Check if PLLSAI ready interrupt occurred or not
6689 * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
6690 * @retval State of bit (1 or 0).
6691 */
LL_RCC_IsActiveFlag_PLLSAIRDY(void)6692 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
6693 {
6694 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
6695 }
6696 #endif /* RCC_PLLSAI_SUPPORT */
6697
6698 /**
6699 * @brief Check if Clock security system interrupt occurred or not
6700 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
6701 * @retval State of bit (1 or 0).
6702 */
LL_RCC_IsActiveFlag_HSECSS(void)6703 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
6704 {
6705 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
6706 }
6707
6708 /**
6709 * @brief Check if RCC flag Independent Watchdog reset is set or not.
6710 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
6711 * @retval State of bit (1 or 0).
6712 */
LL_RCC_IsActiveFlag_IWDGRST(void)6713 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
6714 {
6715 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
6716 }
6717
6718 /**
6719 * @brief Check if RCC flag Low Power reset is set or not.
6720 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
6721 * @retval State of bit (1 or 0).
6722 */
LL_RCC_IsActiveFlag_LPWRRST(void)6723 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
6724 {
6725 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
6726 }
6727
6728 /**
6729 * @brief Check if RCC flag Pin reset is set or not.
6730 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
6731 * @retval State of bit (1 or 0).
6732 */
LL_RCC_IsActiveFlag_PINRST(void)6733 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
6734 {
6735 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
6736 }
6737
6738 /**
6739 * @brief Check if RCC flag POR/PDR reset is set or not.
6740 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
6741 * @retval State of bit (1 or 0).
6742 */
LL_RCC_IsActiveFlag_PORRST(void)6743 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
6744 {
6745 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
6746 }
6747
6748 /**
6749 * @brief Check if RCC flag Software reset is set or not.
6750 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
6751 * @retval State of bit (1 or 0).
6752 */
LL_RCC_IsActiveFlag_SFTRST(void)6753 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
6754 {
6755 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
6756 }
6757
6758 /**
6759 * @brief Check if RCC flag Window Watchdog reset is set or not.
6760 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
6761 * @retval State of bit (1 or 0).
6762 */
LL_RCC_IsActiveFlag_WWDGRST(void)6763 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
6764 {
6765 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
6766 }
6767
6768 #if defined(RCC_CSR_BORRSTF)
6769 /**
6770 * @brief Check if RCC flag BOR reset is set or not.
6771 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
6772 * @retval State of bit (1 or 0).
6773 */
LL_RCC_IsActiveFlag_BORRST(void)6774 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
6775 {
6776 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
6777 }
6778 #endif /* RCC_CSR_BORRSTF */
6779
6780 /**
6781 * @brief Set RMVF bit to clear the reset flags.
6782 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
6783 * @retval None
6784 */
LL_RCC_ClearResetFlags(void)6785 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
6786 {
6787 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
6788 }
6789
6790 /**
6791 * @}
6792 */
6793
6794 /** @defgroup RCC_LL_EF_IT_Management IT Management
6795 * @{
6796 */
6797
6798 /**
6799 * @brief Enable LSI ready interrupt
6800 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
6801 * @retval None
6802 */
LL_RCC_EnableIT_LSIRDY(void)6803 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
6804 {
6805 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
6806 }
6807
6808 /**
6809 * @brief Enable LSE ready interrupt
6810 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
6811 * @retval None
6812 */
LL_RCC_EnableIT_LSERDY(void)6813 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
6814 {
6815 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
6816 }
6817
6818 /**
6819 * @brief Enable HSI ready interrupt
6820 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
6821 * @retval None
6822 */
LL_RCC_EnableIT_HSIRDY(void)6823 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
6824 {
6825 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
6826 }
6827
6828 /**
6829 * @brief Enable HSE ready interrupt
6830 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
6831 * @retval None
6832 */
LL_RCC_EnableIT_HSERDY(void)6833 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
6834 {
6835 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
6836 }
6837
6838 /**
6839 * @brief Enable PLL ready interrupt
6840 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
6841 * @retval None
6842 */
LL_RCC_EnableIT_PLLRDY(void)6843 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
6844 {
6845 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
6846 }
6847
6848 #if defined(RCC_PLLI2S_SUPPORT)
6849 /**
6850 * @brief Enable PLLI2S ready interrupt
6851 * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
6852 * @retval None
6853 */
LL_RCC_EnableIT_PLLI2SRDY(void)6854 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
6855 {
6856 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
6857 }
6858 #endif /* RCC_PLLI2S_SUPPORT */
6859
6860 #if defined(RCC_PLLSAI_SUPPORT)
6861 /**
6862 * @brief Enable PLLSAI ready interrupt
6863 * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
6864 * @retval None
6865 */
LL_RCC_EnableIT_PLLSAIRDY(void)6866 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
6867 {
6868 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
6869 }
6870 #endif /* RCC_PLLSAI_SUPPORT */
6871
6872 /**
6873 * @brief Disable LSI ready interrupt
6874 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
6875 * @retval None
6876 */
LL_RCC_DisableIT_LSIRDY(void)6877 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
6878 {
6879 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
6880 }
6881
6882 /**
6883 * @brief Disable LSE ready interrupt
6884 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
6885 * @retval None
6886 */
LL_RCC_DisableIT_LSERDY(void)6887 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
6888 {
6889 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
6890 }
6891
6892 /**
6893 * @brief Disable HSI ready interrupt
6894 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
6895 * @retval None
6896 */
LL_RCC_DisableIT_HSIRDY(void)6897 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
6898 {
6899 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
6900 }
6901
6902 /**
6903 * @brief Disable HSE ready interrupt
6904 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
6905 * @retval None
6906 */
LL_RCC_DisableIT_HSERDY(void)6907 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
6908 {
6909 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
6910 }
6911
6912 /**
6913 * @brief Disable PLL ready interrupt
6914 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
6915 * @retval None
6916 */
LL_RCC_DisableIT_PLLRDY(void)6917 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
6918 {
6919 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
6920 }
6921
6922 #if defined(RCC_PLLI2S_SUPPORT)
6923 /**
6924 * @brief Disable PLLI2S ready interrupt
6925 * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
6926 * @retval None
6927 */
LL_RCC_DisableIT_PLLI2SRDY(void)6928 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
6929 {
6930 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
6931 }
6932
6933 #endif /* RCC_PLLI2S_SUPPORT */
6934
6935 #if defined(RCC_PLLSAI_SUPPORT)
6936 /**
6937 * @brief Disable PLLSAI ready interrupt
6938 * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
6939 * @retval None
6940 */
LL_RCC_DisableIT_PLLSAIRDY(void)6941 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
6942 {
6943 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
6944 }
6945 #endif /* RCC_PLLSAI_SUPPORT */
6946
6947 /**
6948 * @brief Checks if LSI ready interrupt source is enabled or disabled.
6949 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
6950 * @retval State of bit (1 or 0).
6951 */
LL_RCC_IsEnabledIT_LSIRDY(void)6952 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
6953 {
6954 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
6955 }
6956
6957 /**
6958 * @brief Checks if LSE ready interrupt source is enabled or disabled.
6959 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
6960 * @retval State of bit (1 or 0).
6961 */
LL_RCC_IsEnabledIT_LSERDY(void)6962 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
6963 {
6964 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
6965 }
6966
6967 /**
6968 * @brief Checks if HSI ready interrupt source is enabled or disabled.
6969 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
6970 * @retval State of bit (1 or 0).
6971 */
LL_RCC_IsEnabledIT_HSIRDY(void)6972 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
6973 {
6974 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
6975 }
6976
6977 /**
6978 * @brief Checks if HSE ready interrupt source is enabled or disabled.
6979 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
6980 * @retval State of bit (1 or 0).
6981 */
LL_RCC_IsEnabledIT_HSERDY(void)6982 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
6983 {
6984 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
6985 }
6986
6987 /**
6988 * @brief Checks if PLL ready interrupt source is enabled or disabled.
6989 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
6990 * @retval State of bit (1 or 0).
6991 */
LL_RCC_IsEnabledIT_PLLRDY(void)6992 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
6993 {
6994 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
6995 }
6996
6997 #if defined(RCC_PLLI2S_SUPPORT)
6998 /**
6999 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
7000 * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
7001 * @retval State of bit (1 or 0).
7002 */
LL_RCC_IsEnabledIT_PLLI2SRDY(void)7003 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
7004 {
7005 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
7006 }
7007
7008 #endif /* RCC_PLLI2S_SUPPORT */
7009
7010 #if defined(RCC_PLLSAI_SUPPORT)
7011 /**
7012 * @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
7013 * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
7014 * @retval State of bit (1 or 0).
7015 */
LL_RCC_IsEnabledIT_PLLSAIRDY(void)7016 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
7017 {
7018 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
7019 }
7020 #endif /* RCC_PLLSAI_SUPPORT */
7021
7022 /**
7023 * @}
7024 */
7025
7026 #if defined(USE_FULL_LL_DRIVER)
7027 /** @defgroup RCC_LL_EF_Init De-initialization function
7028 * @{
7029 */
7030 ErrorStatus LL_RCC_DeInit(void);
7031 /**
7032 * @}
7033 */
7034
7035 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
7036 * @{
7037 */
7038 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
7039 #if defined(FMPI2C1)
7040 uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);
7041 #endif /* FMPI2C1 */
7042 #if defined(LPTIM1)
7043 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
7044 #endif /* LPTIM1 */
7045 #if defined(SAI1)
7046 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
7047 #endif /* SAI1 */
7048 #if defined(SDIO)
7049 uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);
7050 #endif /* SDIO */
7051 #if defined(RNG)
7052 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
7053 #endif /* RNG */
7054 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
7055 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
7056 #endif /* USB_OTG_FS || USB_OTG_HS */
7057 #if defined(DFSDM1_Channel0)
7058 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
7059 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
7060 #endif /* DFSDM1_Channel0 */
7061 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
7062 #if defined(CEC)
7063 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
7064 #endif /* CEC */
7065 #if defined(LTDC)
7066 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
7067 #endif /* LTDC */
7068 #if defined(SPDIFRX)
7069 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
7070 #endif /* SPDIFRX */
7071 #if defined(DSI)
7072 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
7073 #endif /* DSI */
7074 /**
7075 * @}
7076 */
7077 #endif /* USE_FULL_LL_DRIVER */
7078
7079 /**
7080 * @}
7081 */
7082
7083 /**
7084 * @}
7085 */
7086
7087 #endif /* defined(RCC) */
7088
7089 /**
7090 * @}
7091 */
7092
7093 #ifdef __cplusplus
7094 }
7095 #endif
7096
7097 #endif /* __STM32F4xx_LL_RCC_H */
7098
7099 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7100