| /aosp_15_r20/external/mesa3d/src/gallium/drivers/r600/sfn/ |
| H A D | sfn_instr_tex.h | 65 struct Inputs { struct
67 const nir_variable *sampler_deref;
68 const nir_variable *texture_deref;
69 RegisterVec4 coord;
70 PVirtualValue bias;
71 PVirtualValue comperator;
72 PVirtualValue lod;
73 RegisterVec4 ddx;
74 RegisterVec4 ddy;
75 nir_src *offset;
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 1081 bool MachineConstEvaluator::getCell(const RegisterSubReg &R, const CellMap &Inputs, in getCell()
1108 const RegisterSubReg &R2, const CellMap &Inputs, bool &Result) { in evaluateCMPrr()
1147 const APInt &A2, const CellMap &Inputs, bool &Result) { in evaluateCMPri()
1174 uint64_t Props2, const CellMap &Inputs, bool &Result) { in evaluateCMPrp()
1367 const CellMap &Inputs, LatticeCell &Result) { in evaluateCOPY()
1372 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateANDrr()
1403 const APInt &A2, const CellMap &Inputs, LatticeCell &Result) { in evaluateANDri()
1439 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateORrr()
1470 const APInt &A2, const CellMap &Inputs, LatticeCell &Result) { in evaluateORri()
1506 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateXORrr()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 1080 bool MachineConstEvaluator::getCell(const RegisterSubReg &R, const CellMap &Inputs, in getCell()
1107 const RegisterSubReg &R2, const CellMap &Inputs, bool &Result) { in evaluateCMPrr()
1146 const APInt &A2, const CellMap &Inputs, bool &Result) { in evaluateCMPri()
1173 uint64_t Props2, const CellMap &Inputs, bool &Result) { in evaluateCMPrp()
1366 const CellMap &Inputs, LatticeCell &Result) { in evaluateCOPY()
1371 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateANDrr()
1402 const APInt &A2, const CellMap &Inputs, LatticeCell &Result) { in evaluateANDri()
1438 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateORrr()
1469 const APInt &A2, const CellMap &Inputs, LatticeCell &Result) { in evaluateORri()
1505 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateXORrr()
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| /aosp_15_r20/external/clang/lib/Driver/ |
| H A D | Tools.cpp | 235 static void AddLinkerInputs(const ToolChain &TC, const InputInfoList &Inputs, in AddLinkerInputs()
303 const InputInfoList &Inputs, in AddPreprocessingOptions()
416 Driver::InputList Inputs; in AddPreprocessingOptions() local
3779 const InputInfo &Output, const InputInfoList &Inputs, in ConstructJob()
6427 const InputInfo &Output, const InputInfoList &Inputs, in ConstructJob()
6610 const InputInfoList &Inputs, const ArgList &Args, in ConstructJob()
6776 const InputInfoList &Inputs, in ConstructJob()
6850 const InputInfo &Output, const InputInfoList &Inputs, in constructHexagonLinkArgs()
7019 const InputInfoList &Inputs, in ConstructJob()
7036 const InputInfoList &Inputs, in ConstructJob()
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| /aosp_15_r20/external/vixl/test/aarch32/ |
| H A D | test-simulator-cond-rd-rn-rm-ge-a32.cc | 149 struct Inputs { struct
150 uint32_t apsr;
151 uint32_t qbit;
152 uint32_t ge;
153 uint32_t rd;
154 uint32_t rn;
155 uint32_t rm;
|
| H A D | test-simulator-cond-rd-rn-rm-a32.cc | 195 struct Inputs { struct
196 uint32_t apsr;
197 uint32_t qbit;
198 uint32_t ge;
199 uint32_t rd;
200 uint32_t rn;
201 uint32_t rm;
|
| H A D | test-simulator-cond-rd-rn-rm-ge-t32.cc | 149 struct Inputs { struct
150 uint32_t apsr;
151 uint32_t qbit;
152 uint32_t ge;
153 uint32_t rd;
154 uint32_t rn;
155 uint32_t rm;
|
| H A D | test-simulator-cond-rd-rn-rm-sel-a32.cc | 137 struct Inputs { struct
138 uint32_t apsr;
139 uint32_t qbit;
140 uint32_t ge;
141 uint32_t rd;
142 uint32_t rn;
143 uint32_t rm;
|
| H A D | test-simulator-cond-rd-rn-rm-sel-t32.cc | 137 struct Inputs { struct
138 uint32_t apsr;
139 uint32_t qbit;
140 uint32_t ge;
141 uint32_t rd;
142 uint32_t rn;
143 uint32_t rm;
|
| H A D | test-simulator-cond-rd-rn-rm-q-t32.cc | 141 struct Inputs { struct
142 uint32_t apsr;
143 uint32_t qbit;
144 uint32_t ge;
145 uint32_t rd;
146 uint32_t rn;
147 uint32_t rm;
|
| H A D | test-simulator-cond-rd-rn-rm-t32.cc | 194 struct Inputs { struct
195 uint32_t apsr;
196 uint32_t qbit;
197 uint32_t ge;
198 uint32_t rd;
199 uint32_t rn;
200 uint32_t rm;
|
| H A D | test-simulator-cond-rd-rn-rm-q-a32.cc | 141 struct Inputs { struct
142 uint32_t apsr;
143 uint32_t qbit;
144 uint32_t ge;
145 uint32_t rd;
146 uint32_t rn;
147 uint32_t rm;
|
| H A D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 159 struct Inputs { struct
160 uint32_t apsr;
161 uint32_t rd;
162 uint32_t rn;
163 uint32_t rm;
164 uint32_t rs;
|
| H A D | test-simulator-cond-dt-drt-drd-drn-drm-float-f64-a32.cc | 139 struct Inputs { struct
140 uint32_t fpscr;
141 uint64_t rd;
142 uint64_t rn;
143 uint64_t rm;
|
| H A D | test-simulator-cond-dt-drt-drd-drn-drm-float-f64-t32.cc | 139 struct Inputs { struct
140 uint32_t fpscr;
141 uint64_t rd;
142 uint64_t rn;
143 uint64_t rm;
|
| H A D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 171 struct Inputs { struct
172 uint32_t apsr;
173 uint32_t rd;
174 uint32_t rn;
175 uint32_t rm;
|
| H A D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 171 struct Inputs { struct
172 uint32_t apsr;
173 uint32_t rd;
174 uint32_t rn;
175 uint32_t rm;
|
| H A D | test-simulator-cond-rdlow-rnlow-rmlow-t32.cc | 139 struct Inputs { struct
140 uint32_t apsr;
141 uint32_t rd;
142 uint32_t rn;
143 uint32_t rm;
|
| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 159 struct Inputs { struct
160 uint32_t apsr;
161 uint32_t rd;
162 uint32_t rn;
163 uint32_t rm;
|
| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 159 struct Inputs { struct
160 uint32_t apsr;
161 uint32_t rd;
162 uint32_t rn;
163 uint32_t rm;
|
| H A D | test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc | 145 struct Inputs { struct
146 uint32_t apsr;
147 uint32_t rd;
148 uint32_t rn;
149 uint32_t rm;
|
| H A D | test-simulator-cond-rd-operand-rn-shift-rs-t32.cc | 140 struct Inputs { struct
141 uint32_t apsr;
142 uint32_t rd;
143 uint32_t rn;
144 uint32_t rs;
|
| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 159 struct Inputs { struct
160 uint32_t apsr;
161 uint32_t rd;
162 uint32_t rn;
163 uint32_t rm;
|
| /aosp_15_r20/external/llvm-libc/test/src/math/ |
| H A D | fma_test.cpp | 13 struct Inputs { struct
20 constexpr Inputs INPUTS[N] = { in test_more_values() argument
|
| /aosp_15_r20/external/swiftshader/src/Device/ |
| H A D | Context.hpp | 132 struct Inputs struct
139 inline const DescriptorSet::Array &getDescriptorSetObjects() const { return descriptorSetObjects; } in getDescriptorSetObjects()
140 inline const DescriptorSet::Bindings &getDescriptorSets() const { return descriptorSets; } in getDescriptorSets()
141 …riptorSet::DynamicOffsets &getDescriptorDynamicOffsets() const { return descriptorDynamicOffsets; } in getDescriptorDynamicOffsets()
142 inline const sw::Stream &getStream(uint32_t i) const { return stream[i]; } in getStream()
151 InputsDynamicStateFlags dynamicStateFlags = {};
152 VertexInputBinding vertexInputBindings[MAX_VERTEX_INPUT_BINDINGS] = {};
153 DescriptorSet::Array descriptorSetObjects = {};
154 DescriptorSet::Bindings descriptorSets = {};
155 DescriptorSet::DynamicOffsets descriptorDynamicOffsets = {};
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