1 /* 2 * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #if TRUSTED_BOARD_BOOT 12 #include MBEDTLS_CONFIG_FILE 13 #endif 14 #include <plat/arm/board/common/board_css_def.h> 15 #include <plat/arm/board/common/v2m_def.h> 16 #include <plat/arm/common/arm_def.h> 17 #include <plat/arm/css/common/css_def.h> 18 #include <plat/arm/soc/common/soc_css_def.h> 19 #include <plat/common/common_def.h> 20 21 #include "../juno_def.h" 22 #ifdef JUNO_ETHOSN_TZMP1 23 #include "../juno_ethosn_tzmp1_def.h" 24 #endif 25 26 /* Required platform porting definitions */ 27 /* Juno supports system power domain */ 28 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 29 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 30 JUNO_CLUSTER_COUNT + \ 31 PLATFORM_CORE_COUNT) 32 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 33 JUNO_CLUSTER1_CORE_COUNT) 34 35 /* 36 * Other platform porting definitions are provided by included headers 37 */ 38 39 /* Define memory configuration for device tree files. */ 40 #define PLAT_ARM_HW_CONFIG_SIZE U(0x8000) 41 42 /* 43 * Required ARM standard platform porting definitions 44 */ 45 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 46 47 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 48 49 /* Use the bypass address */ 50 #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ 51 BL1_ROM_BYPASS_OFFSET) 52 53 #define NSRAM_BASE UL(0x2e000000) 54 #define NSRAM_SIZE UL(0x00008000) /* 32KB */ 55 56 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 57 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 58 59 /* Range of kernel DTB load address */ 60 #define JUNO_DTB_DRAM_MAP_START ULL(0x82000000) 61 #define JUNO_DTB_DRAM_MAP_SIZE ULL(0x00008000) /* 32KB */ 62 63 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 64 JUNO_DTB_DRAM_MAP_START, \ 65 JUNO_DTB_DRAM_MAP_SIZE, \ 66 MT_MEMORY | MT_RO | MT_NS) 67 68 #ifdef JUNO_ETHOSN_TZMP1 69 #define JUNO_ETHOSN_PROT_FW_RO MAP_REGION_FLAT( \ 70 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE, \ 71 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE, \ 72 MT_RO_DATA | MT_SECURE) 73 74 #define JUNO_ETHOSN_PROT_FW_RW MAP_REGION_FLAT( \ 75 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE, \ 76 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE, \ 77 MT_MEMORY | MT_RW | MT_SECURE) 78 #endif 79 80 /* virtual address used by dynamic mem_protect for chunk_base */ 81 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 82 83 /* 84 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 85 */ 86 87 #if USE_ROMLIB 88 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 89 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 90 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000) 91 #else 92 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 93 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 94 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0) 95 #endif 96 97 /* 98 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 99 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 100 * flash 101 */ 102 103 #if TRUSTED_BOARD_BOOT 104 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) 105 #else 106 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) 107 #endif /* TRUSTED_BOARD_BOOT */ 108 109 /* 110 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 111 * plat_arm_mmap array defined for each BL stage. 112 */ 113 #ifdef IMAGE_BL1 114 # define PLAT_ARM_MMAP_ENTRIES 7 115 # define MAX_XLAT_TABLES 4 116 #endif 117 118 #ifdef IMAGE_BL2 119 #ifdef SPD_opteed 120 # define PLAT_ARM_MMAP_ENTRIES 13 121 # define MAX_XLAT_TABLES 5 122 #else 123 # define PLAT_ARM_MMAP_ENTRIES 11 124 # define MAX_XLAT_TABLES 5 125 #endif 126 #endif 127 128 #ifdef IMAGE_BL2U 129 # define PLAT_ARM_MMAP_ENTRIES 5 130 # define MAX_XLAT_TABLES 3 131 #endif 132 133 #ifdef IMAGE_BL31 134 # define PLAT_ARM_MMAP_ENTRIES 8 135 # define MAX_XLAT_TABLES 6 136 #endif 137 138 #ifdef IMAGE_BL32 139 # define PLAT_ARM_MMAP_ENTRIES 6 140 # define MAX_XLAT_TABLES 4 141 #endif 142 143 /* 144 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 145 * plus a little space for growth. 146 */ 147 #if TRUSTED_BOARD_BOOT 148 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 149 #else 150 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) 151 #endif 152 153 /* 154 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 155 * little space for growth. 156 */ 157 #if TRUSTED_BOARD_BOOT 158 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 159 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 160 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 161 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 162 #else 163 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 164 #endif 165 #else 166 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 167 #endif 168 169 /* 170 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 171 * calculated using the current BL31 PROGBITS debug size plus the sizes of 172 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 173 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 174 */ 175 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) 176 177 #if JUNO_AARCH32_EL3_RUNTIME 178 /* 179 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 180 * calculated using the current BL32 PROGBITS debug size plus the sizes of 181 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 182 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 183 */ 184 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3D000) 185 #endif 186 187 /* 188 * Size of cacheable stacks 189 */ 190 #if defined(IMAGE_BL1) 191 # if TRUSTED_BOARD_BOOT 192 # define PLATFORM_STACK_SIZE UL(0x1000) 193 # else 194 # define PLATFORM_STACK_SIZE UL(0x440) 195 # endif 196 #elif defined(IMAGE_BL2) 197 # if TRUSTED_BOARD_BOOT 198 # define PLATFORM_STACK_SIZE UL(0x1000) 199 # else 200 # define PLATFORM_STACK_SIZE UL(0x400) 201 # endif 202 #elif defined(IMAGE_BL2U) 203 # define PLATFORM_STACK_SIZE UL(0x400) 204 #elif defined(IMAGE_BL31) 205 # if PLAT_XLAT_TABLES_DYNAMIC 206 # define PLATFORM_STACK_SIZE UL(0x800) 207 # else 208 # define PLATFORM_STACK_SIZE UL(0x400) 209 # endif 210 #elif defined(IMAGE_BL32) 211 # define PLATFORM_STACK_SIZE UL(0x440) 212 #endif 213 214 /* CCI related constants */ 215 #define PLAT_ARM_CCI_BASE UL(0x2c090000) 216 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 217 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 218 219 /* System timer related constants */ 220 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 221 222 /* TZC related constants */ 223 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 224 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 225 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 226 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 227 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 228 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 229 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 230 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 231 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 232 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 233 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 234 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 235 236 /* TZC related constants */ 237 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 238 239 /* 240 * Required ARM CSS based platform porting definitions 241 */ 242 243 /* GIC related constants (no GICR in GIC-400) */ 244 #define PLAT_ARM_GICD_BASE UL(0x2c010000) 245 #define PLAT_ARM_GICC_BASE UL(0x2c02f000) 246 #define PLAT_ARM_GICH_BASE UL(0x2c04f000) 247 #define PLAT_ARM_GICV_BASE UL(0x2c06f000) 248 249 /* MHU related constants */ 250 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) 251 252 #if CSS_USE_SCMI_SDS_DRIVER 253 /* Index of SDS region used in the communication between AP and SCP */ 254 #define SDS_SCP_AP_REGION_ID U(0) 255 #else 256 /* 257 * Base address of the first memory region used for communication between AP 258 * and SCP. Used by the BOM and SCPI protocols. 259 * 260 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 261 * means the SCP/AP configuration data gets overwritten when the AP initiates 262 * communication with the SCP. The configuration data is expected to be a 263 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 264 * which CPU is the primary, according to the shift and mask definitions below. 265 */ 266 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) 267 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 268 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 269 #endif /* CSS_USE_SCMI_SDS_DRIVER */ 270 271 /* 272 * SCP_BL2 uses up whatever remaining space is available as it is loaded before 273 * anything else in this memory region and is handed over to the SCP before 274 * BL31 is loaded over the top. 275 */ 276 #define PLAT_CSS_MAX_SCP_BL2_SIZE \ 277 ((SCP_BL2_LIMIT - ARM_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK) 278 279 #define PLAT_CSS_MAX_SCP_BL2U_SIZE PLAT_CSS_MAX_SCP_BL2_SIZE 280 281 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 282 CSS_G1S_IRQ_PROPS(grp), \ 283 ARM_G1S_IRQ_PROPS(grp), \ 284 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 285 (grp), GIC_INTR_CFG_LEVEL), \ 286 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 287 (grp), GIC_INTR_CFG_LEVEL), \ 288 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 289 (grp), GIC_INTR_CFG_LEVEL), \ 290 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 291 (grp), GIC_INTR_CFG_LEVEL), \ 292 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 293 (grp), GIC_INTR_CFG_LEVEL), \ 294 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 295 (grp), GIC_INTR_CFG_LEVEL), \ 296 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 297 (grp), GIC_INTR_CFG_LEVEL), \ 298 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 299 (grp), GIC_INTR_CFG_LEVEL) 300 301 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 302 303 /* 304 * Required ARM CSS SoC based platform porting definitions 305 */ 306 307 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 308 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) 309 310 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 311 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 312 313 /* System power domain level */ 314 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 315 316 /* 317 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 318 */ 319 #ifdef __aarch64__ 320 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 321 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 322 #else 323 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 324 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 325 #endif 326 327 /* Number of SCMI channels on the platform */ 328 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 329 330 /* Protected NSAIDs and memory regions for the Arm(R) Ethos(TM)-N NPU driver */ 331 #ifdef JUNO_ETHOSN_TZMP1 332 #define ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT 333 #define ETHOSN_NPU_PROT_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT 334 #define ETHOSN_NPU_PROT_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT 335 336 #define ETHOSN_NPU_NS_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS 337 #define ETHOSN_NPU_NS_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS 338 339 #define ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE 340 #define ETHOSN_NPU_FW_IMAGE_LIMIT \ 341 (JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE + JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE) 342 #endif 343 344 #endif /* PLATFORM_DEF_H */ 345