1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 /* $NoKeywords:$ */ 4 /** 5 * @file 6 * 7 * AMD CPU Late Init API functions Prototypes. 8 * 9 * Contains code for doing any late CPU initialization 10 * 11 * @xrefitem bom "File Content Label" "Release Content" 12 * @e project: AGESA 13 * @e sub-project: CPU 14 * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $ 15 * 16 */ 17 /***************************************************************************** 18 * 19 * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc. 20 * All rights reserved. 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions are met: 24 * * Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * * Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in the 28 * documentation and/or other materials provided with the distribution. 29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of 30 * its contributors may be used to endorse or promote products derived 31 * from this software without specific prior written permission. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY 37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 * 44 ***************************************************************************/ 45 46 #ifndef _CPU_LATE_INIT_H_ 47 #define _CPU_LATE_INIT_H_ 48 49 #include "Filecode.h" 50 51 // Forward declaration needed for multi-structure mutual references. 52 AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE); 53 /*---------------------------------------------------------------------------------------- 54 * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) 55 *---------------------------------------------------------------------------------------- 56 */ 57 58 /*---------------------------------------------------------------------------------------- 59 * D E F I N I T I O N S A N D M A C R O S 60 *---------------------------------------------------------------------------------------- 61 */ 62 63 //---------------------------------------------------------------------------- 64 // DMI DEFINITIONS AND MACROS 65 // 66 //---------------------------------------------------------------------------- 67 #define AP_LATE_TASK_GET_TYPE4_TYPE7 (PROC_CPU_FEATURE_CPUDMI_FILECODE) 68 // SMBIOS constant definition 69 #define CENTRAL_PROCESSOR 0x03 70 #define EXTERNAL_CLOCK_DFLT 200 71 #define EXTERNAL_CLOCK_100MHZ 100 72 #define P_FAMILY_UNKNOWN 0x02 73 #define P_ENGINEERING_SAMPLE 0x00 74 #define P_CHARACTERISTICS 0x4 75 #define CACHE_CFG_L1 0x180 76 #define CACHE_CFG_L2 0x181 77 #define CACHE_CFG_L3 0x182 78 #define SRAM_TYPE 0x10 79 #define ERR_CORRECT_TYPE 0x06 80 #define CACHE_TYPE 0x05 81 #define DMI_ASSOCIATIVE_OTHER 0x01 82 #define DMI_ASSOCIATIVE_UNKNOWN 0x02 83 #define DMI_ASSOCIATIVE_DIRECT_MAPPED 0x03 84 #define DMI_ASSOCIATIVE_2_WAY 0x04 85 #define DMI_ASSOCIATIVE_4_WAY 0x05 86 #define DMI_ASSOCIATIVE_FULLY 0x06 87 #define DMI_ASSOCIATIVE_8_WAY 0x07 88 #define DMI_ASSOCIATIVE_16_WAY 0x08 89 #define DMI_ASSOCIATIVE_12_WAY 0x09 90 #define DMI_ASSOCIATIVE_24_WAY 0x0A 91 #define DMI_ASSOCIATIVE_32_WAY 0x0B 92 #define DMI_ASSOCIATIVE_48_WAY 0x0C 93 #define DMI_ASSOCIATIVE_64_WAY 0x0D 94 #define DMI_ASSOCIATIVE_20_WAY 0x0E 95 #define SOCKET_POPULATED 0x40 96 #define CPU_STATUS_UNKNOWN 0x00 97 #define CPU_STATUS_ENABLED 0x01 98 99 // Processor Upgrade Definition 100 #define P_UPGRADE_UNKNOWN 0x02 101 #define P_UPGRADE_NONE 0x06 102 #define P_UPGRADE_S1GX 0x16 103 #define P_UPGRADE_AM2 0x17 104 #define P_UPGRADE_F1207 0x18 105 #define P_UPGRADE_G34 0x1A 106 #define P_UPGRADE_AM3 0x1B 107 #define P_UPGRADE_C32 0x1C 108 #define P_UPGRADE_FS1 0x27 109 #define P_UPGRADE_FM1 0x29 110 #define P_UPGRADE_FM2 0x2A 111 112 //---------------------------------------------------------------------------- 113 // SRAT DEFINITIONS AND MACROS 114 // 115 //---------------------------------------------------------------------------- 116 #define NorthbridgeCapabilities 0xE8 117 #define DRAMBase0 0x40 118 #define MMIOBase0 0x80 119 #define TOP_MEM 0xC001001Aul 120 #define LOW_NODE_DEVICEID 24 121 #define LOW_APICID 0 122 123 124 // Miscellaneous AMD related values 125 #define MAX_NUMBER_NODES 8 126 127 // Flags 128 #define ENABLED 1 // Bit 0 129 #define DISABLED 0 // Bit 0 130 #define HOTPLUGGABLE 2 // Bit 1 131 132 // Affinity Entry Structures 133 #define AE_APIC 0 134 #define AE_MEMORY 1 135 136 137 // Memory Types 138 #define TYPE_MEMORY 1 139 #define TYPE_RESERVED 2 140 #define TYPE_ACPI 3 141 #define TYPE_NVS 4 142 143 //---------------------------------------------------------------------------- 144 // SLIT DEFINITIONS AND MACROS 145 // 146 //---------------------------------------------------------------------------- 147 #define AMD_ACPI_SLIT_SOCKET_NUM_LENGTH 8 148 149 //---------------------------------------------------------------------------- 150 // CDIT DEFINITIONS AND MACROS 151 // 152 //---------------------------------------------------------------------------- 153 #define AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH 4 // Num domains is a 4-bytes unsigned integer 154 155 156 //---------------------------------------------------------------------------- 157 // P-STATE DEFINITIONS AND MACROS 158 // 159 //---------------------------------------------------------------------------- 160 //------------------------------------- 161 // ERROR Codes 162 //------------------------------------- 163 #define NO_ERROR 0x0 164 #define USER_DISABLE_ERROR 0x01 // User disabled SSDT generation 165 #define CORES_MISSMATCH_PSS_ERROR 0x02 // No PSS match 166 #define PNOW_SUPPORT_ERROR 0x04 // One of the Cores do not support PNOW! 167 #define PWR_FREQ_MATCH_ERROR 0x08 // FREQ and PWR mismatch 168 #define NO_PSS_SIZE_ERROR 0x10 // Error in PSS Size 169 #define INVALID_PSTATE_ERROR 0x20 // Invalid Max or only 1 P-State available 170 #define NO_PSS_ENTRY 0x0FFFFul 171 #define INVALID_FREQ 0x0FFFFFFFFul 172 173 //------------------------- 174 // Default definitions 175 // AMD BKDG default values 176 //------------------------- 177 #define DEFAULT_ISOCH_RELIEF_TIME IRT_80uS 178 #define DEFAULT_RAMP_VOLTAGE_OFFSET RVO_50mV 179 #define DEFAULT_MAX_VOLTAGE_STEP MVS_25mV 180 #define DEFAULT_PERF_PRESENT_CAP 0 // default for Desktop 181 #define DEFAULT_VOLTAGE_STABLE_TIME (100 / 20) // 100uS 182 #define DEFAULT_PLL_LOCK_TIME 2 // 2uS 183 #define DEFAULT_TRANSITION_LATENCY 100 // 100uS 184 #define DEFAULT_BUS_MASTER_LATENCY 9 // 9uS 185 #define DEFAULT_CPU_SCOPE_NUMBER "0UPC" 186 187 // Defines for Common ACPI 188 // ----------------------------- 189 #define SCOPE_OPCODE 0x10 190 #define NAME_OPCODE 0x08 191 #define METHOD_OPCODE 0x14 192 #define PACKAGE_OPCODE 0x12 193 #define BUFFER_OPCODE 0x11 194 #define BYTE_PREFIX_OPCODE 0x0A 195 #define WORD_PREFIX_OPCODE 0x0B 196 #define DWORD_PREFIX_OPCODE 0x0C 197 #define RETURN_OPCODE 0xA4 198 #define ACPI_BUFFER 0x080A0B11ul 199 200 // Generic Register Descriptor (GDR) Fields 201 #define GDR_ASI_SYSTEM_IO 0x01 // Address Space ID 202 #define GDR_ASZ_BYTE_ACCESS 0x01 // Address Size 203 204 // Defines for ACPI Scope Table 205 // ---------------------------- 206 #define SCOPE_LENGTH (SCOPE_STRUCT_SIZE + \ 207 PCT_STRUCT_SIZE + \ 208 PSS_HEADER_STRUCT_SIZE + \ 209 PSS_BODY_STRUCT_SIZE + \ 210 PPC_HEADER_BODY_STRUCT_SIZE) 211 #define SCOPE_VALUE1 0x5C 212 #define SCOPE_VALUE2 0x2E 213 #define SCOPE_NAME__ '_' 214 #define SCOPE_NAME_P 'P' 215 #define SCOPE_NAME_R 'R' 216 #define SCOPE_NAME_S 'S' 217 #define SCOPE_NAME_B 'B' 218 #define SCOPE_NAME_C 'C' 219 #define SCOPE_NAME_U 'U' 220 #define SCOPE_NAME_0 '0' 221 #define SCOPE_NAME_1 '1' 222 #define SCOPE_NAME_2 '2' 223 #define SCOPE_NAME_3 '3' 224 #define SCOPE_NAME_A 'A' 225 226 #ifdef OEM_SCOPE_NAME 227 #if (OEM_SCOPE_NAME > 'Z') || (OEM_SCOPE_NAME < 'A') 228 #error "OEM_SCOPE_NAME: it should be only one char long AND a valid letter (A~Z)" 229 #endif 230 #define SCOPE_NAME_VALUE OEM_SCOPE_NAME 231 #else 232 #define SCOPE_NAME_VALUE SCOPE_NAME_C 233 #endif // OEM_SCOPE_NAME 234 235 #ifdef OEM_SCOPE_NAME1 236 #if (!(((OEM_SCOPE_NAME1 >= 'A') && (OEM_SCOPE_NAME1 <= 'Z')) || \ 237 ((OEM_SCOPE_NAME1 >= '0') && (OEM_SCOPE_NAME1 <= '9')) || \ 238 (OEM_SCOPE_NAME1 == '_'))) 239 #error "OEM_SCOPE_NAME1: it should be only one char long AND a valid letter (0~9, A~F)" 240 #endif 241 #define SCOPE_NAME_VALUE1 OEM_SCOPE_NAME1 242 #else 243 #define SCOPE_NAME_VALUE1 SCOPE_NAME_0 244 #endif // OEM_SCOPE_NAME 245 246 // Defines for PCT Control and Status Table 247 // ---------------------------------------- 248 #define PCT_NAME__ '_' 249 #define PCT_NAME_P 'P' 250 #define PCT_NAME_C 'C' 251 #define PCT_NAME_T 'T' 252 #define PCT_VALUE1 0x11022C12ul 253 #define PCT_VALUE2 0x0A14 254 #define PCT_VALUE3 0x11 255 #define GENERIC_REG_DESCRIPTION 0x82 256 #define PCT_LENGTH 0x0C 257 #define PCT_ADDRESS_SPACE_ID 0x7F 258 #define PCT_REGISTER_BIT_WIDTH 0x40 259 #define PCT_REGISTER_BIT_OFFSET 0x00 260 #define PCT_RESERVED 0x00 261 #define PCT_CONTROL_REG_LO 0xC0010062ul 262 #define PCT_CONTROL_REG_HI 0x00 263 #define PCT_VALUE4 0x14110079ul 264 #define PCT_VALUE5 0x110A 265 #define PCT_STATUS_REG_LO 0x00 266 #define PCT_STATUS_REG_HI 0x00 267 #define PCT_VALUE6 0x0079 268 269 270 // Defines for PSS Header Table 271 // ---------------------------- 272 #define PSS_NAME__ '_' 273 #define PSS_NAME_X 'X' 274 #define PSS_NAME_P 'P' 275 #define PSS_NAME_S 'S' 276 #define PSS_LENGTH (sizeof pssBodyStruct + 3) 277 #define NUM_OF_ITEMS_IN_PSS 0x00 278 279 280 // Defines for PSS Header Table 281 // ---------------------------- 282 #define PSS_PKG_LENGTH 0x20 // PSS_BODY_STRUCT_SIZE - 1 283 #define PSS_NUM_OF_ELEMENTS 0x06 284 #define PSS_FREQUENCY 0x00 285 #define PSS_POWER 0x00 286 #define PSS_TRANSITION_LATENCY DEFAULT_TRANSITION_LATENCY 287 #define PSS_BUS_MASTER_LATENCY DEFAULT_BUS_MASTER_LATENCY 288 #define PSS_CONTROL ((DEFAULT_ISOCH_RELIEF_TIME << 30) + \ 289 (DEFAULT_RAMP_VOLTAGE_OFFSET << 28) + \ 290 (DEFAULT_EXT_TYPE << 27) + \ 291 (DEFAULT_PLL_LOCK_TIME << 20) + \ 292 (DEFAULT_MAX_VOLTAGE_STEP << 18) + \ 293 (DEFAULT_VOLTAGE_STABLE_TIME << 11) + \ 294 (PSS_VID << 6) + PSS_FID) 295 #define PSS_STATUS (DEFAULT_EXTENDED_TYPE << 11) + (PSS_VID << 6) + (PSS_FID) 296 297 // Defines for XPSS Header Table 298 // ---------------------------- 299 #define XPSS_PKG_LENGTH 0x47 // XPSS_BODY_STRUCT_SIZE - 1 300 #define XPSS_NUM_OF_ELEMENTS 0x08 301 #define XPSS_ACPI_BUFFER 0x080A0B11ul 302 303 304 // Defines for PPC Header Table 305 // ---------------------------- 306 #define PPC_NAME__ '_' 307 #define PPC_NAME_P 'P' 308 #define PPC_NAME_C 'C' 309 #define PPC_NAME_V 'V' 310 #define PPC_METHOD_FLAGS 0x00; 311 #define PPC_VALUE1 0x0A; 312 313 // Defines for PSD Header Table 314 // ---------------------------- 315 #define PSD_NAME__ '_' 316 #define PSD_NAME_P 'P' 317 #define PSD_NAME_S 'S' 318 #define PSD_NAME_D 'D' 319 #define PSD_HEADER_LENGTH (PSD_BODY_STRUCT_SIZE + 2) 320 #define PSD_VALUE1 0x01 321 322 323 // Defines for PSD Header Table 324 // ---------------------------- 325 #define PSD_PKG_LENGTH (PSD_BODY_STRUCT_SIZE - 1) 326 #define NUM_OF_ENTRIES 0x05 327 #define PSD_NUM_OF_ENTRIES 0x05 328 #define PSD_REVISION 0x00 329 #define PSD_DEPENDENCY_DOMAIN 0x00 330 #define PSD_COORDINATION_TYPE_HW_ALL 0xFE 331 #define PSD_COORDINATION_TYPE_SW_ANY 0xFD 332 #define PSD_COORDINATION_TYPE_SW_ALL 0xFC 333 #define PSD_NUM_OF_PROCESSORS 0x01 334 #define PSD_TWO_CORES_PER_COMPUTE_UNIT 0x02 335 #define PSD_THREE_CORES_PER_COMPUTE_UNIT 0x03 336 #define PSD_FOUR_CORES_PER_COMPUTE_UNIT 0x04 337 338 339 #define CUSTOM_PSTATE_FLAG 0x55 340 #define PSTATE_FLAG_1 0x55 341 #define TARGET_PSTATE_FLAG 0xAA 342 #define PSTATE_FLAG_2 0xAA 343 344 /*---------------------------------------------------------------------------------------- 345 * T Y P E D E F S, S T R U C T U R E S, E N U M S 346 *---------------------------------------------------------------------------------------- 347 */ 348 //---------------------------------------------------------------------------- 349 // ACPI P-States AML TYPEDEFS, STRUCTURES, ENUMS 350 // 351 //---------------------------------------------------------------------------- 352 353 //-------------------------------------------- 354 // AML code definition 355 // (Scope) 356 //--------------------------------------------- 357 /// SCOPE 358 typedef struct _SCOPE { 359 UINT8 ScopeOpcode; ///< Opcode 360 UINT16 ScopeLength; ///< Scope Length 361 UINT8 ScopeValue1; ///< Value1 362 UINT8 ScopeValue2; ///< Value2 363 UINT8 ScopeNamePt1a__; ///< Name Pointer 364 UINT8 ScopeNamePt1a_P; ///< Name Pointer 365 UINT8 ScopeNamePt1a_R; ///< Name Pointer 366 UINT8 ScopeNamePt1b__; ///< Name Pointer 367 UINT8 ScopeNamePt2a_C; ///< Name Pointer 368 UINT8 ScopeNamePt2a_P; ///< Name Pointer 369 UINT8 ScopeNamePt2a_U; ///< Name Pointer 370 UINT8 ScopeNamePt2a_0; ///< Name Pointer 371 } SCOPE; 372 #define SCOPE_STRUCT_SIZE 13 // 13 Bytes 373 374 //-------------------------------------------- 375 // AML code definition 376 // (PCT Header and Body) 377 //--------------------------------------------- 378 379 ///Performance Control Header 380 typedef struct _PCT_HEADER_BODY { 381 UINT8 NameOpcode; ///< Opcode 382 UINT8 PctName_a__; ///< String "_" 383 UINT8 PctName_a_P; ///< String "P" 384 UINT8 PctName_a_C; ///< String "C" 385 UINT8 PctName_a_T; ///< String "T" 386 UINT32 Value1; ///< Value1 387 UINT16 Value2; ///< Value2 388 UINT8 Value3; ///< Value3 389 UINT8 GenericRegDescription1; ///< Generic Reg Description 390 UINT16 Length1; ///< Length1 391 UINT8 AddressSpaceId1; ///< PCT Address Space ID 392 UINT8 RegisterBitWidth1; ///< PCT Register Bit Width 393 UINT8 RegisterBitOffset1; ///< PCT Register Bit Offset 394 UINT8 Reserved1; ///< Reserved 395 UINT32 ControlRegAddressLo; ///< Control Register Address Low 396 UINT32 ControlRegAddressHi; ///< Control Register Address High 397 UINT32 Value4; ///< Value4 398 UINT16 Value5; ///< Value 5 399 UINT8 GenericRegDescription2; ///< Generic Reg Description 400 UINT16 Length2; ///< Length2 401 UINT8 AddressSpaceId2; ///< PCT Address Space ID 402 UINT8 RegisterBitWidth2; ///< PCT Register Bit Width 403 UINT8 RegisterBitOffset2; ///< PCT Register Bit Offset 404 UINT8 Reserved2; ///< Reserved 405 UINT32 StatusRegAddressLo; ///< Control Register Address Low 406 UINT32 StatusRegAddressHi; ///< Control Register Address High 407 UINT16 Value6; ///< Values 408 } PCT_HEADER_BODY; 409 #define PCT_STRUCT_SIZE 50 // 50 Bytes 410 411 412 //-------------------------------------------- 413 // AML code definition 414 // (PSS Header) 415 //-------------------------------------------- 416 ///Performance Supported States Header 417 typedef struct _PSS_HEADER { 418 UINT8 NameOpcode; ///< Opcode 419 UINT8 PssName_a__; ///< String "_" 420 UINT8 PssName_a_P; ///< String "P" 421 UINT8 PssName_a_S; ///< String "S" 422 UINT8 PssName_b_S; ///< String "S" 423 UINT8 PkgOpcode; ///< Package Opcode 424 UINT16 PssLength; ///< PSS Length 425 UINT8 NumOfItemsInPss; ///< Number of Items in PSS 426 } PSS_HEADER; 427 #define PSS_HEADER_STRUCT_SIZE 9 // 9 Bytes 428 429 430 //-------------------------------------------- 431 // AML code definition 432 // (PSS Body) 433 //-------------------------------------------- 434 ///Performance Supported States Body 435 typedef struct _PSS_BODY { 436 UINT8 PkgOpcode; ///< Package Opcode 437 UINT8 PkgLength; ///< Package Length 438 UINT8 NumOfElements; ///< Number of Elements 439 UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 440 UINT32 Frequency; ///< Frequency 441 UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 442 UINT32 Power; ///< Power 443 UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 444 UINT32 TransitionLatency; ///< Transition Latency 445 UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4 446 UINT32 BusMasterLatency; ///< Bus Master Latency 447 UINT8 DwordPrefixOpcode5; ///< Prefix Opcode5 448 UINT32 Control; ///< Control 449 UINT8 DwordPrefixOpcode6; ///< Prefix Opcode6 450 UINT32 Status; ///< Status 451 } PSS_BODY; 452 #define PSS_BODY_STRUCT_SIZE 33 // 33 Bytes 453 454 455 /*-------------------------------------------- 456 * AML code definition 457 * (XPSS Header) 458 *-------------------------------------------- 459 */ 460 /// Extended PSS Header 461 typedef struct _XPSS_HEADER { 462 UINT8 NameOpcode; ///< 08h 463 UINT8 XpssName_a_X; ///< String "X" 464 UINT8 XpssName_a_P; ///< String "P" 465 UINT8 XpssName_a_S; ///< String "S" 466 UINT8 XpssName_b_S; ///< String "S" 467 UINT8 PkgOpcode; ///< 12h 468 UINT16 XpssLength; ///< XPSS Length 469 UINT8 NumOfItemsInXpss; ///< Number of Items in XPSS 470 } XPSS_HEADER; 471 #define XPSS_HEADER_STRUCT_SIZE 9 // 9 Bytes 472 473 /*-------------------------------------------- 474 * AML code definition 475 * (XPSS Body) 476 *-------------------------------------------- 477 */ 478 /// Extended PSS Body 479 typedef struct _XPSS_BODY { 480 UINT8 PkgOpcode; ///< 12h 481 UINT8 PkgLength; ///< Package Length 482 UINT8 XpssValueTbd; ///< XPSS Value 483 UINT8 NumOfElements; ///< Number of Elements 484 UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 485 UINT32 Frequency; ///< Frequency 486 UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 487 UINT32 Power; ///< Power 488 UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 489 UINT32 TransitionLatency; ///< Transition Latency 490 UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4 491 UINT32 BusMasterLatency; ///< Bus Master Latency 492 UINT32 ControlBuffer; ///< Control Buffer 493 UINT32 ControlLo; ///< Control Low 494 UINT32 ControlHi; ///< Control High 495 UINT32 StatusBuffer; ///< Status Buffer 496 UINT32 StatusLo; ///< Status Low 497 UINT32 StatusHi; ///< Status High 498 UINT32 ControlMaskBuffer; ///< Control Mask Buffer 499 UINT32 ControlMaskLo; ///< Control Mask Low 500 UINT32 ControlMaskHi; ///< Control Mask High 501 UINT32 StatusMaskBuffer; ///< Status Mask Buffer 502 UINT32 StatusMaskLo; ///< Status Mask Low 503 UINT32 StatusMaskHi; ///< Status Mask High 504 } XPSS_BODY; 505 #define XPSS_BODY_STRUCT_SIZE 72 // 72 Bytes 506 507 /*-------------------------------------------- 508 * AML code definition 509 * (PPC Header and Body) 510 *-------------------------------------------- 511 */ 512 /// Performance Present Capabilities Header 513 typedef struct _PPC_HEADER_BODY { 514 UINT8 NameOpcode; ///< Name Opcode 515 UINT8 PpcName_a_P; ///< String "P" 516 UINT8 PpcName_b_P; ///< String "P" 517 UINT8 PpcName_a_C; ///< String "C" 518 UINT8 PpcName_a_V; ///< String "V" 519 UINT8 Value1; ///< Value 520 UINT8 DefaultPerfPresentCap; ///< Default Perf Present Cap 521 UINT8 MethodOpcode; ///< Method Opcode 522 UINT8 PpcLength; ///< Method Length 523 UINT8 PpcName_a__; ///< String "_" 524 UINT8 PpcName_c_P; ///< String "P" 525 UINT8 PpcName_d_P; ///< String "P" 526 UINT8 PpcName_b_C; ///< String "C" 527 UINT8 MethodFlags; ///< Method Flags 528 UINT8 ReturnOpcode; ///< Return Opcoce 529 UINT8 PpcName_e_P; ///< String "P" 530 UINT8 PpcName_f_P; ///< String "P" 531 UINT8 PpcName_c_C; ///< String "C" 532 UINT8 PpcName_b_V; ///< String "V" 533 534 } PPC_HEADER_BODY; 535 #define PPC_HEADER_BODY_STRUCT_SIZE 19 // 19 Bytes 536 #define PPC_METHOD_LENGTH 11 // 11 Bytes 537 538 539 /*-------------------------------------------- 540 * AML code definition 541 * (PSD Header) 542 *-------------------------------------------- 543 */ 544 /// P-State Dependency Header 545 typedef struct _PSD_HEADER { 546 UINT8 NameOpcode; ///< Name Opcode 547 UINT8 PsdName_a__; ///< String "_" 548 UINT8 PsdName_a_P; ///< String "P" 549 UINT8 PsdName_a_S; ///< String "S" 550 UINT8 PsdName_a_D; ///< String "D" 551 UINT8 PkgOpcode; ///< Package Opcode 552 UINT8 PsdLength; ///< PSD Length 553 UINT8 Value1; ///< Value 554 } PSD_HEADER; 555 #define PSD_HEADER_STRUCT_SIZE 8 // 8 Bytes 556 557 /*-------------------------------------------- 558 * AML code definition 559 * (PSD Body) 560 *-------------------------------------------- 561 */ 562 /// P-State Dependency Body 563 typedef struct _PSD_BODY { 564 UINT8 PkgOpcode; ///< Package Opcode 565 UINT8 PkgLength; ///< Package Length 566 UINT8 NumOfEntries; ///< Number of Entries 567 UINT8 BytePrefixOpcode1; ///< Prefix Opcode1 in Byte 568 UINT8 PsdNumOfEntries; ///< PSD Number of Entries 569 UINT8 BytePrefixOpcode2; ///< Prefix Opcode2 in Byte 570 UINT8 PsdRevision; ///< PSD Revision 571 UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 in DWord 572 UINT32 DependencyDomain; ///< Dependency Domain 573 UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 in DWord 574 UINT32 CoordinationType; ///< (0xFC = SW_ALL, 0xFD = SW_ANY, 0xFE = HW_ALL) 575 UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 in DWord 576 UINT32 NumOfProcessors; ///< Number of Processors 577 } PSD_BODY; 578 #define PSD_BODY_STRUCT_SIZE 22 // 22 Bytes 579 580 //---------------------------------------------------------------------------- 581 // WHEA TYPEDEFS, STRUCTURES, ENUMS 582 // 583 //---------------------------------------------------------------------------- 584 585 /// HEST MCE TABLE 586 typedef struct _AMD_HEST_MCE_TABLE { 587 UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_MCE structure. 588 UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into 589 UINT32 GlobCapInitDataMSD; ///< the machine check global capability register(MCG_CAP). 590 UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will program into 591 UINT32 GlobCtrlInitDataMSD; ///< the machine check global control register(MCG_CTL). 592 UINT8 NumHWBanks; ///< The number of hardware error reporting banks. 593 UINT8 Rsvd[7]; ///< reserve 7 bytes as spec's required 594 } AMD_HEST_MCE_TABLE; 595 596 /// HEST CMC TABLE 597 typedef struct _AMD_HEST_CMC_TABLE { 598 UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_CMC structure. 599 UINT8 NumHWBanks; ///< The number of hardware error reporting banks. 600 UINT8 Rsvd[3]; ///< reserve 3 bytes as spec's required 601 } AMD_HEST_CMC_TABLE; 602 603 /// HEST BANK 604 typedef struct _AMD_HEST_BANK { 605 UINT8 BankNum; ///< Zero-based index identifies the machine check error bank. 606 UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check bank 607 ///< is to be cleared during system initialization. 608 UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register 609 UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be 610 ///< modified by the OS. If the bit for the associated parameter is 611 ///< set, the parameter is writable by the OS. 612 UINT32 CtrlRegMSRAddr; ///< Address of the hardware bank's control MSR. Ignored if zero. 613 614 UINT32 CtrlInitDataLSD; ///< This is the value the OS will program into the machine check 615 UINT32 CtrlInitDataMSD; ///< bank's control register 616 UINT32 StatRegMSRAddr; ///< Address of the hardware bank's MCi_STAT MSR. Ignored if zero. 617 UINT32 AddrRegMSRAddr; ///< Address of the hardware bank's MCi_ADDR MSR. Ignored if zero. 618 UINT32 MiscRegMSRAddr; ///< Address of the hardware bank's MCi_MISC MSR. Ignored if zero. 619 } AMD_HEST_BANK; 620 621 /// Initial data of AMD_HEST_BANK 622 typedef struct _AMD_HEST_BANK_INIT_DATA { 623 UINT32 CtrlInitDataLSD; ///< Initial data of CtrlInitDataLSD 624 UINT32 CtrlInitDataMSD; ///< Initial data of CtrlInitDataMSD 625 UINT32 CtrlRegMSRAddr; ///< Initial data of CtrlRegMSRAddr 626 UINT32 StatRegMSRAddr; ///< Initial data of StatRegMSRAddr 627 UINT32 AddrRegMSRAddr; ///< Initial data of AddrRegMSRAddr 628 UINT32 MiscRegMSRAddr; ///< Initial data of MiscRegMSRAddr 629 } AMD_HEST_BANK_INIT_DATA; 630 631 /// MSR179 Global Machine Check Capabilities data struct 632 typedef struct _MSR_MCG_CAP_STRUCT { 633 UINT64 Count:8; ///< Indicates the number of 634 ///< error-reporting banks visible to each core 635 UINT64 McgCtlP:1; ///< 1=The machine check control registers 636 UINT64 Rsvd:55; ///< reserved 637 } MSR_MCG_CAP_STRUCT; 638 639 /// Initial data of WHEA 640 typedef struct _AMD_WHEA_INIT_DATA { 641 UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into the machine 642 UINT32 GlobCapInitDataMSD; ///< Check global capability register 643 UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will grogram into the machine 644 UINT32 GlobCtrlInitDataMSD; ///< Check global control register 645 UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check 646 ///< bank is to be cleared during system initialization 647 UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register 648 UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be 649 ///< modified by the OS. If the bit for the associated parameter is 650 ///< set, the parameter is writable by the OS. 651 UINT8 HestBankNum; ///< Number of HEST Bank 652 AMD_HEST_BANK_INIT_DATA *HestBankInitData; ///< Pointer to Initial data of HEST Bank 653 } AMD_WHEA_INIT_DATA; 654 655 //---------------------------------------------------------------------------- 656 // DMI TYPEDEFS, STRUCTURES, ENUMS 657 // 658 //---------------------------------------------------------------------------- 659 /// DMI brand information 660 typedef struct { 661 UINT16 String1:4; ///< String1 662 UINT16 String2:4; ///< String2 663 UINT16 Model:7; ///< Model 664 UINT16 Pg:1; ///< Page 665 } BRAND_ID; 666 667 /// DMI cache information 668 typedef struct { 669 UINT32 L1CacheSize; ///< L1 cache size 670 UINT8 L1CacheAssoc; ///< L1 cache associativity 671 UINT32 L2CacheSize; ///< L2 cache size 672 UINT8 L2CacheAssoc; ///< L2 cache associativity 673 UINT32 L3CacheSize; ///< L3 cache size 674 UINT8 L3CacheAssoc; ///< L3 cache associativity 675 } CPU_CACHE_INFO; 676 677 /// DMI processor information 678 typedef struct { 679 UINT8 ExtendedFamily; ///< Extended Family 680 UINT8 ExtendedModel; ///< Extended Model 681 UINT8 BaseFamily; ///< Base Family 682 UINT8 BaseModel; ///< Base Model 683 UINT8 Stepping; ///< Stepping 684 UINT8 PackageType; ///< PackageType 685 BRAND_ID BrandId; ///< BrandId which contains information about String1, String2, Model and Page 686 UINT8 TotalCoreNumber; ///< Number of total cores 687 UINT8 EnabledCoreNumber; ///< Number of enabled cores 688 UINT8 ProcUpgrade; ///< ProcUpdrade 689 CPU_CACHE_INFO CacheInfo; ///< CPU cache info 690 } CPU_TYPE_INFO; 691 692 /// A structure containing processor name string and 693 /// the value that should be provide to DMI type 4 processor family 694 typedef struct { 695 IN CONST CHAR8 *Stringstart; ///< The literal string 696 IN UINT8 T4ProcFamilySetting; ///< The value set to DMI type 4 processor family 697 } CPU_T4_PROC_FAMILY; 698 699 /// DMI ECC information 700 typedef struct { 701 BOOLEAN EccCapable; ///< ECC Capable 702 } CPU_GET_MEM_INFO; 703 704 /* Transfer vectors for DMI family specific routines */ 705 typedef VOID OPTION_DMI_GET_CPU_INFO ( 706 IN OUT CPU_TYPE_INFO *CpuInfoPtr, 707 IN AMD_CONFIG_PARAMS *StdHeader 708 ); 709 710 typedef VOID OPTION_DMI_GET_PROC_FAMILY ( 711 IN OUT UINT8 *T4ProcFamily, 712 IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, 713 IN CPU_TYPE_INFO *CpuInfo, 714 IN AMD_CONFIG_PARAMS *StdHeader 715 ); 716 717 typedef UINT8 OPTION_DMI_GET_VOLTAGE ( 718 IN AMD_CONFIG_PARAMS *StdHeader 719 ); 720 721 typedef UINT16 OPTION_DMI_GET_MAX_SPEED ( 722 IN AMD_CONFIG_PARAMS *StdHeader 723 ); 724 725 typedef UINT16 OPTION_DMI_GET_EXT_CLOCK ( 726 IN AMD_CONFIG_PARAMS *StdHeader 727 ); 728 729 typedef VOID OPTION_DMI_GET_MEM_INFO ( 730 IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, 731 IN AMD_CONFIG_PARAMS *StdHeader 732 ); 733 734 /// Brand table entry format 735 typedef struct { 736 UINT8 PackageType; ///< Package type 737 UINT8 PgOfBrandId; ///< Page 738 UINT8 NumberOfCores; ///< Number of cores 739 UINT8 String1ofBrandId; ///< String1 740 UINT8 ValueSetToDmiTable; ///< The value which will should be set to DMI table 741 } DMI_BRAND_ENTRY; 742 743 /// Family specific data table structure 744 struct _PROC_FAMILY_TABLE { 745 UINT64 ProcessorFamily; ///< processor 746 OPTION_DMI_GET_CPU_INFO *DmiGetCpuInfo; ///< transfer vectors 747 OPTION_DMI_GET_PROC_FAMILY *DmiGetT4ProcFamily; ///< Get DMI type 4 processor family information 748 OPTION_DMI_GET_VOLTAGE *DmiGetVoltage; ///< vector for reading voltage 749 OPTION_DMI_GET_MAX_SPEED *DmiGetMaxSpeed; ///< vector for reading speed 750 OPTION_DMI_GET_EXT_CLOCK *DmiGetExtClock; ///< vector for reading external clock speed 751 OPTION_DMI_GET_MEM_INFO *DmiGetMemInfo; ///< Get memory information 752 UINT8 LenBrandList; ///< size of brand table 753 CONST DMI_BRAND_ENTRY *DmiBrandList; ///< translate brand info to DMI identifier 754 }; 755 756 //---------------------------------------------------------------------------- 757 // SLIT TYPEDEFS, STRUCTURES, ENUMS 758 // 759 //---------------------------------------------------------------------------- 760 /// Format for SRAT Header 761 typedef struct { 762 UINT8 Sign[4]; ///< Signature 763 UINT32 TableLength; ///< Table Length 764 UINT8 Revision; ///< Revision 765 UINT8 Checksum; ///< Checksum 766 UINT8 OemId[6]; ///< OEM ID 767 UINT8 OemTableId[8]; ///< OEM Tabled ID 768 UINT32 OemRev; ///< OEM Revision 769 UINT8 CreatorId[4]; ///< Creator ID 770 UINT32 CreatorRev; ///< Creator Revision 771 } ACPI_TABLE_HEADER; 772 773 //---------------------------------------------------------------------------- 774 // SRAT TYPEDEFS, STRUCTURES, ENUMS 775 // 776 //---------------------------------------------------------------------------- 777 /// Format for SRAT Header 778 typedef struct _CPU_SRAT_HEADER { 779 UINT8 Sign[4]; ///< Signature 780 UINT32 TableLength; ///< Table Length 781 UINT8 Revision; ///< Revision 782 UINT8 Checksum; ///< Checksum 783 UINT8 OemId[6]; ///< OEM ID 784 UINT8 OemTableId[8]; ///< OEM Tabled ID 785 UINT32 OemRev; ///< OEM Revision 786 UINT8 CreatorId[4]; ///< Creator ID 787 UINT32 CreatorRev; ///< Creator Revision 788 UINT32 TableRev; ///< Table Revision 789 UINT8 Reserved[8]; ///< Reserved 790 } CPU_SRAT_HEADER; 791 792 793 /// Format for SRAT APIC Affinity Entry 794 typedef struct _CPU_SRAT_APIC_ENTRY { 795 UINT8 Type; ///< Type 796 UINT8 Length; ///< Length 797 UINT8 Domain; ///< Domain 798 UINT8 ApicId; ///< Apic ID 799 UINT32 Flags; ///< Flags 800 UINT8 LSApicEid; ///< Local SAPIC EID 801 UINT8 Reserved[7]; ///< Reserved 802 } CPU_SRAT_APIC_ENTRY; 803 804 805 /// Format for SRAT Memory Affinity Entry 806 typedef struct _CPU_SRAT_MEMORY_ENTRY { 807 UINT8 Type; ///< 0: Memory affinity = 1 808 UINT8 Length; ///< 1: Length = 40 bytes 809 UINT32 Domain; ///< 2: Proximity domain 810 UINT8 Reserved1[2]; ///< 6: Reserved 811 UINT32 BaseAddrLow; ///< 8: Low 32bits address base 812 UINT32 BaseAddrHigh; ///< 12: High 32bits address base 813 UINT32 LengthAddrLow; ///< 16: Low 32bits address limit 814 UINT32 LengthAddrHigh; ///< 20: High 32bits address limit 815 UINT8 Reserved2[4]; ///< 24: Memory Type 816 UINT32 Flags; ///< 28: Flags 817 UINT8 Reserved3[8]; ///< 32: Reserved 818 } CPU_SRAT_MEMORY_ENTRY; 819 820 //---------------------------------------------------------------------------- 821 // CRAT TYPEDEFS, STRUCTURES, ENUMS 822 // Component Resource Affinity Table 823 //---------------------------------------------------------------------------- 824 /// Format for CRAT Header 825 typedef struct { 826 UINT8 Sign[4]; ///< CRAT, Signature for the Component Resource Affinity Table. 827 UINT32 Length; ///< Length, in bytes, of the entire CRAT 828 UINT8 Revision; ///< 0 829 UINT8 Checksum; ///< Entire table must sum to zero. 830 UINT8 OemId[6]; ///< OEM ID 831 UINT8 OemTableId[8]; ///< OEM Tabled ID 832 UINT32 OemRev; ///< OEM Revision 833 UINT8 CreatorId[4]; ///< Creator ID 834 UINT32 CreatorRev; ///< Creator Revision 835 UINT32 TotalEntries; ///< total number[n] of entries in the CRAT 836 UINT16 NumDomains; ///< Number of HSA proximity domains 837 UINT8 Reserved[6]; ///< Reserved 838 } CRAT_HEADER; 839 840 /// Flags field of the CRAT HSA Processing Unit Affinity Structure 841 typedef struct { 842 UINT32 Enabled:1; ///< Enabled 843 UINT32 HotPluggable:1; ///< Hot Pluggable 844 UINT32 CpuPresent:1; ///< Cpu Present 845 UINT32 GpuPresent:1; ///< Gpu Present 846 UINT32 IommuPresent:1; ///< IOMMU Present 847 UINT32 :27; ///< Reserved 848 } CRAT_HSA_PROCESSING_UNIT_FLAG; 849 850 /// CRAT HSA Processing Unit Affinity Structure 851 typedef struct { 852 UINT8 Type; ///< 0 - CRAT HSA Processing Unit Structure 853 UINT8 Length; ///< 40 854 UINT16 Reserved; ///< Reserved 855 CRAT_HSA_PROCESSING_UNIT_FLAG Flags; ///< Flags - HSA Processing Unit Affinity Structure 856 UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to 857 UINT32 ProcessorIdLow; ///< Low value of the logical processor included in this HSA proximity domain 858 UINT16 NumCPUCores; ///< Indicates count of CCompute execution units present in this APU node. 859 UINT16 NumSIMDCores; ///< Indicates maximum count of HCompute SIMD cores present in this node. 860 UINT16 MaxWavesSIMD; ///< This identifies the max. number of launched waves per SIMD. 861 UINT16 IoCount; ///< Number of discoverable IO Interfaces connecting this node to other components. 862 UINT16 HSACapability; ///< Must be 0 863 UINT16 LDSSizeInKB; ///< Size of LDS memory per SIMD Wavefront 864 UINT8 WaveFrontSize; ///< 64, may be 32 for some FSA based architectures 865 UINT8 NumBanks; ///< Number of Banks or "Shader Engines", typically 1 or 2 866 UINT16 uEngineIdentifier; ///< Identifier (Rev) of the GPU uEngine or firmware 867 UINT8 NumArrays; ///< Number of SIMD Arrays per Engine 868 UINT8 NumCUPerArray; ///< Number of Compute Units (CU) per SIMD Array 869 UINT8 NumSIMDPerCU; ///< Number of SIMD representing a Compute Unit 870 UINT8 MaxSlotsScratchCU; ///< Max. Number of temp. memory ("scratch") wave slots 871 ///< available to access, may be 0 if HW has no restrictions 872 UINT8 Reserved1[4]; ///< Reserved 873 } CRAT_HSA_PROCESSING_UNIT; 874 875 /// Flags field of the CRAT Memory Affinity Structure 876 typedef struct { 877 UINT32 Enabled:1; ///< Enabled 878 UINT32 HotPluggable:1; ///< Hot Pluggable 879 UINT32 NonVolatile:1; ///< If set, the memory region represents Non-Volatile memory 880 UINT32 :29; ///< Reserved 881 } CRAT_MEMORY_FLAG; 882 883 /// CRAT Memory Affinity Structure 884 typedef struct { 885 UINT8 Type; ///< 1 - CRAT Memory Affinity Structure 886 UINT8 Length; ///< 40 887 UINT16 Reserved; ///< Reserved 888 CRAT_MEMORY_FLAG Flags; ///< Flags - Memory Affinity Structure. Indicates whether the region of memory is enabled and can be hot plugged 889 UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to 890 UINT32 BaseAddressLow; ///< Low 32Bits of the Base Address of the memory range 891 UINT32 BaseAddressHigh; ///< High 32Bits of the Base Address of the memory range 892 UINT32 LengthLow; ///< Low 32Bits of the length of the memory range 893 UINT32 LengthHigh; ///< High 32Bits of the length of the memory range 894 UINT32 Width; ///< Memory width - Specifies the number of parallel bits of the memory interface 895 UINT8 Reserved1[8]; ///< Reserved 896 } CRAT_MEMORY; 897 898 /// Flags field of the CRAT Cache Affinity structure 899 typedef struct { 900 UINT32 Enabled:1; ///< Enabled 901 UINT32 DataCache:1; ///< 1 if cache includes data 902 UINT32 InstructionCache:1; ///< 1 if cache includes instructions 903 UINT32 CpuCache:1; ///< 1 if cache is part of CPU functionality 904 UINT32 SimdCache:1; ///< 1 if cache is part of SIMD functionality 905 UINT32 :27; ///< Reserved 906 } CRAT_CACHE_FLAG; 907 908 /// CRAT Cache Affinity Structure 909 typedef struct { 910 UINT8 Type; ///< 2 - CRAT Cache Affinity Structure 911 UINT8 Length; ///< 64 912 UINT16 Reserved; ///< Reserved 913 CRAT_CACHE_FLAG Flags; ///< Flags - Cache Affinity Structure. Indicates whether the region of cache is enabled 914 UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component 915 UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor 916 UINT32 CacheSize; ///< Cache size in KB 917 UINT8 CacheLevel; ///< Integer representing level: 1, 2, 3, 4, etc. 918 UINT8 LinesPerTag; ///< Cache Lines per tag 919 UINT16 CacheLineSize; ///< Cache line size in bytes 920 UINT8 Associativity; ///< Cache associativity 921 ///< The associativity fields are encoded as follows: 922 ///< 00h: Reserved. 923 ///< 01h: Direct mapped. 924 ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.) 925 ///< FFh: Fully associative 926 UINT8 CacheProperties; ///< Cache Properties bits [2:0] represent Inclusive/Exclusive property encoded. 927 ///< 0: Cache is strictly exclusive to lower level caches. 928 ///< 1: Cache is mostly exclusive to lower level caches. 929 ///< 2: Cache is strictly inclusive to lower level caches. 930 ///< 3: Cache is mostly inclusive to lower level caches. 931 ///< 4: Cache is a "constant cache" (= explicit update) 932 ///< 5: Cache is a "specialty cache" (e.g. Texture cache) 933 ///< 6-7: Reserved 934 ///< CacheProperties bits [7:3] are reserved 935 UINT16 CacheLatency; ///< Cost of time to access cache described in nanoseconds. 936 UINT8 Reserved1[8]; ///< Reserved 937 } CRAT_CACHE; 938 939 /// Flags field of the CRAT TLB Affinity structure 940 typedef struct { 941 UINT32 Enabled:1; ///< Enabled 942 UINT32 DataTLB:1; ///< 1 if TLB includes translation information for data. 943 UINT32 InstructionTLB:1; ///< 1 if TLB includes translation information for instructions. 944 UINT32 CpuTLB:1; ///< 1 if TLB is part of CPU functionality 945 UINT32 SimdTLB:1; ///< 1 if TLB is part of SIMD functionality 946 UINT32 TLB4KBase256:1; ///< 1 if value in table is factored by 256 to get number of 4K entries 947 UINT32 :1; ///< Reserved 948 UINT32 TLB2MBase256:1; ///< 1 if value in table is factored by 256 to get number of 2M entries 949 UINT32 :1; ///< Reserved 950 UINT32 TLB1GBase256:1; ///< 1 if value in table is factored by 256 to get number of 1G entries 951 UINT32 :22; ///< Reserved 952 } CRAT_TLB_FLAG; 953 954 /// CRAT TLB Affinity Structure 955 typedef struct { 956 UINT8 Type; ///< 3 - CRAT TLB Affinity Structure 957 UINT8 Length; ///< 64 958 UINT16 Reserved; ///< Reserved 959 CRAT_TLB_FLAG Flags; ///< Flags - TLB Affinity Structure. Indicates whether the TLB is enabled and defined 960 UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component. 961 UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor 962 UINT32 TlbLevel; ///< Integer representing level: 1, 2, 3, 4, etc. 963 UINT8 DataTlbAssociativity2MB; ///< Data TLB associativity for 2MB pages 964 ///< The associativity fields are encoded as follows: 965 ///< 00h: Reserved. 966 ///< 01h: Direct mapped. 967 ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.) 968 ///< FFh: Fully associative. 969 UINT8 DataTlbSize2MB; ///< Data TLB number of entries for 2MB. 970 UINT8 InstructionTlbAssociativity2MB; ///< Instruction TLB associativity for 2MB pages 971 ///< The associativity fields are encoded as follows: 972 ///< 00h: Reserved. 973 ///< 01h: Direct mapped. 974 ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.) 975 ///< FFh: Fully associative. 976 UINT8 InstructionTlbSize2MB; ///< Instruction TLB number of entries for 2MB pages. 977 UINT8 DataTlbAssociativity4K; ///< Data TLB Associativity for 4KB pages 978 UINT8 DataTlbSize4K; ///< Data TLB number of entries for 4KB pages 979 UINT8 InstructionTlbAssociativity4K; ///< Instruction TLB Associativity for 4KB pages 980 UINT8 InstructionTlbSize4K; ///< Instruction TLB number of entries for 4KB pages 981 UINT8 DataTlbAssociativity1G; ///< Data TLB Associativity for 1GB pages 982 UINT8 DataTlbSize1G; ///< Data TLB number of entries for 1GB pages 983 UINT8 InstructionTlbAssociativity1G; ///< Instruction TLB Associativity for 1GB pages 984 UINT8 InstructionTlbSize1G; ///< Instruction TLB number of entries for 1GB pages 985 UINT8 Reserved1[4]; ///< Reserved 986 } CRAT_TLB; 987 988 /// Flags field of the CRAT FPU Affinity structure 989 typedef struct { 990 UINT32 Enabled:1; ///< Enabled 991 UINT32 :31; ///< Reserved 992 } CRAT_FPU_FLAG; 993 994 /// CRAT FPU Affinity Structure 995 typedef struct { 996 UINT8 Type; ///< 4 - CRAT FPU Affinity Structure 997 UINT8 Length; ///< 64 998 UINT16 Reserved; ///< Reserved 999 CRAT_FPU_FLAG Flags; ///< Flags - FPU Affinity Structure. Indicates whether the region of FPU affinity structure is enabled and defined 1000 UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component. 1001 UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor 1002 UINT32 FPUSize; ///< Product specific 1003 UINT8 Reserved1[16]; ///< Reserved 1004 } CRAT_FPU; 1005 1006 /// Flags field of the CRAT IO Affinity structure 1007 typedef struct { 1008 UINT32 Enabled:1; ///< Enabled 1009 UINT32 Coherency:1; ///< If set, IO interface supports coherent transactions (natively or through protocol extensions) 1010 UINT32 :30; ///< Reserved 1011 } CRAT_IO_FLAG; 1012 1013 /// CRAT IO Affinity Structure 1014 typedef struct { 1015 UINT8 Type; ///< 5 - CRAT IO Affinity Structure 1016 UINT8 Length; ///< 64 1017 UINT16 Reserved; ///< Reserved 1018 CRAT_IO_FLAG Flags; ///< Flags - IO Affinity Structure. Indicates whether the region of IO affinity structure is enabled and defined. 1019 UINT32 ProximityDomainFrom; ///< Integer that represents the proximity domain to which the IO Interface belongs to 1020 UINT32 ProximityDomainTo; ///< Integer that represents the other proximity domain to which the IO Interface belongs to 1021 UINT8 IoType; ///< IO Interface type. Values defined are 1022 ///< 0: Undefined 1023 ///< 1: Hypertransport 1024 ///< 2: PCI Express 1025 ///< 3: Other (e.g. internal) 1026 ///< 4-255: Reserved 1027 UINT8 VersionMajor; ///< Major version of the Bus interface 1028 UINT16 VersionMinor; ///< Minor version of the Bus interface ((optional) 1029 UINT32 MinimumLatency; ///< Cost of time to transfer, described in nanoseconds. 1030 UINT32 MaximumLatency; ///< Cost of time to transfer, described in nanoseconds. 1031 UINT32 MinimumBandwidth; ///< Minimum interface Bandwidth in MB/s 1032 UINT32 MaximumBandwidth; ///< Maximum interface Bandwidth in MB/s 1033 UINT32 RecommendedTransferSize; ///< Recommended transfer size to reach maximum interface bandwidth in Bytes 1034 UINT8 Reserved1[24]; ///< Reserved 1035 } CRAT_IO; 1036 1037 #define CRAT_MAX_LENGTH 0x800ul ///< Reserve 2K for CRAT 1038 /// CRAT entry type 1039 typedef enum { 1040 CRAT_TYPE_HSA_PROC_UNIT = 0, ///< 0 - CRAT HSA Processing Unit Structure 1041 CRAT_TYPE_MEMORY, ///< 1 - CRAT Memory Affinity Structure 1042 CRAT_TYPE_CACHE, ///< 2 - CRAT Cache Affinity Structure 1043 CRAT_TYPE_TLB, ///< 3 - CRAT TLB Affinity Structure 1044 CRAT_TYPE_FPU, ///< 4 - CRAT FPU Affinity Structure 1045 CRAT_TYPE_IO, ///< 5 - CRAT IO Affinity Structure 1046 } CRAT_ENTRY_TYPE; 1047 1048 /*---------------------------------------------------------------------------------------- 1049 * F U N C T I O N P R O T O T Y P E 1050 *---------------------------------------------------------------------------------------- 1051 */ 1052 1053 AGESA_STATUS 1054 AmdCpuLate ( 1055 IN AMD_CONFIG_PARAMS *StdHeader, 1056 IN PLATFORM_CONFIGURATION *PlatformConfig 1057 ); 1058 1059 AGESA_STATUS 1060 CreateAcpiWhea ( 1061 IN OUT AMD_CONFIG_PARAMS *StdHeader, 1062 IN OUT VOID **WheaMcePtr, 1063 IN OUT VOID **WheaCmcPtr 1064 ); 1065 1066 AGESA_STATUS 1067 CreateDmiRecords ( 1068 IN OUT AMD_CONFIG_PARAMS *StdHeader, 1069 IN OUT DMI_INFO **DmiTable 1070 ); 1071 1072 AGESA_STATUS 1073 GetType4Type7Info ( 1074 IN AP_EXE_PARAMS *ApExeParams 1075 ); 1076 1077 VOID 1078 DmiGetT4ProcFamilyFromBrandId ( 1079 IN OUT UINT8 *T4ProcFamily, 1080 IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, 1081 IN CPU_TYPE_INFO *CpuInfo, 1082 IN AMD_CONFIG_PARAMS *StdHeader 1083 ); 1084 1085 VOID 1086 GetNameString ( 1087 IN OUT CHAR8 *String, 1088 IN OUT AMD_CONFIG_PARAMS *StdHeader 1089 ); 1090 1091 BOOLEAN 1092 IsSourceStrContainTargetStr ( 1093 IN OUT CHAR8 *SourceStr, 1094 IN OUT CONST CHAR8 *TargetStr, 1095 IN OUT AMD_CONFIG_PARAMS *StdHeader 1096 ); 1097 1098 AGESA_STATUS 1099 CreateAcpiCrat ( 1100 IN OUT AMD_CONFIG_PARAMS *StdHeader, 1101 OUT VOID **CratPtr 1102 ); 1103 1104 AGESA_STATUS 1105 CreateAcpiCdit ( 1106 IN OUT AMD_CONFIG_PARAMS *StdHeader, 1107 IN PLATFORM_CONFIGURATION *PlatformConfig, 1108 OUT VOID **CditPtr 1109 ); 1110 1111 AGESA_STATUS 1112 CreateAcpiSrat ( 1113 IN OUT AMD_CONFIG_PARAMS *StdHeader, 1114 IN OUT VOID **SratPtr 1115 ); 1116 1117 AGESA_STATUS 1118 CreateAcpiSlit ( 1119 IN OUT AMD_CONFIG_PARAMS *StdHeader, 1120 IN PLATFORM_CONFIGURATION *PlatformConfig, 1121 IN OUT VOID **SlitPtr 1122 ); 1123 1124 VOID 1125 ChecksumAcpiTable ( 1126 IN OUT ACPI_TABLE_HEADER *Table, 1127 IN AMD_CONFIG_PARAMS *StdHeader 1128 ); 1129 1130 AGESA_STATUS 1131 RunLateApTaskOnAllAPs ( 1132 IN AP_EXE_PARAMS *ApParams, 1133 IN AMD_CONFIG_PARAMS *StdHeader 1134 ); 1135 1136 AGESA_STATUS 1137 RunLateApTaskOnAllCore0s ( 1138 IN AP_EXE_PARAMS *ApParams, 1139 IN AMD_CONFIG_PARAMS *StdHeader 1140 ); 1141 1142 #endif // _CPU_LATE_INIT_H_ 1143