1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32l4xx_ll_rcc.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif
28 /** @addtogroup STM32L4xx_LL_Driver
29 * @{
30 */
31
32 #if defined(RCC)
33
34 /** @addtogroup RCC_LL
35 * @{
36 */
37
38 /* Private types -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /* Private constants ---------------------------------------------------------*/
41 /* Private macros ------------------------------------------------------------*/
42 /** @addtogroup RCC_LL_Private_Macros
43 * @{
44 */
45 #if defined(RCC_CCIPR_USART3SEL)
46 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
47 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
48 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
49 #else
50 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
51 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
52
53 #endif /* RCC_CCIPR_USART3SEL */
54 #if defined(RCC_CCIPR_UART4SEL) && defined(RCC_CCIPR_UART5SEL)
55 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
56 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
57 #elif defined(RCC_CCIPR_UART4SEL)
58 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
59 #elif defined(RCC_CCIPR_UART5SEL)
60 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)
61 #endif /* RCC_CCIPR_UART4SEL && RCC_CCIPR_UART5SEL*/
62
63 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
64
65 #if defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) && defined(RCC_CCIPR2_I2C4SEL)
66 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
67 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
68 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
69 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
70 #elif defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL)
71 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
72 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
73 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
74
75 #elif !defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL)
76 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
77 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
78
79 #else
80 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
81
82 #endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL && RCC_CCIPR2_I2C4SEL */
83 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
84 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))
85
86 #if defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI2SEL)
87 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
88 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
89 #elif defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
90 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
91 #endif /* RCC_CCIPR_SAI2SEL RCC_CCIPR2_SAI2SEL ||*/
92
93 #if defined(SDMMC1)
94 #if defined(RCC_CCIPR2_SDMMCSEL)
95 #define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_KERNELCLKSOURCE))
96 #endif /* RCC_CCIPR2_SDMMCSEL */
97
98 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
99 #endif /* SDMMC1 */
100
101 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
102
103 #if defined(USB_OTG_FS) || defined(USB)
104 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
105 #endif /* USB_OTG_FS || USB */
106
107 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
108
109 #if defined(SWPMI1)
110 #define IS_LL_RCC_SWPMI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SWPMI1_CLKSOURCE))
111 #endif /* SWPMI1 */
112
113 #if defined(DFSDM1_Channel0)
114 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
115 #if defined(RCC_CCIPR2_DFSDM1SEL)
116 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
117 #endif /* RCC_CCIPR2_DFSDM1SEL */
118 #endif /* DFSDM1_Channel0 */
119
120 #if defined(DSI)
121 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
122 #endif /* DSI */
123
124 #if defined(LTDC)
125 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
126 #endif /* LTDC */
127
128 #if defined(OCTOSPI1)
129 #define IS_LL_RCC_OCTOSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OCTOSPI_CLKSOURCE))
130 #endif /* OCTOSPI */
131
132 /**
133 * @}
134 */
135
136 /* Private function prototypes -----------------------------------------------*/
137 /** @defgroup RCC_LL_Private_Functions RCC Private functions
138 * @{
139 */
140 uint32_t RCC_GetSystemClockFreq(void);
141 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
142 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
143 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
144 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
145 uint32_t RCC_PLL_GetFreqDomain_SAI(void);
146 uint32_t RCC_PLL_GetFreqDomain_48M(void);
147 #if defined(RCC_PLLSAI1_SUPPORT)
148 uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);
149 uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
150 uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
151 #endif /* RCC_PLLSAI1_SUPPORT */
152 #if defined(RCC_PLLSAI2_SUPPORT)
153 uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void);
154 #if defined(LTDC)
155 uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void);
156 #else
157 uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void);
158 #endif /* LTDC */
159 #if defined(DSI)
160 uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void);
161 #endif /* DSI */
162 #endif /*RCC_PLLSAI2_SUPPORT*/
163 /**
164 * @}
165 */
166
167
168 /* Exported functions --------------------------------------------------------*/
169 /** @addtogroup RCC_LL_Exported_Functions
170 * @{
171 */
172
173 /** @addtogroup RCC_LL_EF_Init
174 * @{
175 */
176
177 /**
178 * @brief Reset the RCC clock configuration to the default reset state.
179 * @note The default reset state of the clock configuration is given below:
180 * - MSI ON and used as system clock source
181 * - HSE, HSI, PLL, PLLSAI1 and PLLSAI2 OFF
182 * - AHB, APB1 and APB2 prescaler set to 1.
183 * - CSS, MCO OFF
184 * - All interrupts disabled
185 * @note This function doesn't modify the configuration of the
186 * - Peripheral clocks
187 * - LSI, LSE and RTC clocks
188 * @retval An ErrorStatus enumeration value:
189 * - SUCCESS: RCC registers are de-initialized
190 * - ERROR: not applicable
191 */
LL_RCC_DeInit(void)192 ErrorStatus LL_RCC_DeInit(void)
193 {
194 __IO uint32_t vl_mask;
195
196 /* Set MSION bit */
197 LL_RCC_MSI_Enable();
198
199 /* Insure MSIRDY bit is set before writing default MSIRANGE value */
200 while (LL_RCC_MSI_IsReady() == 0U)
201 {
202 }
203
204 /* Set MSIRANGE default value */
205 LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
206
207 /* Set MSITRIM bits to the reset value*/
208 LL_RCC_MSI_SetCalibTrimming(0);
209
210 /* Set HSITRIM bits to the reset value*/
211 LL_RCC_HSI_SetCalibTrimming(0x10U);
212
213 /* Reset CFGR register */
214 LL_RCC_WriteReg(CFGR, 0x00000000U);
215
216 /* Read CR register */
217 vl_mask = LL_RCC_ReadReg(CR);
218
219 /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON bits */
220 CLEAR_BIT(vl_mask,
221 (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_PLLON));
222
223 #if defined(RCC_PLLSAI1_SUPPORT)
224 /* Reset PLLSAI1ON bit */
225 CLEAR_BIT(vl_mask, RCC_CR_PLLSAI1ON);
226 #endif /*RCC_PLLSAI1_SUPPORT*/
227
228 #if defined(RCC_PLLSAI2_SUPPORT)
229 /* Reset PLLSAI2ON bit */
230 CLEAR_BIT(vl_mask, RCC_CR_PLLSAI2ON);
231 #endif /*RCC_PLLSAI2_SUPPORT*/
232
233 /* Write new value in CR register */
234 LL_RCC_WriteReg(CR, vl_mask);
235
236 #if defined(RCC_PLLSAI2_SUPPORT)
237 /* Wait for PLLRDY, PLLSAI1RDY and PLLSAI2RDY bits to be reset */
238 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U)
239 {
240 }
241 #elif defined(RCC_PLLSAI1_SUPPORT)
242 /* Wait for PLLRDY and PLLSAI1RDY to be reset */
243 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U)
244 {
245 }
246 #else
247 /* Wait for PLLRDY bit to be reset */
248 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
249 {
250 }
251 #endif
252
253 /* Reset PLLCFGR register */
254 LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);
255
256 #if defined(RCC_PLLSAI1_SUPPORT)
257 /* Reset PLLSAI1CFGR register */
258 LL_RCC_WriteReg(PLLSAI1CFGR, 16U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
259 #endif /*RCC_PLLSAI1_SUPPORT*/
260
261 #if defined(RCC_PLLSAI2_SUPPORT)
262 /* Reset PLLSAI2CFGR register */
263 LL_RCC_WriteReg(PLLSAI2CFGR, 16U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
264 #endif /*RCC_PLLSAI2_SUPPORT*/
265
266 /* Reset HSEBYP bit */
267 LL_RCC_HSE_DisableBypass();
268
269 /* Disable all interrupts */
270 LL_RCC_WriteReg(CIER, 0x00000000U);
271
272 /* Clear all interrupt flags */
273 vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \
274 RCC_CICR_CSSC | RCC_CICR_LSECSSC;
275 #if defined(RCC_HSI48_SUPPORT)
276 vl_mask |= RCC_CICR_HSI48RDYC;
277 #endif
278 #if defined(RCC_PLLSAI1_SUPPORT)
279 vl_mask |= RCC_CICR_PLLSAI1RDYC;
280 #endif
281 #if defined(RCC_PLLSAI2_SUPPORT)
282 vl_mask |= RCC_CICR_PLLSAI2RDYC;
283 #endif
284 LL_RCC_WriteReg(CICR, vl_mask);
285
286 /* Clear reset flags */
287 LL_RCC_ClearResetFlags();
288
289 return SUCCESS;
290 }
291
292 /**
293 * @}
294 */
295
296 /** @addtogroup RCC_LL_EF_Get_Freq
297 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
298 * and different peripheral clocks available on the device.
299 * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*)
300 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
301 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
302 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
303 * or HSI_VALUE(**) or MSI_VALUE(*) multiplied/divided by the PLL factors.
304 * @note (*) MSI_VALUE is a constant defined in this file (default value
305 * 4 MHz) but the real value may vary depending on the variations
306 * in voltage and temperature.
307 * @note (**) HSI_VALUE is a constant defined in this file (default value
308 * 16 MHz) but the real value may vary depending on the variations
309 * in voltage and temperature.
310 * @note (***) HSE_VALUE is a constant defined in this file (default value
311 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
312 * frequency of the crystal used. Otherwise, this function may
313 * have wrong result.
314 * @note The result of this function could be incorrect when using fractional
315 * value for HSE crystal.
316 * @note This function can be used by the user application to compute the
317 * baud-rate for the communication peripherals or configure other parameters.
318 * @{
319 */
320
321 /**
322 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
323 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
324 * must be called to update structure fields. Otherwise, any
325 * configuration based on this function will be incorrect.
326 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
327 * @retval None
328 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)329 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
330 {
331 /* Get SYSCLK frequency */
332 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
333
334 /* HCLK clock frequency */
335 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
336
337 /* PCLK1 clock frequency */
338 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
339
340 /* PCLK2 clock frequency */
341 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
342 }
343
344 /**
345 * @brief Return USARTx clock frequency
346 * @param USARTxSource This parameter can be one of the following values:
347 * @arg @ref LL_RCC_USART1_CLKSOURCE
348 * @arg @ref LL_RCC_USART2_CLKSOURCE
349 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
350 *
351 * (*) value not defined in all devices.
352 * @retval USART clock frequency (in Hz)
353 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
354 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)355 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
356 {
357 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
358
359 /* Check parameter */
360 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
361
362 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
363 {
364 /* USART1CLK clock frequency */
365 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
366 {
367 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
368 usart_frequency = RCC_GetSystemClockFreq();
369 break;
370
371 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
372 if (LL_RCC_HSI_IsReady() != 0U)
373 {
374 usart_frequency = HSI_VALUE;
375 }
376 break;
377
378 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
379 if (LL_RCC_LSE_IsReady() != 0U)
380 {
381 usart_frequency = LSE_VALUE;
382 }
383 break;
384
385 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
386 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
387 break;
388
389 default:
390 break;
391 }
392 }
393 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
394 {
395 /* USART2CLK clock frequency */
396 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
397 {
398 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
399 usart_frequency = RCC_GetSystemClockFreq();
400 break;
401
402 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
403 if (LL_RCC_HSI_IsReady() != 0U)
404 {
405 usart_frequency = HSI_VALUE;
406 }
407 break;
408
409 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
410 if (LL_RCC_LSE_IsReady() != 0U)
411 {
412 usart_frequency = LSE_VALUE;
413 }
414 break;
415
416 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
417 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
418 break;
419
420 default:
421 break;
422 }
423 }
424 else
425 {
426 #if defined(RCC_CCIPR_USART3SEL)
427 if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
428 {
429 /* USART3CLK clock frequency */
430 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
431 {
432 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
433 usart_frequency = RCC_GetSystemClockFreq();
434 break;
435
436 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
437 if (LL_RCC_HSI_IsReady() != 0U)
438 {
439 usart_frequency = HSI_VALUE;
440 }
441 break;
442
443 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
444 if (LL_RCC_LSE_IsReady() != 0U)
445 {
446 usart_frequency = LSE_VALUE;
447 }
448 break;
449
450 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
451 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
452 break;
453
454 default:
455 break;
456 }
457 }
458 #endif /* RCC_CCIPR_USART3SEL */
459 }
460 return usart_frequency;
461 }
462
463 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
464 /**
465 * @brief Return UARTx clock frequency
466 * @param UARTxSource This parameter can be one of the following values:
467 * @arg @ref LL_RCC_UART4_CLKSOURCE
468 * @arg @ref LL_RCC_UART5_CLKSOURCE
469 * @retval UART clock frequency (in Hz)
470 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
471 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)472 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
473 {
474 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
475
476 /* Check parameter */
477 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
478
479 #if defined(RCC_CCIPR_UART4SEL)
480 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
481 {
482 /* UART4CLK clock frequency */
483 switch (LL_RCC_GetUARTClockSource(UARTxSource))
484 {
485 case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
486 uart_frequency = RCC_GetSystemClockFreq();
487 break;
488
489 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
490 if (LL_RCC_HSI_IsReady() != 0U)
491 {
492 uart_frequency = HSI_VALUE;
493 }
494 break;
495
496 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
497 if (LL_RCC_LSE_IsReady() != 0U)
498 {
499 uart_frequency = LSE_VALUE;
500 }
501 break;
502
503 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
504 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
505 break;
506
507 default:
508 break;
509 }
510 }
511 #endif /* RCC_CCIPR_UART4SEL */
512
513 #if defined(RCC_CCIPR_UART5SEL)
514 if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
515 {
516 /* UART5CLK clock frequency */
517 switch (LL_RCC_GetUARTClockSource(UARTxSource))
518 {
519 case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
520 uart_frequency = RCC_GetSystemClockFreq();
521 break;
522
523 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
524 if (LL_RCC_HSI_IsReady() != 0U)
525 {
526 uart_frequency = HSI_VALUE;
527 }
528 break;
529
530 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
531 if (LL_RCC_LSE_IsReady() != 0U)
532 {
533 uart_frequency = LSE_VALUE;
534 }
535 break;
536
537 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
538 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
539 break;
540
541 default:
542 break;
543 }
544 }
545 #endif /* RCC_CCIPR_UART5SEL */
546
547 return uart_frequency;
548 }
549 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
550
551 /**
552 * @brief Return I2Cx clock frequency
553 * @param I2CxSource This parameter can be one of the following values:
554 * @arg @ref LL_RCC_I2C1_CLKSOURCE
555 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
556 * @arg @ref LL_RCC_I2C3_CLKSOURCE
557 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
558 *
559 * (*) value not defined in all devices.
560 * @retval I2C clock frequency (in Hz)
561 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
562 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)563 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
564 {
565 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
566
567 /* Check parameter */
568 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
569
570 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
571 {
572 /* I2C1 CLK clock frequency */
573 switch (LL_RCC_GetI2CClockSource(I2CxSource))
574 {
575 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
576 i2c_frequency = RCC_GetSystemClockFreq();
577 break;
578
579 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
580 if (LL_RCC_HSI_IsReady() != 0U)
581 {
582 i2c_frequency = HSI_VALUE;
583 }
584 break;
585
586 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
587 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
588 break;
589
590 default:
591 break;
592 }
593 }
594 #if defined(RCC_CCIPR_I2C2SEL)
595 else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
596 {
597 /* I2C2 CLK clock frequency */
598 switch (LL_RCC_GetI2CClockSource(I2CxSource))
599 {
600 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
601 i2c_frequency = RCC_GetSystemClockFreq();
602 break;
603
604 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
605 if (LL_RCC_HSI_IsReady() != 0U)
606 {
607 i2c_frequency = HSI_VALUE;
608 }
609 break;
610
611 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
612 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
613 break;
614
615 default:
616 break;
617 }
618 }
619 #endif /*RCC_CCIPR_I2C2SEL*/
620 else
621 {
622 if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
623 {
624 /* I2C3 CLK clock frequency */
625 switch (LL_RCC_GetI2CClockSource(I2CxSource))
626 {
627 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
628 i2c_frequency = RCC_GetSystemClockFreq();
629 break;
630
631 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
632 if (LL_RCC_HSI_IsReady() != 0U)
633 {
634 i2c_frequency = HSI_VALUE;
635 }
636 break;
637
638 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
639 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
640 break;
641
642 default:
643 break;
644 }
645 }
646 #if defined(RCC_CCIPR2_I2C4SEL)
647 else
648 {
649 if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
650 {
651 /* I2C4 CLK clock frequency */
652 switch (LL_RCC_GetI2CClockSource(I2CxSource))
653 {
654 case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
655 i2c_frequency = RCC_GetSystemClockFreq();
656 break;
657
658 case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
659 if (LL_RCC_HSI_IsReady() != 0U)
660 {
661 i2c_frequency = HSI_VALUE;
662 }
663 break;
664
665 case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
666 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
667 break;
668
669 default:
670 break;
671 }
672 }
673 }
674 #endif /*RCC_CCIPR2_I2C4SEL*/
675 }
676
677 return i2c_frequency;
678 }
679
680
681 /**
682 * @brief Return LPUARTx clock frequency
683 * @param LPUARTxSource This parameter can be one of the following values:
684 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
685 * @retval LPUART clock frequency (in Hz)
686 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
687 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)688 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
689 {
690 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
691
692 /* Check parameter */
693 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
694
695 /* LPUART1CLK clock frequency */
696 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
697 {
698 case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
699 lpuart_frequency = RCC_GetSystemClockFreq();
700 break;
701
702 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
703 if (LL_RCC_HSI_IsReady() != 0U)
704 {
705 lpuart_frequency = HSI_VALUE;
706 }
707 break;
708
709 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
710 if (LL_RCC_LSE_IsReady() != 0U)
711 {
712 lpuart_frequency = LSE_VALUE;
713 }
714 break;
715
716 case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */
717 lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
718 break;
719
720 default:
721 break;
722 }
723
724 return lpuart_frequency;
725 }
726
727 /**
728 * @brief Return LPTIMx clock frequency
729 * @param LPTIMxSource This parameter can be one of the following values:
730 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
731 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
732 * @retval LPTIM clock frequency (in Hz)
733 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
734 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)735 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
736 {
737 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
738
739 /* Check parameter */
740 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
741
742 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
743 {
744 /* LPTIM1CLK clock frequency */
745 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
746 {
747 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
748 if (LL_RCC_LSI_IsReady() != 0U)
749 {
750 #if defined(RCC_CSR_LSIPREDIV)
751 if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128)
752 {
753 lptim_frequency = LSI_VALUE / 128U;
754 }
755 else
756 #endif /* RCC_CSR_LSIPREDIV */
757 {
758 lptim_frequency = LSI_VALUE;
759 }
760 }
761 break;
762
763 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
764 if (LL_RCC_HSI_IsReady() != 0U)
765 {
766 lptim_frequency = HSI_VALUE;
767 }
768 break;
769
770 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
771 if (LL_RCC_LSE_IsReady() != 0U)
772 {
773 lptim_frequency = LSE_VALUE;
774 }
775 break;
776
777 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
778 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
779 break;
780
781 default:
782 break;
783 }
784 }
785 else
786 {
787 if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE)
788 {
789 /* LPTIM2CLK clock frequency */
790 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
791 {
792 case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */
793 if (LL_RCC_LSI_IsReady() != 0U)
794 {
795 #if defined(RCC_CSR_LSIPREDIV)
796 if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128)
797 {
798 lptim_frequency = LSI_VALUE / 128U;
799 }
800 else
801 #endif /* RCC_CSR_LSIPREDIV */
802 {
803 lptim_frequency = LSI_VALUE;
804 }
805 }
806 break;
807
808 case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */
809 if (LL_RCC_HSI_IsReady() != 0U)
810 {
811 lptim_frequency = HSI_VALUE;
812 }
813 break;
814
815 case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */
816 if (LL_RCC_LSE_IsReady() != 0U)
817 {
818 lptim_frequency = LSE_VALUE;
819 }
820 break;
821
822 case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */
823 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
824 break;
825
826 default:
827 break;
828 }
829 }
830 }
831
832 return lptim_frequency;
833 }
834
835 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI1SEL) || defined(RCC_CCIPR2_SAI2SEL)
836 /**
837 * @brief Return SAIx clock frequency
838 * @param SAIxSource This parameter can be one of the following values:
839 * @arg @ref LL_RCC_SAI1_CLKSOURCE
840 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
841 *
842 * (*) value not defined in all devices.
843 * @retval SAI clock frequency (in Hz)
844 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
845
846 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)847 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
848 {
849 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
850
851 /* Check parameter */
852 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
853
854 if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
855 {
856 /* SAI1CLK clock frequency */
857 switch (LL_RCC_GetSAIClockSource(SAIxSource))
858 {
859 case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */
860 if (LL_RCC_PLLSAI1_IsReady() != 0U)
861 {
862 sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
863 }
864 break;
865
866 #if defined(RCC_PLLSAI2_SUPPORT)
867 case LL_RCC_SAI1_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI1 clock source */
868 if (LL_RCC_PLLSAI2_IsReady() != 0U)
869 {
870 sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
871 }
872 break;
873
874 #endif /* RCC_PLLSAI2_SUPPORT */
875 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
876 if (LL_RCC_PLL_IsReady() != 0U)
877 {
878 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
879 }
880 break;
881
882 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
883 sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
884 break;
885
886 default:
887 break;
888 }
889 }
890 else
891 {
892 #if defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI2SEL)
893 if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
894 {
895 /* SAI2CLK clock frequency */
896 switch (LL_RCC_GetSAIClockSource(SAIxSource))
897 {
898 case LL_RCC_SAI2_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI2 clock source */
899 if (LL_RCC_PLLSAI1_IsReady() != 0U)
900 {
901 sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
902 }
903 break;
904
905 #if defined(RCC_PLLSAI2_SUPPORT)
906 case LL_RCC_SAI2_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI2 clock source */
907 if (LL_RCC_PLLSAI2_IsReady() != 0U)
908 {
909 sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
910 }
911 break;
912
913 #endif /* RCC_PLLSAI2_SUPPORT */
914 case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
915 if (LL_RCC_PLL_IsReady() != 0U)
916 {
917 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
918 }
919 break;
920
921 case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
922 sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE;
923 break;
924
925 default:
926 break;
927 }
928 }
929 #endif /* RCC_CCIPR_SAI2SEL || RCC_CCIPR2_SAI2SEL */
930 }
931
932 return sai_frequency;
933 }
934 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR_SAI2SEL || RCC_CCIPR2_SAI1SEL || RCC_CCIPR2_SAI2SEL*/
935
936 #if defined(SDMMC1)
937 #if defined(RCC_CCIPR2_SDMMCSEL)
938 /**
939 * @brief Return SDMMCx kernel clock frequency
940 * @param SDMMCxSource This parameter can be one of the following values:
941 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
942 * @retval SDMMC clock frequency (in Hz)
943 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
944 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
945 */
LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)946 uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)
947 {
948 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
949
950 /* Check parameter */
951 assert_param(IS_LL_RCC_SDMMC_KERNELCLKSOURCE(SDMMCxSource));
952
953 /* SDMMC1CLK kernel clock frequency */
954 switch (LL_RCC_GetSDMMCKernelClockSource(SDMMCxSource))
955 {
956 case LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK: /* 48MHz clock from internal multiplexor used as SDMMC1 clock source */
957 sdmmc_frequency = LL_RCC_GetSDMMCClockFreq(LL_RCC_SDMMC1_CLKSOURCE);
958 break;
959
960 case LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP: /* PLL "P" output (PLLSAI3CLK) clock used as SDMMC1 clock source */
961 if (LL_RCC_PLL_IsReady() != 0U)
962 {
963 sdmmc_frequency = RCC_PLL_GetFreqDomain_SAI();
964 }
965 break;
966
967 default:
968 sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
969 break;
970 }
971
972 return sdmmc_frequency;
973 }
974 #endif
975
976 /**
977 * @brief Return SDMMCx clock frequency
978 * @param SDMMCxSource This parameter can be one of the following values:
979 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
980 * @retval SDMMC clock frequency (in Hz)
981 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
982 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
983 */
LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)984 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
985 {
986 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
987
988 /* Check parameter */
989 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
990
991 /* SDMMC1CLK clock frequency */
992 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
993 {
994 #if defined(LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1)
995 case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SDMMC1 clock source */
996 if (LL_RCC_PLLSAI1_IsReady() != 0U)
997 {
998 sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
999 }
1000 break;
1001 #endif
1002
1003 case LL_RCC_SDMMC1_CLKSOURCE_PLL: /* PLL clock used as SDMMC1 clock source */
1004 if (LL_RCC_PLL_IsReady() != 0U)
1005 {
1006 sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
1007 }
1008 break;
1009
1010 #if defined(LL_RCC_SDMMC1_CLKSOURCE_MSI)
1011 case LL_RCC_SDMMC1_CLKSOURCE_MSI: /* MSI clock used as SDMMC1 clock source */
1012 if (LL_RCC_MSI_IsReady() != 0U)
1013 {
1014 sdmmc_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1015 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1016 LL_RCC_MSI_GetRange() :
1017 LL_RCC_MSI_GetRangeAfterStandby()));
1018 }
1019 break;
1020 #endif
1021
1022 #if defined(RCC_HSI48_SUPPORT)
1023 case LL_RCC_SDMMC1_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */
1024 if (LL_RCC_HSI48_IsReady() != 0U)
1025 {
1026 sdmmc_frequency = HSI48_VALUE;
1027 }
1028 break;
1029 #else
1030 case LL_RCC_SDMMC1_CLKSOURCE_NONE: /* No clock used as SDMMC1 clock source */
1031 #endif
1032 default:
1033 sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1034 break;
1035 }
1036
1037 return sdmmc_frequency;
1038 }
1039 #endif /* SDMMC1 */
1040
1041 /**
1042 * @brief Return RNGx clock frequency
1043 * @param RNGxSource This parameter can be one of the following values:
1044 * @arg @ref LL_RCC_RNG_CLKSOURCE
1045 * @retval RNG clock frequency (in Hz)
1046 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
1047 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
1048 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)1049 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
1050 {
1051 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1052
1053 /* Check parameter */
1054 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
1055
1056 /* RNGCLK clock frequency */
1057 switch (LL_RCC_GetRNGClockSource(RNGxSource))
1058 {
1059 #if defined(RCC_PLLSAI1_SUPPORT)
1060 case LL_RCC_RNG_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as RNG clock source */
1061 if (LL_RCC_PLLSAI1_IsReady() != 0U)
1062 {
1063 rng_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
1064 }
1065 break;
1066 #endif /* RCC_PLLSAI1_SUPPORT */
1067
1068 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
1069 if (LL_RCC_PLL_IsReady() != 0U)
1070 {
1071 rng_frequency = RCC_PLL_GetFreqDomain_48M();
1072 }
1073 break;
1074
1075 case LL_RCC_RNG_CLKSOURCE_MSI: /* MSI clock used as RNG clock source */
1076 if (LL_RCC_MSI_IsReady() != 0U)
1077 {
1078 rng_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1079 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1080 LL_RCC_MSI_GetRange() :
1081 LL_RCC_MSI_GetRangeAfterStandby()));
1082 }
1083 break;
1084
1085
1086 #if defined(RCC_HSI48_SUPPORT)
1087 case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 used as RNG clock source */
1088 if (LL_RCC_HSI48_IsReady() != 0U)
1089 {
1090 rng_frequency = HSI48_VALUE;
1091 }
1092 break;
1093 #else
1094 case LL_RCC_RNG_CLKSOURCE_NONE: /* No clock used as RNG clock source */
1095 #endif
1096 default:
1097 rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1098 break;
1099
1100 }
1101
1102 return rng_frequency;
1103 }
1104
1105
1106 #if defined(USB_OTG_FS)||defined(USB)
1107 /**
1108 * @brief Return USBx clock frequency
1109 * @param USBxSource This parameter can be one of the following values:
1110 * @arg @ref LL_RCC_USB_CLKSOURCE
1111 * @retval USB clock frequency (in Hz)
1112 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
1113 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
1114 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)1115 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
1116 {
1117 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1118
1119 /* Check parameter */
1120 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
1121
1122 /* USBCLK clock frequency */
1123 switch (LL_RCC_GetUSBClockSource(USBxSource))
1124 {
1125 #if defined(RCC_PLLSAI1_SUPPORT)
1126 case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */
1127 if (LL_RCC_PLLSAI1_IsReady() != 0U)
1128 {
1129 usb_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
1130 }
1131 break;
1132 #endif /* RCC_PLLSAI1_SUPPORT */
1133
1134 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
1135 if (LL_RCC_PLL_IsReady() != 0U)
1136 {
1137 usb_frequency = RCC_PLL_GetFreqDomain_48M();
1138 }
1139 break;
1140
1141 case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */
1142 if (LL_RCC_MSI_IsReady() != 0U)
1143 {
1144 usb_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1145 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1146 LL_RCC_MSI_GetRange() :
1147 LL_RCC_MSI_GetRangeAfterStandby()));
1148 }
1149 break;
1150
1151 #if defined(RCC_HSI48_SUPPORT)
1152 case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 used as USB clock source */
1153 if (LL_RCC_HSI48_IsReady() != 0U)
1154 {
1155 usb_frequency = HSI48_VALUE;
1156 }
1157 break;
1158 #else
1159 case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */
1160 #endif
1161 default:
1162 usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1163 break;
1164 }
1165
1166 return usb_frequency;
1167 }
1168 #endif /* USB_OTG_FS || USB */
1169
1170 /**
1171 * @brief Return ADCx clock frequency
1172 * @param ADCxSource This parameter can be one of the following values:
1173 * @arg @ref LL_RCC_ADC_CLKSOURCE
1174 * @retval ADC clock frequency (in Hz)
1175 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
1176 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
1177 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)1178 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
1179 {
1180 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1181
1182 /* Check parameter */
1183 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
1184
1185 /* ADCCLK clock frequency */
1186 switch (LL_RCC_GetADCClockSource(ADCxSource))
1187 {
1188 #if defined(RCC_PLLSAI1_SUPPORT)
1189 case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */
1190 if (LL_RCC_PLLSAI1_IsReady() != 0U)
1191 {
1192 adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC();
1193 }
1194 break;
1195 #endif /* RCC_PLLSAI1_SUPPORT */
1196
1197 #if defined(RCC_PLLSAI2_SUPPORT) && defined(LL_RCC_ADC_CLKSOURCE_PLLSAI2)
1198 case LL_RCC_ADC_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as ADC clock source */
1199 if (LL_RCC_PLLSAI2_IsReady() != 0U)
1200 {
1201 adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC();
1202 }
1203 break;
1204 #endif /* RCC_PLLSAI2_SUPPORT && LL_RCC_ADC_CLKSOURCE_PLLSAI2 */
1205
1206 case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */
1207 adc_frequency = RCC_GetSystemClockFreq();
1208 break;
1209
1210 case LL_RCC_ADC_CLKSOURCE_NONE: /* No clock used as ADC clock source */
1211 default:
1212 adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1213 break;
1214 }
1215
1216 return adc_frequency;
1217 }
1218
1219 #if defined(SWPMI1)
1220 /**
1221 * @brief Return SWPMIx clock frequency
1222 * @param SWPMIxSource This parameter can be one of the following values:
1223 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE
1224 * @retval SWPMI clock frequency (in Hz)
1225 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready
1226 */
LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource)1227 uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource)
1228 {
1229 uint32_t swpmi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1230
1231 /* Check parameter */
1232 assert_param(IS_LL_RCC_SWPMI_CLKSOURCE(SWPMIxSource));
1233
1234 /* SWPMI1CLK clock frequency */
1235 switch (LL_RCC_GetSWPMIClockSource(SWPMIxSource))
1236 {
1237 case LL_RCC_SWPMI1_CLKSOURCE_HSI: /* SWPMI1 Clock is HSI Osc. */
1238 if (LL_RCC_HSI_IsReady())
1239 {
1240 swpmi_frequency = HSI_VALUE;
1241 }
1242 break;
1243
1244 case LL_RCC_SWPMI1_CLKSOURCE_PCLK1: /* SWPMI1 Clock is PCLK1 */
1245 swpmi_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1246 break;
1247
1248 default:
1249 break;
1250 }
1251
1252 return swpmi_frequency;
1253 }
1254 #endif /* SWPMI1 */
1255
1256 #if defined(DFSDM1_Channel0)
1257 /**
1258 * @brief Return DFSDMx clock frequency
1259 * @param DFSDMxSource This parameter can be one of the following values:
1260 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
1261 * @retval DFSDM clock frequency (in Hz)
1262 */
LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)1263 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
1264 {
1265 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1266
1267 /* Check parameter */
1268 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
1269
1270 /* DFSDM1CLK clock frequency */
1271 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
1272 {
1273 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
1274 dfsdm_frequency = RCC_GetSystemClockFreq();
1275 break;
1276
1277 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
1278 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1279 break;
1280
1281 default:
1282 break;
1283 }
1284
1285 return dfsdm_frequency;
1286 }
1287
1288 #if defined(RCC_CCIPR2_DFSDM1SEL)
1289 /**
1290 * @brief Return DFSDMx Audio clock frequency
1291 * @param DFSDMxSource This parameter can be one of the following values:
1292 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
1293 * @retval DFSDM clock frequency (in Hz)
1294 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1295 */
LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)1296 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
1297 {
1298 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1299
1300 /* Check parameter */
1301 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
1302
1303 /* DFSDM1CLK clock frequency */
1304 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
1305 {
1306 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */
1307 dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);
1308 break;
1309
1310 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI: /* MSI clock used as DFSDM1 audio clock */
1311 if (LL_RCC_MSI_IsReady() != 0U)
1312 {
1313 dfsdm_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1314 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1315 LL_RCC_MSI_GetRange() :
1316 LL_RCC_MSI_GetRangeAfterStandby()));
1317 }
1318 break;
1319
1320 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI: /* HSI clock used as DFSDM1 audio clock */
1321 default:
1322 if (LL_RCC_HSI_IsReady() != 0U)
1323 {
1324 dfsdm_frequency = HSI_VALUE;
1325 }
1326 break;
1327 }
1328
1329 return dfsdm_frequency;
1330 }
1331 #endif /* RCC_CCIPR2_DFSDM1SEL */
1332 #endif /* DFSDM1_Channel0 */
1333
1334 #if defined(DSI)
1335 /**
1336 * @brief Return DSI clock frequency
1337 * @param DSIxSource This parameter can be one of the following values:
1338 * @arg @ref LL_RCC_DSI_CLKSOURCE
1339 * @retval DSI clock frequency (in Hz)
1340 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1341 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1342 */
LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)1343 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1344 {
1345 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1346
1347 /* Check parameter */
1348 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
1349
1350 /* DSICLK clock frequency */
1351 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1352 {
1353 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLLSAI2 Osc. */
1354 if (LL_RCC_PLLSAI2_IsReady() != 0U)
1355 {
1356 dsi_frequency = RCC_PLLSAI2_GetFreqDomain_DSI();
1357 }
1358 break;
1359
1360 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
1361 default:
1362 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1363 break;
1364 }
1365
1366 return dsi_frequency;
1367 }
1368 #endif /* DSI */
1369
1370 #if defined(LTDC)
1371 /**
1372 * @brief Return LTDC clock frequency
1373 * @param LTDCxSource This parameter can be one of the following values:
1374 * @arg @ref LL_RCC_LTDC_CLKSOURCE
1375 * @retval LTDC clock frequency (in Hz)
1376 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
1377 */
LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)1378 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
1379 {
1380 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1381
1382 /* Check parameter */
1383 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
1384
1385 if (LL_RCC_PLLSAI2_IsReady() != 0U)
1386 {
1387 ltdc_frequency = RCC_PLLSAI2_GetFreqDomain_LTDC();
1388 }
1389
1390 return ltdc_frequency;
1391 }
1392 #endif /* LTDC */
1393
1394 #if defined(OCTOSPI1)
1395 /**
1396 * @brief Return OCTOSPI clock frequency
1397 * @param OCTOSPIxSource This parameter can be one of the following values:
1398 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
1399 * @retval OCTOSPI clock frequency (in Hz)
1400 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
1401 */
LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)1402 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)
1403 {
1404 uint32_t octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1405
1406 /* Check parameter */
1407 assert_param(IS_LL_RCC_OCTOSPI_CLKSOURCE(OCTOSPIxSource));
1408
1409 /* OCTOSPI clock frequency */
1410 switch (LL_RCC_GetOCTOSPIClockSource(OCTOSPIxSource))
1411 {
1412 case LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK: /* OCTOSPI clock is SYSCLK */
1413 octospi_frequency = RCC_GetSystemClockFreq();
1414 break;
1415
1416 case LL_RCC_OCTOSPI_CLKSOURCE_MSI: /* MSI clock used as OCTOSPI clock */
1417 if (LL_RCC_MSI_IsReady() != 0U)
1418 {
1419 octospi_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1420 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1421 LL_RCC_MSI_GetRange() :
1422 LL_RCC_MSI_GetRangeAfterStandby()));
1423 }
1424 break;
1425
1426 case LL_RCC_OCTOSPI_CLKSOURCE_PLL: /* PLL clock used as OCTOSPI source */
1427 if (LL_RCC_PLL_IsReady() != 0U)
1428 {
1429 octospi_frequency = RCC_PLL_GetFreqDomain_48M();
1430 }
1431 break;
1432
1433 default:
1434 octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1435 break;
1436 }
1437
1438 return octospi_frequency;
1439 }
1440 #endif /* OCTOSPI1 */
1441
1442 /**
1443 * @}
1444 */
1445
1446 /**
1447 * @}
1448 */
1449
1450 /** @addtogroup RCC_LL_Private_Functions
1451 * @{
1452 */
1453
1454 /**
1455 * @brief Return SYSTEM clock frequency
1456 * @retval SYSTEM clock frequency (in Hz)
1457 */
RCC_GetSystemClockFreq(void)1458 uint32_t RCC_GetSystemClockFreq(void)
1459 {
1460 uint32_t frequency;
1461
1462 /* Get SYSCLK source -------------------------------------------------------*/
1463 switch (LL_RCC_GetSysClkSource())
1464 {
1465 case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
1466 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1467 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1468 LL_RCC_MSI_GetRange() :
1469 LL_RCC_MSI_GetRangeAfterStandby()));
1470 break;
1471
1472 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1473 frequency = HSI_VALUE;
1474 break;
1475
1476 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1477 frequency = HSE_VALUE;
1478 break;
1479
1480 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1481 frequency = RCC_PLL_GetFreqDomain_SYS();
1482 break;
1483
1484 default:
1485 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1486 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1487 LL_RCC_MSI_GetRange() :
1488 LL_RCC_MSI_GetRangeAfterStandby()));
1489 break;
1490 }
1491
1492 return frequency;
1493 }
1494
1495 /**
1496 * @brief Return HCLK clock frequency
1497 * @param SYSCLK_Frequency SYSCLK clock frequency
1498 * @retval HCLK clock frequency (in Hz)
1499 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1500 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1501 {
1502 /* HCLK clock frequency */
1503 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1504 }
1505
1506 /**
1507 * @brief Return PCLK1 clock frequency
1508 * @param HCLK_Frequency HCLK clock frequency
1509 * @retval PCLK1 clock frequency (in Hz)
1510 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1511 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1512 {
1513 /* PCLK1 clock frequency */
1514 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1515 }
1516
1517 /**
1518 * @brief Return PCLK2 clock frequency
1519 * @param HCLK_Frequency HCLK clock frequency
1520 * @retval PCLK2 clock frequency (in Hz)
1521 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1522 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1523 {
1524 /* PCLK2 clock frequency */
1525 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1526 }
1527
1528 /**
1529 * @brief Return PLL clock frequency used for system domain
1530 * @retval PLL clock frequency (in Hz)
1531 */
RCC_PLL_GetFreqDomain_SYS(void)1532 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
1533 {
1534 uint32_t pllinputfreq, pllsource;
1535
1536 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
1537 SYSCLK = PLL_VCO / PLLR
1538 */
1539 pllsource = LL_RCC_PLL_GetMainSource();
1540
1541 switch (pllsource)
1542 {
1543 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1544 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1545 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1546 LL_RCC_MSI_GetRange() :
1547 LL_RCC_MSI_GetRangeAfterStandby()));
1548 break;
1549
1550 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1551 pllinputfreq = HSI_VALUE;
1552 break;
1553
1554 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1555 pllinputfreq = HSE_VALUE;
1556 break;
1557
1558 default:
1559 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1560 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1561 LL_RCC_MSI_GetRange() :
1562 LL_RCC_MSI_GetRangeAfterStandby()));
1563 break;
1564 }
1565 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1566 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1567 }
1568
1569 #if defined(SAI1)
1570 /**
1571 * @brief Return PLL clock frequency used for SAI domain
1572 * @retval PLL clock frequency (in Hz)
1573 */
RCC_PLL_GetFreqDomain_SAI(void)1574 uint32_t RCC_PLL_GetFreqDomain_SAI(void)
1575 {
1576 uint32_t pllinputfreq, pllsource;
1577
1578 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN
1579 SAI Domain clock = PLL_VCO / PLLP
1580 */
1581 pllsource = LL_RCC_PLL_GetMainSource();
1582
1583 switch (pllsource)
1584 {
1585 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1586 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1587 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1588 LL_RCC_MSI_GetRange() :
1589 LL_RCC_MSI_GetRangeAfterStandby()));
1590 break;
1591
1592 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1593 pllinputfreq = HSI_VALUE;
1594 break;
1595
1596 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1597 pllinputfreq = HSE_VALUE;
1598 break;
1599
1600 default:
1601 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1602 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1603 LL_RCC_MSI_GetRange() :
1604 LL_RCC_MSI_GetRangeAfterStandby()));
1605 break;
1606 }
1607 return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1608 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1609 }
1610 #endif /* SAI1 */
1611
1612 /**
1613 * @brief Return PLL clock frequency used for 48 MHz domain
1614 * @retval PLL clock frequency (in Hz)
1615 */
RCC_PLL_GetFreqDomain_48M(void)1616 uint32_t RCC_PLL_GetFreqDomain_48M(void)
1617 {
1618 uint32_t pllinputfreq, pllsource;
1619
1620 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
1621 48M Domain clock = PLL_VCO / PLLQ
1622 */
1623 pllsource = LL_RCC_PLL_GetMainSource();
1624
1625 switch (pllsource)
1626 {
1627 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1628 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1629 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1630 LL_RCC_MSI_GetRange() :
1631 LL_RCC_MSI_GetRangeAfterStandby()));
1632 break;
1633
1634 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1635 pllinputfreq = HSI_VALUE;
1636 break;
1637
1638 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1639 pllinputfreq = HSE_VALUE;
1640 break;
1641
1642 default:
1643 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1644 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1645 LL_RCC_MSI_GetRange() :
1646 LL_RCC_MSI_GetRangeAfterStandby()));
1647 break;
1648 }
1649 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1650 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1651 }
1652 #if defined(DSI)
1653 /**
1654 * @brief Return PLL clock frequency used for DSI clock
1655 * @retval PLL clock frequency (in Hz)
1656 */
RCC_PLLSAI2_GetFreqDomain_DSI(void)1657 uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void)
1658 {
1659 uint32_t pllinputfreq, pllsource;
1660
1661 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
1662 /* DSICLK = PLLSAI2_VCO / PLLSAI2R */
1663 pllsource = LL_RCC_PLL_GetMainSource();
1664
1665 switch (pllsource)
1666 {
1667 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
1668 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1669 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1670 LL_RCC_MSI_GetRange() :
1671 LL_RCC_MSI_GetRangeAfterStandby()));
1672 break;
1673
1674 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
1675 pllinputfreq = HSI_VALUE;
1676 break;
1677
1678 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
1679 pllinputfreq = HSE_VALUE;
1680 break;
1681
1682 default:
1683 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1684 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1685 LL_RCC_MSI_GetRange() :
1686 LL_RCC_MSI_GetRangeAfterStandby()));
1687 break;
1688 }
1689
1690 return __LL_RCC_CALC_PLLSAI2_DSI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
1691 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
1692 }
1693 #endif /* DSI */
1694
1695 #if defined(RCC_PLLSAI1_SUPPORT)
1696 /**
1697 * @brief Return PLLSAI1 clock frequency used for SAI domain
1698 * @retval PLLSAI1 clock frequency (in Hz)
1699 */
RCC_PLLSAI1_GetFreqDomain_SAI(void)1700 uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
1701 {
1702 uint32_t pllinputfreq, pllsource;
1703
1704 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1705 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
1706 #else
1707 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
1708 #endif
1709 /* SAI Domain clock = PLLSAI1_VCO / PLLSAI1P */
1710 pllsource = LL_RCC_PLL_GetMainSource();
1711
1712 switch (pllsource)
1713 {
1714 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1715 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1716 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1717 LL_RCC_MSI_GetRange() :
1718 LL_RCC_MSI_GetRangeAfterStandby()));
1719 break;
1720
1721 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1722 pllinputfreq = HSI_VALUE;
1723 break;
1724
1725 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1726 pllinputfreq = HSE_VALUE;
1727 break;
1728
1729 default:
1730 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1731 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1732 LL_RCC_MSI_GetRange() :
1733 LL_RCC_MSI_GetRangeAfterStandby()));
1734 break;
1735 }
1736 return __LL_RCC_CALC_PLLSAI1_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1737 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP());
1738 }
1739
1740 /**
1741 * @brief Return PLLSAI1 clock frequency used for 48Mhz domain
1742 * @retval PLLSAI1 clock frequency (in Hz)
1743 */
RCC_PLLSAI1_GetFreqDomain_48M(void)1744 uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
1745 {
1746 uint32_t pllinputfreq, pllsource;
1747
1748 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1749 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
1750 #else
1751 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
1752 #endif
1753 /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1Q */
1754 pllsource = LL_RCC_PLL_GetMainSource();
1755
1756 switch (pllsource)
1757 {
1758 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1759 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1760 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1761 LL_RCC_MSI_GetRange() :
1762 LL_RCC_MSI_GetRangeAfterStandby()));
1763 break;
1764
1765 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1766 pllinputfreq = HSI_VALUE;
1767 break;
1768
1769 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1770 pllinputfreq = HSE_VALUE;
1771 break;
1772
1773 default:
1774 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1775 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1776 LL_RCC_MSI_GetRange() :
1777 LL_RCC_MSI_GetRangeAfterStandby()));
1778 break;
1779 }
1780 return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1781 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ());
1782 }
1783
1784 /**
1785 * @brief Return PLLSAI1 clock frequency used for ADC domain
1786 * @retval PLLSAI1 clock frequency (in Hz)
1787 */
RCC_PLLSAI1_GetFreqDomain_ADC(void)1788 uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
1789 {
1790 uint32_t pllinputfreq, pllsource;
1791
1792 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1793 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
1794 #else
1795 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
1796 #endif
1797 /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1R */
1798 pllsource = LL_RCC_PLL_GetMainSource();
1799
1800 switch (pllsource)
1801 {
1802 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1803 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1804 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1805 LL_RCC_MSI_GetRange() :
1806 LL_RCC_MSI_GetRangeAfterStandby()));
1807 break;
1808
1809 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1810 pllinputfreq = HSI_VALUE;
1811 break;
1812
1813 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1814 pllinputfreq = HSE_VALUE;
1815 break;
1816
1817 default:
1818 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1819 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1820 LL_RCC_MSI_GetRange() :
1821 LL_RCC_MSI_GetRangeAfterStandby()));
1822 break;
1823 }
1824 return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1825 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR());
1826 }
1827 #endif /* RCC_PLLSAI1_SUPPORT */
1828
1829 #if defined(RCC_PLLSAI2_SUPPORT)
1830 /**
1831 * @brief Return PLLSAI2 clock frequency used for SAI domain
1832 * @retval PLLSAI2 clock frequency (in Hz)
1833 */
RCC_PLLSAI2_GetFreqDomain_SAI(void)1834 uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void)
1835 {
1836 uint32_t pllinputfreq, pllsource;
1837
1838 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1839 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
1840 #else
1841 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */
1842 #endif
1843 /* SAI Domain clock = PLLSAI2_VCO / PLLSAI2P */
1844 pllsource = LL_RCC_PLL_GetMainSource();
1845
1846 switch (pllsource)
1847 {
1848 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
1849 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1850 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1851 LL_RCC_MSI_GetRange() :
1852 LL_RCC_MSI_GetRangeAfterStandby()));
1853 break;
1854
1855 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
1856 pllinputfreq = HSI_VALUE;
1857 break;
1858
1859 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
1860 pllinputfreq = HSE_VALUE;
1861 break;
1862
1863 default:
1864 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1865 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1866 LL_RCC_MSI_GetRange() :
1867 LL_RCC_MSI_GetRangeAfterStandby()));
1868 break;
1869 }
1870 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1871 return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
1872 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());
1873 #else
1874 return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1875 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());
1876 #endif
1877 }
1878
1879 #if defined(LTDC)
1880 /**
1881 * @brief Return PLLSAI2 clock frequency used for LTDC domain
1882 * @retval PLLSAI2 clock frequency (in Hz)
1883 */
RCC_PLLSAI2_GetFreqDomain_LTDC(void)1884 uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void)
1885 {
1886 uint32_t pllinputfreq, pllsource;
1887
1888 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
1889 /* LTDC Domain clock = (PLLSAI2_VCO / PLLSAI2R) / PLLSAI2DIVR */
1890 pllsource = LL_RCC_PLL_GetMainSource();
1891
1892 switch (pllsource)
1893 {
1894 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
1895 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1896 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1897 LL_RCC_MSI_GetRange() :
1898 LL_RCC_MSI_GetRangeAfterStandby()));
1899 break;
1900
1901 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
1902 pllinputfreq = HSI_VALUE;
1903 break;
1904
1905 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
1906 pllinputfreq = HSE_VALUE;
1907 break;
1908
1909 default:
1910 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1911 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1912 LL_RCC_MSI_GetRange() :
1913 LL_RCC_MSI_GetRangeAfterStandby()));
1914 break;
1915 }
1916
1917 return __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
1918 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR(), LL_RCC_PLLSAI2_GetDIVR());
1919 }
1920
1921 #else
1922
1923 /**
1924 * @brief Return PLLSAI2 clock frequency used for ADC domain
1925 * @retval PLLSAI2 clock frequency (in Hz)
1926 */
RCC_PLLSAI2_GetFreqDomain_ADC(void)1927 uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void)
1928 {
1929 uint32_t pllinputfreq = 0U, pllsource = 0U;
1930
1931 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */
1932 /* 48M Domain clock = PLLSAI2_VCO / PLLSAI2R */
1933 pllsource = LL_RCC_PLL_GetMainSource();
1934
1935 switch (pllsource)
1936 {
1937 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
1938 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1939 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1940 LL_RCC_MSI_GetRange() :
1941 LL_RCC_MSI_GetRangeAfterStandby()));
1942 break;
1943
1944 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
1945 pllinputfreq = HSI_VALUE;
1946 break;
1947
1948 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
1949 pllinputfreq = HSE_VALUE;
1950 break;
1951
1952 default:
1953 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1954 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1955 LL_RCC_MSI_GetRange() :
1956 LL_RCC_MSI_GetRangeAfterStandby()));
1957 break;
1958 }
1959 return __LL_RCC_CALC_PLLSAI2_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1960 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
1961 }
1962 #endif /* LTDC */
1963
1964 #endif /*RCC_PLLSAI2_SUPPORT*/
1965
1966 /**
1967 * @}
1968 */
1969
1970 /**
1971 * @}
1972 */
1973
1974 #endif /* defined(RCC) */
1975
1976 /**
1977 * @}
1978 */
1979
1980 #endif /* USE_FULL_LL_DRIVER */
1981
1982 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1983