1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_utils.c
4 * @author MCD Application Team
5 * @brief UTILS LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32l4xx_ll_utils.h"
21 #include "stm32l4xx_ll_rcc.h"
22 #include "stm32l4xx_ll_system.h"
23 #include "stm32l4xx_ll_pwr.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 /** @addtogroup UTILS_LL
35 * @{
36 */
37
38 /* Private types -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /* Private constants ---------------------------------------------------------*/
41 /** @addtogroup UTILS_LL_Private_Constants
42 * @{
43 */
44 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
45 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
46 #define UTILS_MAX_FREQUENCY_SCALE1 120000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
47 #define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
48 #else
49 #define UTILS_MAX_FREQUENCY_SCALE1 80000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
50 #define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
51 #endif
52
53 /* Defines used for PLL range */
54 #define UTILS_PLLVCO_INPUT_MIN 4000000U /*!< Frequency min for PLLVCO input, in Hz */
55 #define UTILS_PLLVCO_INPUT_MAX 16000000U /*!< Frequency max for PLLVCO input, in Hz */
56 #define UTILS_PLLVCO_OUTPUT_MIN 64000000U /*!< Frequency min for PLLVCO output, in Hz */
57 #define UTILS_PLLVCO_OUTPUT_MAX 344000000U /*!< Frequency max for PLLVCO output, in Hz */
58
59 /* Defines used for HSE range */
60 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
61 #define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */
62
63 /* Defines used for FLASH latency according to HCLK Frequency */
64 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
65 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
66 #define UTILS_SCALE1_LATENCY1_FREQ 20000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
67 #define UTILS_SCALE1_LATENCY2_FREQ 40000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
68 #define UTILS_SCALE1_LATENCY3_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
69 #define UTILS_SCALE1_LATENCY4_FREQ 80000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
70 #define UTILS_SCALE1_LATENCY5_FREQ 100000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
71 #define UTILS_SCALE2_LATENCY1_FREQ 8000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
72 #define UTILS_SCALE2_LATENCY2_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
73 #else
74 #define UTILS_SCALE1_LATENCY1_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
75 #define UTILS_SCALE1_LATENCY2_FREQ 32000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
76 #define UTILS_SCALE1_LATENCY3_FREQ 48000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
77 #define UTILS_SCALE1_LATENCY4_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
78 #define UTILS_SCALE2_LATENCY1_FREQ 6000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
79 #define UTILS_SCALE2_LATENCY2_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
80 #define UTILS_SCALE2_LATENCY3_FREQ 18000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
81 #endif
82 /**
83 * @}
84 */
85
86 /* Private macros ------------------------------------------------------------*/
87 /** @addtogroup UTILS_LL_Private_Macros
88 * @{
89 */
90 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
91 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
92 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
93 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
94 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
95 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
96 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
97 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
98 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
99
100 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
101 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
102 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
103 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
104 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
105
106 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
107 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
108 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
109 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
110 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
111
112 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \
113 || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
114 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
115 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
116 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
117 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
118 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
119 || ((__VALUE__) == LL_RCC_PLLM_DIV_8))
120
121 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
122
123 #define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \
124 || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
125 || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
126 || ((__VALUE__) == LL_RCC_PLLR_DIV_8))
127
128 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
129
130 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
131
132 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
133 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
134
135 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
136 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
137
138 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
139 /**
140 * @}
141 */
142 /* Private function prototypes -----------------------------------------------*/
143 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
144 * @{
145 */
146 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
147 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
148 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
149 static ErrorStatus UTILS_PLL_IsBusy(void);
150 /**
151 * @}
152 */
153
154 /* Exported functions --------------------------------------------------------*/
155 /** @addtogroup UTILS_LL_Exported_Functions
156 * @{
157 */
158
159 /** @addtogroup UTILS_LL_EF_DELAY
160 * @{
161 */
162
163 /**
164 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
165 * @note When a RTOS is used, it is recommended to avoid changing the Systick
166 * configuration by calling this function, for a delay use rather osDelay RTOS service.
167 * @param HCLKFrequency HCLK frequency in Hz
168 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
169 * @retval None
170 */
LL_Init1msTick(uint32_t HCLKFrequency)171 void LL_Init1msTick(uint32_t HCLKFrequency)
172 {
173 /* Use frequency provided in argument */
174 LL_InitTick(HCLKFrequency, 1000U);
175 }
176
177 /**
178 * @brief This function provides accurate delay (in milliseconds) based
179 * on SysTick counter flag
180 * @note When a RTOS is used, it is recommended to avoid using blocking delay
181 * and use rather osDelay service.
182 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
183 * will configure Systick to 1ms
184 * @param Delay specifies the delay time length, in milliseconds.
185 * @retval None
186 */
LL_mDelay(uint32_t Delay)187 void LL_mDelay(uint32_t Delay)
188 {
189 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
190 uint32_t tmpDelay = Delay;
191
192 /* Add this code to indicate that local variable is not used */
193 ((void)tmp);
194
195 /* Add a period to guaranty minimum wait */
196 if(tmpDelay < LL_MAX_DELAY)
197 {
198 tmpDelay++;
199 }
200
201 while (tmpDelay != 0U)
202 {
203 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
204 {
205 tmpDelay--;
206 }
207 }
208 }
209
210 /**
211 * @}
212 */
213
214 /** @addtogroup UTILS_EF_SYSTEM
215 * @brief System Configuration functions
216 *
217 @verbatim
218 ===============================================================================
219 ##### System Configuration functions #####
220 ===============================================================================
221 [..]
222 System, AHB and APB buses clocks configuration
223
224 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is
225 120000000 Hz for STM32L4Rx/STM32L4Sx devices and 80000000 Hz for others.
226 @endverbatim
227 @internal
228 Depending on the device voltage range, the maximum frequency should be
229 adapted accordingly:
230
231 (++) Table 1. HCLK clock frequency for STM32L4+ Series devices
232 (++) +--------------------------------------------------------+
233 (++) | Latency | HCLK clock frequency (MHz) |
234 (++) | |--------------------------------------|
235 (++) | | voltage range 1 | voltage range 2 |
236 (++) | | 1.2 V | 1.0 V |
237 (++) |-----------------|-------------------|------------------|
238 (++) |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 |
239 (++) |-----------------|-------------------|------------------|
240 (++) |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 |
241 (++) |-----------------|-------------------|------------------|
242 (++) |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 |
243 (++) |-----------------|-------------------|------------------|
244 (++) |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 |
245 (++) |-----------------|-------------------|------------------|
246 (++) |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 |
247 (++) |-----------------|-------------------|------------------|
248 (++) |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 |
249 (++) +--------------------------------------------------------+
250
251 (++) Table 2. HCLK clock frequency for STM32L4 Series devices
252 (++) +-------------------------------------------------------+
253 (++) | Latency | HCLK clock frequency (MHz) |
254 (++) | |-------------------------------------|
255 (++) | | voltage range 1 | voltage range 2 |
256 (++) | | 1.2 V | 1.0 V |
257 (++) |-----------------|------------------|------------------|
258 (++) |0WS(1 CPU cycles)| 0 < HCLK <= 16 | 0 < HCLK <= 6 |
259 (++) |-----------------|------------------|------------------|
260 (++) |1WS(2 CPU cycles)| 16 < HCLK <= 32 | 6 < HCLK <= 12 |
261 (++) |-----------------|------------------|------------------|
262 (++) |2WS(3 CPU cycles)| 32 < HCLK <= 48 | 12 < HCLK <= 18 |
263 (++) |-----------------|------------------|------------------|
264 (++) |3WS(4 CPU cycles)| 48 < HCLK <= 64 | 18 < HCLK <= 26 |
265 (++) |-----------------|------------------|------------------|
266 (++) |4WS(5 CPU cycles)| 64 < HCLK <= 80 | 18 < HCLK <= 26 |
267 (++) +-------------------------------------------------------+
268
269 @endinternal
270 * @{
271 */
272
273 /**
274 * @brief This function sets directly SystemCoreClock CMSIS variable.
275 * @note Variable can be calculated also through SystemCoreClockUpdate function.
276 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
277 * @retval None
278 */
LL_SetSystemCoreClock(uint32_t HCLKFrequency)279 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
280 {
281 /* HCLK clock frequency */
282 SystemCoreClock = HCLKFrequency;
283 }
284
285 /**
286 * @brief Update number of Flash wait states in line with new frequency and current
287 voltage range.
288 * @param HCLKFrequency HCLK frequency
289 * @retval An ErrorStatus enumeration value:
290 * - SUCCESS: Latency has been modified
291 * - ERROR: Latency cannot be modified
292 */
LL_SetFlashLatency(uint32_t HCLKFrequency)293 ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency)
294 {
295 ErrorStatus status = SUCCESS;
296
297 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
298
299 /* Frequency cannot be equal to 0 or greater than max clock */
300 if ((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE1))
301 {
302 status = ERROR;
303 }
304 else
305 {
306 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
307 {
308 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
309 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
310 if(HCLKFrequency > UTILS_SCALE1_LATENCY5_FREQ)
311 {
312 /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */
313 latency = LL_FLASH_LATENCY_5;
314 }
315 else if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ)
316 {
317 /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */
318 latency = LL_FLASH_LATENCY_4;
319 }
320 else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ)
321 {
322 /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */
323 latency = LL_FLASH_LATENCY_3;
324 }
325 else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)
326 {
327 /* 40 < HCLK <= 20 => 2WS (3 CPU cycles) */
328 latency = LL_FLASH_LATENCY_2;
329 }
330 else
331 {
332 if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
333 {
334 /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */
335 latency = LL_FLASH_LATENCY_1;
336 }
337 /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
338 }
339 #else
340 if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ)
341 {
342 /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */
343 latency = LL_FLASH_LATENCY_4;
344 }
345 else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ)
346 {
347 /* 48 < HCLK <= 64 => 3WS (4 CPU cycles) */
348 latency = LL_FLASH_LATENCY_3;
349 }
350 else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)
351 {
352 /* 32 < HCLK <= 48 => 2WS (3 CPU cycles) */
353 latency = LL_FLASH_LATENCY_2;
354 }
355 else
356 {
357 if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
358 {
359 /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */
360 latency = LL_FLASH_LATENCY_1;
361 }
362 /* else HCLKFrequency <= 16MHz default LL_FLASH_LATENCY_0 0WS */
363 }
364 #endif
365 }
366 else /* SCALE2 */
367 {
368 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
369 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
370 if(HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE2)
371 {
372 /* Unexpected HCLK > 26 */
373 status = ERROR;
374 }
375 else if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ)
376 {
377 /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */
378 latency = LL_FLASH_LATENCY_2;
379 }
380 else
381 {
382 if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ)
383 {
384 /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
385 latency = LL_FLASH_LATENCY_1;
386 }
387 /* else HCLKFrequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */
388 }
389 #else
390 if(HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE2)
391 {
392 /* Unexpected HCLK > 26 */
393 status = ERROR;
394 }
395 else if(HCLKFrequency > UTILS_SCALE2_LATENCY3_FREQ)
396 {
397 /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */
398 latency = LL_FLASH_LATENCY_3;
399 }
400 else if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ)
401 {
402 /* 12 < HCLK <= 18 => 2WS (3 CPU cycles) */
403 latency = LL_FLASH_LATENCY_2;
404 }
405 else
406 {
407 if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ)
408 {
409 /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */
410 latency = LL_FLASH_LATENCY_1;
411 }
412 /* else HCLKFrequency <= 6MHz default LL_FLASH_LATENCY_0 0WS */
413 }
414 #endif
415 }
416
417 LL_FLASH_SetLatency(latency);
418
419 /* Check that the new number of wait states is taken into account to access the Flash
420 memory by reading the FLASH_ACR register */
421 if(LL_FLASH_GetLatency() != latency)
422 {
423 status = ERROR;
424 }
425 }
426 return status;
427 }
428
429 /**
430 * @brief This function configures system clock with MSI as clock source of the PLL
431 * @note The application needs to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
432 * @note Function is based on the following formula:
433 * - PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLR)
434 * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = MSI frequency / PLLM)
435 * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
436 * - PLLR: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLR)
437 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
438 * the configuration information for the PLL.
439 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
440 * the configuration information for the BUS prescalers.
441 * @retval An ErrorStatus enumeration value:
442 * - SUCCESS: Max frequency configuration done
443 * - ERROR: Max frequency configuration not done
444 */
LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)445 ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
446 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
447 {
448 ErrorStatus status = SUCCESS;
449 uint32_t pllfreq, msi_range;
450 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
451 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
452 uint32_t hpre = 0U; /* Set default value */
453 #endif
454
455 /* Check if one of the PLL is enabled */
456 if(UTILS_PLL_IsBusy() == SUCCESS)
457 {
458 /* Get the current MSI range */
459 if(LL_RCC_MSI_IsEnabledRangeSelect() != 0U)
460 {
461 msi_range = LL_RCC_MSI_GetRange();
462 switch (msi_range)
463 {
464 case LL_RCC_MSIRANGE_0: /* MSI = 100 KHz */
465 case LL_RCC_MSIRANGE_1: /* MSI = 200 KHz */
466 case LL_RCC_MSIRANGE_2: /* MSI = 400 KHz */
467 case LL_RCC_MSIRANGE_3: /* MSI = 800 KHz */
468 case LL_RCC_MSIRANGE_4: /* MSI = 1 MHz */
469 case LL_RCC_MSIRANGE_5: /* MSI = 2 MHz */
470 /* PLLVCO input frequency is not in the range from 4 to 16 MHz*/
471 status = ERROR;
472 break;
473
474 case LL_RCC_MSIRANGE_6: /* MSI = 4 MHz */
475 case LL_RCC_MSIRANGE_7: /* MSI = 8 MHz */
476 case LL_RCC_MSIRANGE_8: /* MSI = 16 MHz */
477 case LL_RCC_MSIRANGE_9: /* MSI = 24 MHz */
478 case LL_RCC_MSIRANGE_10: /* MSI = 32 MHz */
479 case LL_RCC_MSIRANGE_11: /* MSI = 48 MHz */
480 default:
481 break;
482 }
483 }
484 else
485 {
486 msi_range = LL_RCC_MSI_GetRangeAfterStandby();
487 switch (msi_range)
488 {
489 case LL_RCC_MSISRANGE_4: /* MSI = 1 MHz */
490 case LL_RCC_MSISRANGE_5: /* MSI = 2 MHz */
491 /* PLLVCO input frequency is not in the range from 4 to 16 MHz*/
492 status = ERROR;
493 break;
494
495 case LL_RCC_MSISRANGE_7: /* MSI = 8 MHz */
496 case LL_RCC_MSISRANGE_6: /* MSI = 4 MHz */
497 default:
498 break;
499 }
500 }
501
502 /* Main PLL configuration and activation */
503 if(status != ERROR)
504 {
505 /* Calculate the new PLL output frequency */
506 pllfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), msi_range),
507 UTILS_PLLInitStruct);
508
509 /* Enable MSI if not enabled */
510 if(LL_RCC_MSI_IsReady() != 1U)
511 {
512 LL_RCC_MSI_Enable();
513 while ((LL_RCC_MSI_IsReady() != 1U))
514 {
515 /* Wait for MSI ready */
516 }
517 }
518
519 /* Configure PLL */
520 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
521 UTILS_PLLInitStruct->PLLR);
522
523 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
524 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
525 /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
526 if(pllfreq > 80000000U)
527 {
528 if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
529 {
530 UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
531 hpre = LL_RCC_SYSCLK_DIV_2;
532 }
533 }
534 #endif
535 /* Enable PLL and switch system clock to PLL */
536 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
537
538 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
539 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
540 /* Apply definitive AHB prescaler value if necessary */
541 if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
542 {
543 /* Set FLASH latency to highest latency */
544 status = LL_SetFlashLatency(pllfreq);
545 if(status == SUCCESS)
546 {
547 UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
548 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
549 LL_SetSystemCoreClock(pllfreq);
550 }
551 }
552 #endif
553 }
554 }
555 else
556 {
557 /* Current PLL configuration cannot be modified */
558 status = ERROR;
559 }
560
561 return status;
562 }
563
564 /**
565 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
566 * @note The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
567 * @note Function is based on the following formula:
568 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
569 * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
570 * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
571 * - PLLR: ensure that max frequency at 120000000 Hz is reach (PLLVCO_output / PLLR)
572 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
573 * the configuration information for the PLL.
574 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
575 * the configuration information for the BUS prescalers.
576 * @retval An ErrorStatus enumeration value:
577 * - SUCCESS: Max frequency configuration done
578 * - ERROR: Max frequency configuration not done
579 */
LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)580 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
581 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
582 {
583 ErrorStatus status;
584 uint32_t pllfreq;
585 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
586 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
587 uint32_t hpre = LL_RCC_SYSCLK_DIV_1; /* Set default value */
588 #endif
589
590 /* Check if one of the PLL is enabled */
591 if(UTILS_PLL_IsBusy() == SUCCESS)
592 {
593 /* Calculate the new PLL output frequency */
594 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
595
596 /* Enable HSI if not enabled */
597 if(LL_RCC_HSI_IsReady() != 1U)
598 {
599 LL_RCC_HSI_Enable();
600 while (LL_RCC_HSI_IsReady() != 1U)
601 {
602 /* Wait for HSI ready */
603 }
604 }
605
606 /* Configure PLL */
607 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
608 UTILS_PLLInitStruct->PLLR);
609
610 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
611 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
612 /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
613 if(pllfreq > 80000000U)
614 {
615 if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
616 {
617 UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
618 hpre = LL_RCC_SYSCLK_DIV_2;
619 }
620 }
621 #endif
622 /* Enable PLL and switch system clock to PLL */
623 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
624
625 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
626 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
627 /* Apply definitive AHB prescaler value if necessary */
628 if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
629 {
630 /* Set FLASH latency to highest latency */
631 status = LL_SetFlashLatency(pllfreq);
632 if(status == SUCCESS)
633 {
634 UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
635 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
636 LL_SetSystemCoreClock(pllfreq);
637 }
638 }
639 #endif
640 }
641 else
642 {
643 /* Current PLL configuration cannot be modified */
644 status = ERROR;
645 }
646
647 return status;
648 }
649
650 /**
651 * @brief This function configures system clock with HSE as clock source of the PLL
652 * @note The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
653 * @note Function is based on the following formula:
654 * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
655 * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
656 * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
657 * - PLLR: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLR)
658 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
659 * @param HSEBypass This parameter can be one of the following values:
660 * @arg @ref LL_UTILS_HSEBYPASS_ON
661 * @arg @ref LL_UTILS_HSEBYPASS_OFF
662 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
663 * the configuration information for the PLL.
664 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
665 * the configuration information for the BUS prescalers.
666 * @retval An ErrorStatus enumeration value:
667 * - SUCCESS: Max frequency configuration done
668 * - ERROR: Max frequency configuration not done
669 */
LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,uint32_t HSEBypass,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)670 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
671 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
672 {
673 ErrorStatus status;
674 uint32_t pllfreq;
675 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
676 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
677 uint32_t hpre = 0U; /* Set default value */
678 #endif
679
680 /* Check the parameters */
681 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
682 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
683
684 /* Check if one of the PLL is enabled */
685 if(UTILS_PLL_IsBusy() == SUCCESS)
686 {
687 /* Calculate the new PLL output frequency */
688 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
689
690 /* Enable HSE if not enabled */
691 if(LL_RCC_HSE_IsReady() != 1U)
692 {
693 /* Check if need to enable HSE bypass feature or not */
694 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
695 {
696 LL_RCC_HSE_EnableBypass();
697 }
698 else
699 {
700 LL_RCC_HSE_DisableBypass();
701 }
702
703 /* Enable HSE */
704 LL_RCC_HSE_Enable();
705 while (LL_RCC_HSE_IsReady() != 1U)
706 {
707 /* Wait for HSE ready */
708 }
709 }
710
711 /* Configure PLL */
712 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
713 UTILS_PLLInitStruct->PLLR);
714
715 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
716 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
717 /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
718 if(pllfreq > 80000000U)
719 {
720 if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
721 {
722 UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
723 hpre = LL_RCC_SYSCLK_DIV_2;
724 }
725 }
726 #endif
727 /* Enable PLL and switch system clock to PLL */
728 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
729
730 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
731 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
732 /* Apply definitive AHB prescaler value if necessary */
733 if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
734 {
735 /* Set FLASH latency to highest latency */
736 status = LL_SetFlashLatency(pllfreq);
737 if(status == SUCCESS)
738 {
739 UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
740 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
741 LL_SetSystemCoreClock(pllfreq);
742 }
743 }
744 #endif
745 }
746 else
747 {
748 /* Current PLL configuration cannot be modified */
749 status = ERROR;
750 }
751
752 return status;
753 }
754
755 /**
756 * @}
757 */
758
759 /**
760 * @}
761 */
762
763 /** @addtogroup UTILS_LL_Private_Functions
764 * @{
765 */
766 /**
767 * @brief Function to check that PLL can be modified
768 * @param PLL_InputFrequency PLL input frequency (in Hz)
769 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
770 * the configuration information for the PLL.
771 * @retval PLL output frequency (in Hz)
772 */
UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct)773 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
774 {
775 uint32_t pllfreq;
776
777 /* Check the parameters */
778 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
779 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
780 assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
781
782 /* Check different PLL parameters according to RM */
783 /* - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz. */
784 pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U));
785 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
786
787 /* - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/
788 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
789 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
790
791 /* - PLLR: ensure that max frequency at 120000000 Hz is reached */
792 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U);
793 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
794
795 return pllfreq;
796 }
797
798 /**
799 * @brief Function to check that PLL can be modified
800 * @retval An ErrorStatus enumeration value:
801 * - SUCCESS: PLL modification can be done
802 * - ERROR: PLL is busy
803 */
UTILS_PLL_IsBusy(void)804 static ErrorStatus UTILS_PLL_IsBusy(void)
805 {
806 ErrorStatus status = SUCCESS;
807
808 /* Check if PLL is busy*/
809 if(LL_RCC_PLL_IsReady() != 0U)
810 {
811 /* PLL configuration cannot be modified */
812 status = ERROR;
813 }
814
815 #if defined(RCC_PLLSAI1_SUPPORT)
816 /* Check if PLLSAI1 is busy*/
817 if(LL_RCC_PLLSAI1_IsReady() != 0U)
818 {
819 /* PLLSAI1 configuration cannot be modified */
820 status = ERROR;
821 }
822 #endif /*RCC_PLLSAI1_SUPPORT*/
823 #if defined(RCC_PLLSAI2_SUPPORT)
824
825 /* Check if PLLSAI2 is busy*/
826 if(LL_RCC_PLLSAI2_IsReady() != 0U)
827 {
828 /* PLLSAI2 configuration cannot be modified */
829 status = ERROR;
830 }
831 #endif /*RCC_PLLSAI2_SUPPORT*/
832
833 return status;
834 }
835
836 /**
837 * @brief Function to enable PLL and switch system clock to PLL
838 * @param SYSCLK_Frequency SYSCLK frequency
839 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
840 * the configuration information for the BUS prescalers.
841 * @retval An ErrorStatus enumeration value:
842 * - SUCCESS: No problem to switch system to PLL
843 * - ERROR: Problem to switch system to PLL
844 */
UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)845 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
846 {
847 ErrorStatus status = SUCCESS;
848 uint32_t hclk_frequency;
849
850 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
851 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
852 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
853
854 /* Calculate HCLK frequency */
855 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
856
857 /* Increasing the number of wait states because of higher CPU frequency */
858 if(SystemCoreClock < hclk_frequency)
859 {
860 /* Set FLASH latency to highest latency */
861 status = LL_SetFlashLatency(hclk_frequency);
862 }
863
864 /* Update system clock configuration */
865 if(status == SUCCESS)
866 {
867 /* Enable PLL */
868 LL_RCC_PLL_Enable();
869 LL_RCC_PLL_EnableDomain_SYS();
870 while (LL_RCC_PLL_IsReady() != 1U)
871 {
872 /* Wait for PLL ready */
873 }
874
875 /* Sysclk activation on the main PLL */
876 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
877 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
878 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
879 {
880 /* Wait for system clock switch to PLL */
881 }
882
883 /* Set APB1 & APB2 prescaler*/
884 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
885 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
886 }
887
888 /* Decreasing the number of wait states because of lower CPU frequency */
889 if(SystemCoreClock > hclk_frequency)
890 {
891 /* Set FLASH latency to lowest latency */
892 status = LL_SetFlashLatency(hclk_frequency);
893 }
894
895 /* Update SystemCoreClock variable */
896 if(status == SUCCESS)
897 {
898 LL_SetSystemCoreClock(hclk_frequency);
899 }
900
901 return status;
902 }
903
904 /**
905 * @}
906 */
907
908 /**
909 * @}
910 */
911
912 /**
913 * @}
914 */
915
916 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
917