| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth()
798 bool LanaiInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset()
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| /aosp_15_r20/external/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 751 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, in getMemOpBaseRegImmOfsWidth()
788 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, in getMemOpBaseRegImmOfs()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 754 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth()
795 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 661 GLoadStore &LdSt = cast<GLoadStore>(I); in select() local
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| /aosp_15_r20/external/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 1538 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, in getMemOpBaseRegImmOfs()
1573 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, in getMemOpBaseRegImmOfsWidth()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 563 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2851 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth()
2862 static bool isLdStSafeToCluster(const MachineInstr &LdSt, in isLdStSafeToCluster()
5641 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 1981 bool AArch64InstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset()
1993 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 2583 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth()
2617 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 1755 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth()
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 205 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, in getMemOpBaseRegImmOfs()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 4260 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth()
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| /aosp_15_r20/external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 2942 bool HexagonInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt, in getMemOpBaseRegImmOfs()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 2944 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffset()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 3041 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth()
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| /aosp_15_r20/external/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1133 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op); in SelectAddrMode6Offset() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1044 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op); in SelectAddrMode6Offset() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1086 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op); in SelectAddrMode6Offset() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2813 GLoadStore &LdSt = cast<GLoadStore>(I); in select() local
|
| /aosp_15_r20/external/swiftshader/third_party/subzero/src/ |
| H A D | IceTargetLoweringMIPS32.cpp | 5301 const Inst *LdSt, in formAddressingMode()
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| H A D | IceTargetLoweringARM32.cpp | 5564 const Inst *LdSt, in formAddressingMode()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 261 bool SIInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 295 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1384 if (auto *LdSt = dyn_cast<GLoadStore>(&UseMI)) { in matchPtrAddImmedChain() local
|