| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 452 SDValue LoHalf(SDValue V, SelectionDAG &DAG) const { in LoHalf() function
|
| H A D | HexagonISelDAGToDAGHVX.cpp | 652 LoHalf = 0x20000000, enumerator
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 5322 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0); in splitScalar64BitUnaryOp() local
5388 MachineInstr *LoHalf = in splitScalar64BitAddSub() local
5460 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp() local
|
| H A D | SILoadStoreOptimizer.cpp | 1613 MachineInstr *LoHalf = in computeBase() local
|
| H A D | SIISelLowering.cpp | 4824 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, in lowerINSERT_VECTOR_ELT() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 6862 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0); in splitScalar64BitUnaryOp() local
6933 MachineInstr *LoHalf = in splitScalar64BitAddSub() local
7008 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp() local
|
| H A D | SILoadStoreOptimizer.cpp | 1945 MachineInstr *LoHalf = in computeBase() local
|
| H A D | SIISelLowering.cpp | 4125 MachineInstr *LoHalf = BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0) in EmitInstrWithCustomInserter() local
5750 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, in lowerINSERT_VECTOR_ELT() local
|
| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 2784 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 647 LoHalf = 0x20000000, enumerator
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 4853 Register LoHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_D() local
|