| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 761 Register LoReg = LoOperand.getReg(); in emitCombineIR() local
860 Register LoReg = LoOperand.getReg(); in emitCombineRR() local
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| H A D | HexagonFrameLowering.cpp | 977 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo); in insertCFIInstructionsAt() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 756 Register LoReg = LoOperand.getReg(); in emitCombineIR() local
855 Register LoReg = LoOperand.getReg(); in emitCombineRR() local
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| H A D | HexagonFrameLowering.cpp | 1127 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo); in insertCFIInstructionsAt() local
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| /aosp_15_r20/external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 734 unsigned LoReg = LoOperand.getReg(); in emitCombineIR() local
833 unsigned LoReg = LoOperand.getReg(); in emitCombineRR() local
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| H A D | HexagonFrameLowering.cpp | 827 unsigned LoReg = HRI.getSubReg(Reg, Hexagon::subreg_loreg); in insertCFIInstructionsAt() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 268 unsigned &LoReg, in splitReg()
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| /aosp_15_r20/external/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2137 unsigned LoReg; in Select() local
2184 unsigned SrcReg, LoReg, HiReg; in Select() local
2341 unsigned LoReg, HiReg, ClrReg; in Select() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 305 void AVRRegisterInfo::splitReg(Register Reg, Register &LoReg, in splitReg()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 2185 Register LoReg = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() local
2482 Register LoReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local
2537 Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local
2574 Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FABS() local
2846 Register LoReg = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() local
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| H A D | SILoadStoreOptimizer.cpp | 185 Register LoReg; member
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1135 Register LoReg = MI.getOperand(0).getReg(); in emitReadCycleWidePseudo() local
1171 Register LoReg = MI.getOperand(0).getReg(); in emitSplitF64Pseudo() local
1204 Register LoReg = MI.getOperand(1).getReg(); in emitBuildPairF64Pseudo() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 814 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| H A D | MipsSEFrameLowering.cpp | 308 Register LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local
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| /aosp_15_r20/external/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 651 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| H A D | MipsSEFrameLowering.cpp | 284 unsigned LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1975 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves() local
1995 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; in CMSEPushCalleeSaves() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 828 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| H A D | MipsSEFrameLowering.cpp | 308 Register LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4696 unsigned LoReg, ROpc, MOpc; in Select() local
4790 unsigned SrcReg, LoReg, HiReg; in Select() local
4885 unsigned LoReg, HiReg, ClrReg; in Select() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1464 Register LoReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local
1675 Register LoReg = MRI->createVirtualRegister(&RegRC); in selectG_PTR_MASK() local
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| H A D | SILoadStoreOptimizer.cpp | 186 unsigned LoReg = 0; member
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5162 unsigned LoReg, ROpc, MOpc; in Select() local
5241 unsigned LoReg, HiReg; in Select() local
5380 unsigned LoReg, HiReg, ClrReg; in Select() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1284 Register LoReg = VA.getLocReg() + 1; in LowerCall_64() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 11060 Register LoReg = MI.getOperand(0).getReg(); in emitReadCycleWidePseudo() local
11096 Register LoReg = MI.getOperand(0).getReg(); in emitSplitF64Pseudo() local
11131 Register LoReg = MI.getOperand(1).getReg(); in emitBuildPairF64Pseudo() local
|