1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _DENVERTON_NS_SMBUS_H_ 4 #define _DENVERTON_NS_SMBUS_H_ 5 6 /* PCI Configuration Space (D31:F4): SMBus */ 7 #define SMB_BASE 0x20 8 #define HOSTC 0x40 9 #define HST_EN (1 << 0) 10 #define HOSTC_SMI_EN (1 << 1) 11 #define HOSTC_I2C_EN (1 << 2) 12 13 /* SMBUS TCO base address. */ 14 #define TCOBASE 0x50 15 #define MASK_TCOBASE 0xffe0 16 #define TCOCTL 0x54 17 #define TCOBASE_EN (1 << 8) 18 #define TCOBASE_LOCK (1 << 0) 19 20 #define SMBUS_SLAVE_ADDR 0x44 21 22 /* 23 * SMBus Private Config Registers (PID:SMB) 24 */ 25 #define PCR_SMBUS_TCOCFG 0x00 /* TCO Configuration register */ 26 #define PCR_SMBUS_TCOCFG_IE (1 << 7) /* TCO IRQ Enable */ 27 #define PCR_SMBUS_TCOCFG_IS 7 /* TCO IRQ Select */ 28 #define PCR_SMBUS_TCOCFG_IRQ_9 0x00 29 #define PCR_SMBUS_TCOCFG_IRQ_10 0x01 30 #define PCR_SMBUS_TCOCFG_IRQ_11 0x02 31 #define PCR_SMBUS_TCOCFG_IRQ_20 0x04 /* only if APIC enabled */ 32 #define PCR_SMBUS_TCOCFG_IRQ_21 0x05 /* only if APIC enabled */ 33 #define PCR_SMBUS_TCOCFG_IRQ_22 0x06 /* only if APIC enabled */ 34 #define PCR_SMBUS_TCOCFG_IRQ_23 0x07 /* only if APIC enabled */ 35 #define PCR_SMBUS_SMBTM 0x04 /* SMBus Test Mode */ 36 #define PCR_SMBUS_SMBTM_SMBCT (1 << 1) /* SMBus Counter */ 37 #define PCR_SMBUS_SMBTM_SMBDG (1 << 0) /* SMBus Deglitch */ 38 #define PCR_SMBUS_SCTM 0x08 /* Short Counter Test Mode */ 39 #define PCR_SMBUS_SCTM_SSU (1 << 31) /* Simulation Speed-Up */ 40 #define PCR_SMBUS_GC 0x0C /* General Control */ 41 #define PCR_SMBUS_GC_FD (1 << 0) /* Function Disable */ 42 #define PCR_SMBUS_GC_NR (1 << 1) /* No Reboot */ 43 #define PCR_SMBUS_GC_SMBSCGE (1 << 2) /* SMB Static Clock Gating Enable */ 44 #define PCR_SMBUS_PCE 0x10 /* Power Control Enable */ 45 #define PCR_SMBUS_PCE_HAE (1 << 5) /* Hardware Autonomous Enable */ 46 47 #endif /* _DENVERTON_NS_SMBUS_H_ */ 48