1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _DENVERTON_NS_SYSTEMAGENT_H_ 4 #define _DENVERTON_NS_SYSTEMAGENT_H_ 5 6 #include <soc/iomap.h> 7 8 /* Device 0:0.0 PCI configuration space (Host Bridge) */ 9 #define PCH_SA_DEV PCI_DEV(0, SA_DEV, SA_FUNC) 10 11 #define MCHBAR 0x48 /* MCH space. */ 12 #define PCIEXBAR 0x60 /* PCI express space. */ 13 #define MASK_PCIEXBAR_256M 0xF0000000 14 #define MASK_PCIEXBAR_128M 0xF8000000 15 #define MASK_PCIEXBAR_64M 0xFC000000 16 #define MASK_PCIEXBAR_LENGTH 0x6 17 #define SHIFT_PCIEXBAR_LENGTH 0x1 18 #define MASK_PCIEXBAR_LENGTH_256M (0x0 << SHIFT_PCIEXBAR_LENGTH) 19 #define MASK_PCIEXBAR_LENGTH_128M (0x1 << SHIFT_PCIEXBAR_LENGTH) 20 #define MASK_PCIEXBAR_LENGTH_64M (0x2 << SHIFT_PCIEXBAR_LENGTH) 21 22 #define TOUUD_LO 0xa8 /* Top of Upper Usable DRAM - Low */ 23 #define MASK_TOUUD_LO 0xFFF00000 24 #define TOUUD_HI 0xac /* Top of Upper Usable DRAM - High */ 25 #define MASK_TOUUD_HI 0x0000007F 26 #define TOUUD TOUUD_LO /* Top of Upper Usable DRAM */ 27 #define MASK_TOUUD 0x7FFFF00000 28 29 #define TSEGMB 0xb8 /* TSEG base */ 30 #define MASK_TSEGMB 0xFFF00000 31 #define TOLUD 0xbc /* Top of Low Used Memory */ 32 #define MASK_TOLUD 0xFFF00000 33 34 #define CAPID0_A 0xe4 35 #define VTD_DISABLE (1 << 23) 36 37 /* SideBand B-UNIT */ 38 #define B_UNIT 3 39 40 /* SideBand C-UNIT */ 41 #define C_UNIT 8 42 43 /* SideBand D-UNIT */ 44 #define D_UNIT 1 45 46 /* SideBand P-UNIT */ 47 #define P_UNIT 4 48 49 /* 50 * MCHBAR 51 */ 52 #define MCH_BASE_SIZE 0x8000 53 #define MCH_BMISC 0x6800 54 #define MCH_BMISC_SBVDRAM \ 55 0x08 /* Bit 3: 1 - reads targeting boot vector are routed to DRAM. */ 56 #define MCH_BMISC_ABSEGINDRAM \ 57 0x04 /* Bit 2: 1 - reads targeting A/B-segment are routed to DRAM. */ 58 #define MCH_BMISC_RFSDRAM \ 59 0x02 /* Bit 1: 1 - reads targeting E-segment are routed to DRAM. */ 60 #define MCH_BMISC_RESDRAM \ 61 0x01 /* Bit 0: 1 - reads targeting E-segment are routed to DRAM. */ 62 63 #define MCH_VTBAR_OFFSET 0x6c80 64 #define MCH_VTBAR_ENABLE_MASK 0x1 65 #define MCH_VTBAR_MASK 0x7ffffff000 66 67 #define MCH_BAR_BIOS_RESET_CPL 0x7078 68 #define RST_CPL_BIT (1 << 0) 69 #define PCODE_INIT_DONE (1 << 8) 70 #define MCH_BAR_CORE_EXISTS_MASK 0x7164 71 #define MCH_BAR_CORE_DISABLE_MASK 0x7168 72 73 /* Device 0:4.0 PCI configuration space (RAS) */ 74 75 /* Device 0:5.0 PCI configuration space (RCEC) */ 76 77 /* Top of 32bit usable memory */ 78 u32 top_of_32bit_ram(void); 79 80 #endif //_DENVERTON_NS_SYSTEMAGENT_H_ 81