1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ 4 #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ 5 6 /* 7 * D1:F0 PEG 8 */ 9 #define PEG_CAP 0xa2 10 #define SLOTCAP 0xb4 11 #define PEGLC 0xec 12 #define D1F0_VCCAP 0x104 13 #define D1F0_VC0RCTL 0x114 14 15 /* Chipset types */ 16 #define IRONLAKE_MOBILE 0 17 #define IRONLAKE_DESKTOP 1 18 #define IRONLAKE_SERVER 2 19 20 #include "memmap.h" 21 22 #define QUICKPATH_BUS (CONFIG_ECAM_MMCONF_BUS_NUMBER - 1) 23 24 #include <southbridge/intel/ibexpeak/pch.h> 25 26 /* Everything below this line is ignored in the DSDT */ 27 #ifndef __ACPI__ 28 29 /* Device 0:0.0 PCI configuration space (Host Bridge) */ 30 31 #include "registers/host_bridge.h" 32 33 /* 34 * Generic Non-Core Registers 35 */ 36 #define QPI_NON_CORE PCI_DEV(QUICKPATH_BUS, 0, 0) 37 38 #define MAX_RTIDS 0x60 39 #define DESIRED_CORES 0x80 40 #define MIRROR_PORT_CTL 0xd0 41 42 /* 43 * SAD - System Address Decoder 44 */ 45 #define QPI_SAD PCI_DEV(QUICKPATH_BUS, 0, 1) 46 47 #define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ 48 #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */ 49 50 #define SAD_PCIEXBAR 0x50 51 52 #define SAD_DRAM_RULE(x) (0x80 + 4 * (x)) /* 0-7 */ 53 #define SAD_INTERLEAVE_LIST(x) (0xc0 + 4 * (x)) /* 0-7 */ 54 55 /* 56 * QPI Link 0 57 */ 58 #define QPI_LINK_0 PCI_DEV(QUICKPATH_BUS, 2, 0) 59 60 #define QPI_QPILCP 0x40 /* QPI Link Capability */ 61 #define QPI_QPILCL 0x48 /* QPI Link Control */ 62 #define QPI_QPILS 0x50 /* QPI Link Status */ 63 #define QPI_DEF_RMT_VN_CREDITS 0x58 /* Default Available Remote Credits */ 64 65 /* 66 * QPI Physical Layer 0 67 */ 68 #define QPI_PHY_0 PCI_DEV(QUICKPATH_BUS, 2, 1) 69 70 #define QPI_PLL_STATUS 0x50 71 #define QPI_PLL_RATIO 0x54 72 #define QPI_PHY_CAPABILITY 0x68 /* QPI Phys. Layer Capability */ 73 #define QPI_PHY_CONTROL 0x6c /* QPI Phys. Layer Control */ 74 #define QPI_PHY_INIT_STATUS 0x80 /* QPI Phys. Layer Initialization Status */ 75 #define QPI_PHY_PRIM_TIMEOUT 0x94 /* QPI Phys. Layer Primary Timeout Value */ 76 #define QPI_PHY_PWR_MGMT 0xd0 /* QPI Phys. Layer Power Management */ 77 #define QPI_PHY_EP_SELECT 0xe0 /* QPI Phys. Layer Electrical Parameter Select */ 78 #define QPI_PHY_EP_MCTR 0xf4 /* QPI Phys. Layer Electrical Parameter Misc. Control */ 79 80 81 /* Device 0:2.0 PCI configuration space (Graphics Device) */ 82 83 #define MSAC 0x62 /* Multi Size Aperture Control */ 84 85 /* 86 * MCHBAR 87 */ 88 89 #include <northbridge/intel/common/fixed_bars.h> 90 91 /* 92 * EPBAR - Egress Port Root Complex Register Block 93 */ 94 95 #include "registers/epbar.h" 96 97 /* 98 * DMIBAR 99 */ 100 101 #include "registers/dmibar.h" 102 103 #ifndef __ASSEMBLER__ 104 105 void intel_ironlake_finalize_smm(void); 106 107 int bridge_silicon_revision(void); 108 void ironlake_early_initialization(int chipset_type); 109 void ironlake_late_initialization(void); 110 void mainboard_pre_raminit(void); 111 void mainboard_get_spd_map(u8 *spd_addrmap); 112 113 #endif 114 #endif 115 #endif /* __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ */ 116