1 /* 2 * Copyright (c) 2011-2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file codechal_encode_avc_g8.h 24 //! \brief This file defines the C++ class/interface for Gen8 platform's AVC 25 //! DualPipe encoding to be used across CODECHAL components. 26 //! 27 28 #ifndef __CODECHAL_ENCODE_AVC_G8_H__ 29 #define __CODECHAL_ENCODE_AVC_G8_H__ 30 31 #include "codechal_encode_avc.h" 32 33 typedef enum _WP_BINDING_TABLE_OFFSET 34 { 35 WP_INPUT_REF_SURFACE = 0, 36 WP_OUTPUT_SCALED_SURFACE = 1, 37 WP_NUM_SURFACES = 2 38 } WP_BINDING_TABLE_OFFSET; 39 40 typedef enum _ME_BINDING_TABLE_OFFSET_CM 41 { 42 ME_MV_DATA_SURFACE_CM = 0, 43 ME_16x_MV_DATA_SURFACE_CM = 1, 44 ME_32x_MV_DATA_SURFACE_CM = 1, 45 ME_DISTORTION_SURFACE_CM = 2, 46 ME_BRC_DISTORTION_CM = 3, 47 ME_RESERVED0_CM = 4, 48 ME_CURR_FOR_FWD_REF_CM = 5, 49 ME_FWD_REF_IDX0_CM = 6, 50 ME_RESERVED1_CM = 7, 51 ME_FWD_REF_IDX1_CM = 8, 52 ME_RESERVED2_CM = 9, 53 ME_FWD_REF_IDX2_CM = 10, 54 ME_RESERVED3_CM = 11, 55 ME_FWD_REF_IDX3_CM = 12, 56 ME_RESERVED4_CM = 13, 57 ME_FWD_REF_IDX4_CM = 14, 58 ME_RESERVED5_CM = 15, 59 ME_FWD_REF_IDX5_CM = 16, 60 ME_RESERVED6_CM = 17, 61 ME_FWD_REF_IDX6_CM = 18, 62 ME_RESERVED7_CM = 19, 63 ME_FWD_REF_IDX7_CM = 20, 64 ME_RESERVED8_CM = 21, 65 ME_CURR_FOR_BWD_REF_CM = 22, 66 ME_BWD_REF_IDX0_CM = 23, 67 ME_RESERVED9_CM = 24, 68 ME_BWD_REF_IDX1_CM = 25, 69 ME_RESERVED10_CM = 26, 70 ME_NUM_SURFACES_CM = 27 71 } ME_DING_TABLE_OFFSET_CM; 72 73 typedef enum _BINDING_TABLE_OFFSET_MBENC_CM 74 { 75 MBENC_MFC_AVC_PAK_OBJ_CM = 0, 76 MBENC_IND_MV_DATA_CM = 1, 77 MBENC_BRC_DISTORTION_CM = 2, // For BRC distortion for I 78 MBENC_CURR_Y_CM = 3, 79 MBENC_CURR_UV_CM = 4, 80 MBENC_MB_SPECIFIC_DATA_CM = 5, 81 MBENC_AUX_VME_OUT_CM = 6, 82 MBENC_REFPICSELECT_L0_CM = 7, 83 MBENC_MV_DATA_FROM_ME_CM = 8, 84 MBENC_4xME_DISTORTION_CM = 9, 85 MBENC_SLICEMAP_DATA_CM = 10, 86 MBENC_FWD_MB_DATA_CM = 11, 87 MBENC_FWD_MV_DATA_CM = 12, 88 MBENC_MBQP_CM = 13, 89 MBENC_MBBRC_CONST_DATA_CM = 14, 90 MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_CM = 15, 91 MBENC_VME_INTER_PRED_FWD_PIC_IDX0_CM = 16, 92 MBENC_VME_INTER_PRED_BWD_PIC_IDX0_0_CM = 17, 93 MBENC_VME_INTER_PRED_FWD_PIC_IDX1_CM = 18, 94 MBENC_VME_INTER_PRED_BWD_PIC_IDX1_0_CM = 19, 95 MBENC_VME_INTER_PRED_FWD_PIC_IDX2_CM = 20, 96 MBENC_RESERVED0_CM = 21, 97 MBENC_VME_INTER_PRED_FWD_PIC_IDX3_CM = 22, 98 MBENC_RESERVED1_CM = 23, 99 MBENC_VME_INTER_PRED_FWD_PIC_IDX4_CM = 24, 100 MBENC_RESERVED2_CM = 25, 101 MBENC_VME_INTER_PRED_FWD_PIC_IDX5_CM = 26, 102 MBENC_RESERVED3_CM = 27, 103 MBENC_VME_INTER_PRED_FWD_PIC_IDX6_CM = 28, 104 MBENC_RESERVED4_CM = 29, 105 MBENC_VME_INTER_PRED_FWD_PIC_IDX7_CM = 30, 106 MBENC_RESERVED5_CM = 31, 107 MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_CM = 32, 108 MBENC_VME_INTER_PRED_BWD_PIC_IDX0_1_CM = 33, 109 MBENC_RESERVED6_CM = 34, 110 MBENC_VME_INTER_PRED_BWD_PIC_IDX1_1_CM = 35, 111 MBENC_RESERVED7_CM = 36, 112 MBENC_FLATNESS_CHECK_CM = 37, 113 MBENC_MAD_DATA_CM = 38, 114 MBENC_FORCE_NONSKIP_MB_MAP_CM = 39, 115 MBENC_ADV_WA_DATA_CM = 40, 116 MBENC_BRC_CURBE_DATA_CM = 41, 117 MBENC_STATIC_FRAME_DETECTION_OUTPUT_CM = 42, 118 MBENC_NUM_SURFACES_CM = 43 119 } BINDING_TABLE_OFFSET_MBENC_CM; 120 121 // AVC Gen 8 WP kernel CURBE 122 typedef struct _WP_CURBE 123 { 124 // DW0 125 union 126 { 127 struct 128 { 129 uint32_t DefaultWeight : MOS_BITFIELD_RANGE( 0,15 ); 130 uint32_t DefaultOffset : MOS_BITFIELD_RANGE( 16,31 ); 131 }; 132 struct 133 { 134 uint32_t Value; 135 }; 136 } DW0; 137 138 // DW1 139 union 140 { 141 struct 142 { 143 uint32_t ROI0_X_left : MOS_BITFIELD_RANGE( 0,15 ); 144 uint32_t ROI0_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 145 }; 146 struct 147 { 148 uint32_t Value; 149 }; 150 } DW1; 151 152 // DW2 153 union 154 { 155 struct 156 { 157 uint32_t ROI0_X_right : MOS_BITFIELD_RANGE( 0,15 ); 158 uint32_t ROI0_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 159 }; 160 struct 161 { 162 uint32_t Value; 163 }; 164 } DW2; 165 166 // DW3 167 union 168 { 169 struct 170 { 171 uint32_t ROI0Weight : MOS_BITFIELD_RANGE( 0,15 ); 172 uint32_t ROI0Offset : MOS_BITFIELD_RANGE( 16,31 ); 173 }; 174 struct 175 { 176 uint32_t Value; 177 }; 178 } DW3; 179 180 // DW4 181 union 182 { 183 struct 184 { 185 uint32_t ROI1_X_left : MOS_BITFIELD_RANGE( 0,15 ); 186 uint32_t ROI1_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 187 }; 188 struct 189 { 190 uint32_t Value; 191 }; 192 } DW4; 193 194 // DW5 195 union 196 { 197 struct 198 { 199 uint32_t ROI1_X_right : MOS_BITFIELD_RANGE( 0,15 ); 200 uint32_t ROI1_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 201 }; 202 struct 203 { 204 uint32_t Value; 205 }; 206 } DW5; 207 208 // DW6 209 union 210 { 211 struct 212 { 213 uint32_t ROI1Weight : MOS_BITFIELD_RANGE( 0,15 ); 214 uint32_t ROI1Offset : MOS_BITFIELD_RANGE( 16,31 ); 215 }; 216 struct 217 { 218 uint32_t Value; 219 }; 220 } DW6; 221 222 // DW7 223 union 224 { 225 struct 226 { 227 uint32_t ROI2_X_left : MOS_BITFIELD_RANGE( 0,15 ); 228 uint32_t ROI2_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 229 }; 230 struct 231 { 232 uint32_t Value; 233 }; 234 } DW7; 235 236 // DW8 237 union 238 { 239 struct 240 { 241 uint32_t ROI2_X_right : MOS_BITFIELD_RANGE( 0,15 ); 242 uint32_t ROI2_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 243 }; 244 struct 245 { 246 uint32_t Value; 247 }; 248 } DW8; 249 250 // DW9 251 union 252 { 253 struct 254 { 255 uint32_t ROI2Weight : MOS_BITFIELD_RANGE( 0,15 ); 256 uint32_t ROI2Offset : MOS_BITFIELD_RANGE( 16,31 ); 257 }; 258 struct 259 { 260 uint32_t Value; 261 }; 262 } DW9; 263 264 // DW10 265 union 266 { 267 struct 268 { 269 uint32_t ROI3_X_left : MOS_BITFIELD_RANGE( 0,15 ); 270 uint32_t ROI3_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 271 }; 272 struct 273 { 274 uint32_t Value; 275 }; 276 } DW10; 277 278 // DW11 279 union 280 { 281 struct 282 { 283 uint32_t ROI3_X_right : MOS_BITFIELD_RANGE( 0,15 ); 284 uint32_t ROI3_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 285 }; 286 struct 287 { 288 uint32_t Value; 289 }; 290 } DW11; 291 292 // DW12 293 union 294 { 295 struct 296 { 297 uint32_t ROI3Weight : MOS_BITFIELD_RANGE( 0,15 ); 298 uint32_t ROI3Offset : MOS_BITFIELD_RANGE( 16,31 ); 299 }; 300 struct 301 { 302 uint32_t Value; 303 }; 304 } DW12; 305 306 // DW13 307 union 308 { 309 struct 310 { 311 uint32_t ROI4_X_left : MOS_BITFIELD_RANGE( 0,15 ); 312 uint32_t ROI4_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 313 }; 314 struct 315 { 316 uint32_t Value; 317 }; 318 } DW13; 319 320 // DW14 321 union 322 { 323 struct 324 { 325 uint32_t ROI4_X_right : MOS_BITFIELD_RANGE( 0,15 ); 326 uint32_t ROI4_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 327 }; 328 struct 329 { 330 uint32_t Value; 331 }; 332 } DW14; 333 334 // DW15 335 union 336 { 337 struct 338 { 339 uint32_t ROI4Weight : MOS_BITFIELD_RANGE( 0,15 ); 340 uint32_t ROI4Offset : MOS_BITFIELD_RANGE( 16,31 ); 341 }; 342 struct 343 { 344 uint32_t Value; 345 }; 346 } DW15; 347 348 // DW16 349 union 350 { 351 struct 352 { 353 uint32_t ROI5_X_left : MOS_BITFIELD_RANGE( 0,15 ); 354 uint32_t ROI5_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 355 }; 356 struct 357 { 358 uint32_t Value; 359 }; 360 } DW16; 361 362 // DW17 363 union 364 { 365 struct 366 { 367 uint32_t ROI5_X_right : MOS_BITFIELD_RANGE( 0,15 ); 368 uint32_t ROI5_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 369 }; 370 struct 371 { 372 uint32_t Value; 373 }; 374 } DW17; 375 376 // DW18 377 union 378 { 379 struct 380 { 381 uint32_t ROI5Weight : MOS_BITFIELD_RANGE( 0,15 ); 382 uint32_t ROI5Offset : MOS_BITFIELD_RANGE( 16,31 ); 383 }; 384 struct 385 { 386 uint32_t Value; 387 }; 388 } DW18; 389 390 // DW19 391 union 392 { 393 struct 394 { 395 uint32_t ROI6_X_left : MOS_BITFIELD_RANGE( 0,15 ); 396 uint32_t ROI6_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 397 }; 398 struct 399 { 400 uint32_t Value; 401 }; 402 } DW19; 403 404 // DW20 405 union 406 { 407 struct 408 { 409 uint32_t ROI6_X_right : MOS_BITFIELD_RANGE( 0,15 ); 410 uint32_t ROI6_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 411 }; 412 struct 413 { 414 uint32_t Value; 415 }; 416 } DW20; 417 418 // DW21 419 union 420 { 421 struct 422 { 423 uint32_t ROI6Weight : MOS_BITFIELD_RANGE( 0,15 ); 424 uint32_t ROI6Offset : MOS_BITFIELD_RANGE( 16,31 ); 425 }; 426 struct 427 { 428 uint32_t Value; 429 }; 430 } DW21; 431 432 // DW22 433 union 434 { 435 struct 436 { 437 uint32_t ROI7_X_left : MOS_BITFIELD_RANGE( 0,15 ); 438 uint32_t ROI7_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 439 }; 440 struct 441 { 442 uint32_t Value; 443 }; 444 } DW22; 445 446 // DW23 447 union 448 { 449 struct 450 { 451 uint32_t ROI7_X_right : MOS_BITFIELD_RANGE( 0,15 ); 452 uint32_t ROI7_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 453 }; 454 struct 455 { 456 uint32_t Value; 457 }; 458 } DW23; 459 460 // DW24 461 union 462 { 463 struct 464 { 465 uint32_t ROI7Weight : MOS_BITFIELD_RANGE( 0,15 ); 466 uint32_t ROI7Offset : MOS_BITFIELD_RANGE( 16,31 ); 467 }; 468 struct 469 { 470 uint32_t Value; 471 }; 472 } DW24; 473 474 // DW25 475 union 476 { 477 struct 478 { 479 uint32_t ROI8_X_left : MOS_BITFIELD_RANGE( 0,15 ); 480 uint32_t ROI8_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 481 }; 482 struct 483 { 484 uint32_t Value; 485 }; 486 } DW25; 487 488 // DW26 489 union 490 { 491 struct 492 { 493 uint32_t ROI8_X_right : MOS_BITFIELD_RANGE( 0,15 ); 494 uint32_t ROI8_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 495 }; 496 struct 497 { 498 uint32_t Value; 499 }; 500 } DW26; 501 502 // DW27 503 union 504 { 505 struct 506 { 507 uint32_t ROI8Weight : MOS_BITFIELD_RANGE( 0,15 ); 508 uint32_t ROI8Offset : MOS_BITFIELD_RANGE( 16,31 ); 509 }; 510 struct 511 { 512 uint32_t Value; 513 }; 514 } DW27; 515 516 // DW28 517 union 518 { 519 struct 520 { 521 uint32_t ROI9_X_left : MOS_BITFIELD_RANGE( 0,15 ); 522 uint32_t ROI9_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 523 }; 524 struct 525 { 526 uint32_t Value; 527 }; 528 } DW28; 529 530 // DW29 531 union 532 { 533 struct 534 { 535 uint32_t ROI9_X_right : MOS_BITFIELD_RANGE( 0,15 ); 536 uint32_t ROI9_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 537 }; 538 struct 539 { 540 uint32_t Value; 541 }; 542 } DW29; 543 544 // DW30 545 union 546 { 547 struct 548 { 549 uint32_t ROI9Weight : MOS_BITFIELD_RANGE( 0,15 ); 550 uint32_t ROI9Offset : MOS_BITFIELD_RANGE( 16,31 ); 551 }; 552 struct 553 { 554 uint32_t Value; 555 }; 556 } DW30; 557 558 // DW31 559 union 560 { 561 struct 562 { 563 uint32_t ROI10_X_left : MOS_BITFIELD_RANGE( 0,15 ); 564 uint32_t ROI10_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 565 }; 566 struct 567 { 568 uint32_t Value; 569 }; 570 } DW31; 571 572 // DW32 573 union 574 { 575 struct 576 { 577 uint32_t ROI10_X_right : MOS_BITFIELD_RANGE( 0,15 ); 578 uint32_t ROI10_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 579 }; 580 struct 581 { 582 uint32_t Value; 583 }; 584 } DW32; 585 586 // DW33 587 union 588 { 589 struct 590 { 591 uint32_t ROI10Weight : MOS_BITFIELD_RANGE( 0,15 ); 592 uint32_t ROI10Offset : MOS_BITFIELD_RANGE( 16,31 ); 593 }; 594 struct 595 { 596 uint32_t Value; 597 }; 598 } DW33; 599 600 // DW34 601 union 602 { 603 struct 604 { 605 uint32_t ROI11_X_left : MOS_BITFIELD_RANGE( 0,15 ); 606 uint32_t ROI11_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 607 }; 608 struct 609 { 610 uint32_t Value; 611 }; 612 } DW34; 613 614 // DW35 615 union 616 { 617 struct 618 { 619 uint32_t ROI11_X_right : MOS_BITFIELD_RANGE( 0,15 ); 620 uint32_t ROI11_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 621 }; 622 struct 623 { 624 uint32_t Value; 625 }; 626 } DW35; 627 628 // DW36 629 union 630 { 631 struct 632 { 633 uint32_t ROI11Weight : MOS_BITFIELD_RANGE( 0,15 ); 634 uint32_t ROI11Offset : MOS_BITFIELD_RANGE( 16,31 ); 635 }; 636 struct 637 { 638 uint32_t Value; 639 }; 640 } DW36; 641 642 // DW37 643 union 644 { 645 struct 646 { 647 uint32_t ROI12_X_left : MOS_BITFIELD_RANGE( 0,15 ); 648 uint32_t ROI12_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 649 }; 650 struct 651 { 652 uint32_t Value; 653 }; 654 } DW37; 655 656 // DW38 657 union 658 { 659 struct 660 { 661 uint32_t ROI12_X_right : MOS_BITFIELD_RANGE( 0,15 ); 662 uint32_t ROI12_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 663 }; 664 struct 665 { 666 uint32_t Value; 667 }; 668 } DW38; 669 670 // DW39 671 union 672 { 673 struct 674 { 675 uint32_t ROI12Weight : MOS_BITFIELD_RANGE( 0,15 ); 676 uint32_t ROI12Offset : MOS_BITFIELD_RANGE( 16,31 ); 677 }; 678 struct 679 { 680 uint32_t Value; 681 }; 682 } DW39; 683 684 // DW40 685 union 686 { 687 struct 688 { 689 uint32_t ROI13_X_left : MOS_BITFIELD_RANGE( 0,15 ); 690 uint32_t ROI13_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 691 }; 692 struct 693 { 694 uint32_t Value; 695 }; 696 } DW40; 697 698 // DW41 699 union 700 { 701 struct 702 { 703 uint32_t ROI13_X_right : MOS_BITFIELD_RANGE( 0,15 ); 704 uint32_t ROI13_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 705 }; 706 struct 707 { 708 uint32_t Value; 709 }; 710 } DW41; 711 712 // DW42 713 union 714 { 715 struct 716 { 717 uint32_t ROI13Weight : MOS_BITFIELD_RANGE( 0,15 ); 718 uint32_t ROI13Offset : MOS_BITFIELD_RANGE( 16,31 ); 719 }; 720 struct 721 { 722 uint32_t Value; 723 }; 724 } DW42; 725 726 // DW43 727 union 728 { 729 struct 730 { 731 uint32_t ROI14_X_left : MOS_BITFIELD_RANGE( 0,15 ); 732 uint32_t ROI14_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 733 }; 734 struct 735 { 736 uint32_t Value; 737 }; 738 } DW43; 739 740 // DW44 741 union 742 { 743 struct 744 { 745 uint32_t ROI14_X_right : MOS_BITFIELD_RANGE( 0,15 ); 746 uint32_t ROI14_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 747 }; 748 struct 749 { 750 uint32_t Value; 751 }; 752 } DW44; 753 754 // DW45 755 union 756 { 757 struct 758 { 759 uint32_t ROI14Weight : MOS_BITFIELD_RANGE( 0,15 ); 760 uint32_t ROI14Offset : MOS_BITFIELD_RANGE( 16,31 ); 761 }; 762 struct 763 { 764 uint32_t Value; 765 }; 766 } DW45; 767 768 // DW46 769 union 770 { 771 struct 772 { 773 uint32_t ROI15_X_left : MOS_BITFIELD_RANGE( 0,15 ); 774 uint32_t ROI15_Y_top : MOS_BITFIELD_RANGE( 16,31 ); 775 }; 776 struct 777 { 778 uint32_t Value; 779 }; 780 } DW46; 781 782 // DW47 783 union 784 { 785 struct 786 { 787 uint32_t ROI15_X_right : MOS_BITFIELD_RANGE( 0,15 ); 788 uint32_t ROI15_Y_bottom : MOS_BITFIELD_RANGE( 16,31 ); 789 }; 790 struct 791 { 792 uint32_t Value; 793 }; 794 } DW47; 795 796 // DW48 797 union 798 { 799 struct 800 { 801 uint32_t ROI15Weight : MOS_BITFIELD_RANGE( 0,15 ); 802 uint32_t ROI15Offset : MOS_BITFIELD_RANGE( 16,31 ); 803 }; 804 struct 805 { 806 uint32_t Value; 807 }; 808 } DW48; 809 810 // DW49 811 union 812 { 813 struct 814 { 815 uint32_t Log2WeightDenom : MOS_BITFIELD_RANGE( 0,2 ); 816 uint32_t reserve1 : MOS_BITFIELD_RANGE( 3,7 ); 817 uint32_t ROI_enabled : MOS_BITFIELD_RANGE( 8,8 ); 818 uint32_t reserve2 : MOS_BITFIELD_RANGE( 9,31 ); 819 }; 820 struct 821 { 822 uint32_t Value; 823 }; 824 } DW49; 825 826 // DW50 827 union 828 { 829 struct 830 { 831 uint32_t InputSurface : MOS_BITFIELD_RANGE( 0,31 ); 832 }; 833 struct 834 { 835 uint32_t Value; 836 }; 837 } DW50; 838 839 // DW51 840 union 841 { 842 struct 843 { 844 uint32_t OutputSurface : MOS_BITFIELD_RANGE( 0,31 ); 845 }; 846 struct 847 { 848 uint32_t Value; 849 }; 850 } DW51; 851 852 } WP_CURBE, *PWP_CURBE; 853 854 C_ASSERT(SIZE32(WP_CURBE) == 52); 855 856 struct CodechalEncodeAvcEncG8 : public CodechalEncodeAvcEnc 857 { 858 static const uint32_t m_mbencNumTargetUsagesCommon = 3; 859 static const uint32_t m_brcConstantSurfaceEarlySkipTableSizeCommon = 128; 860 static const uint32_t m_brcConstantSurfaceRefCostSizeCommon = 128; 861 static const uint32_t m_brcConstantSurfaceModeMvCosttSizeCommon = 1664; 862 863 static const uint32_t m_mbencCurbeSizeInDword = 96; 864 static const uint32_t m_mbencNumTargetUsagesCm = 3; 865 static const uint32_t m_hmeFirstStep = 0; 866 867 static const uint32_t m_hmeFollowingStep = 1; 868 static const uint32_t m_mvShiftFactor32x = 1; 869 static const uint32_t m_mvShiftFactor16x = 2; 870 static const uint32_t m_mvShiftFactor4x = 2; 871 static const uint32_t m_prevMvReadPosition16x = 1; 872 static const uint32_t m_prevMvReadPosition8x = 0; 873 874 // BRC Constant Surface 875 static const uint32_t m_brcConstantSurfaceQpList0 = 32; 876 static const uint32_t m_brcConstantSurfaceQpList0Reserved = 32; 877 static const uint32_t m_brcConstantSurfaceQpList1 = 32; 878 static const uint32_t m_brcConstantSurfaceQpList1Reserved = 160; 879 880 static const uint32_t m_brcConstantSurfaceWidth = 64; 881 static const uint32_t m_brcConstantSurfaceHeight = 44; 882 883 static const uint32_t m_initBrcHistoryBufferSize = 864; 884 static const uint32_t m_brcConstantSurfaceIntraCostScalingFactor = 64; 885 886 static const uint32_t m_sfdOutputBufferSize = 128; 887 888 static const uint32_t m_cabacZone0Threshold = 128; 889 static const uint32_t m_cabacZone1Threshold = 384; 890 static const uint32_t m_cabacZone2Threshold = 768; 891 static const uint32_t m_cabacZone3Threshold = 65535; 892 893 static const uint32_t m_cabacWaZone0IMinQp = 10; 894 static const uint32_t m_cabacWaZone1IMinQp = 12; 895 static const uint32_t m_cabacWaZone2IMinQp = 14; 896 static const uint32_t m_cabacWaZone3IMinQp = 16; 897 898 static const uint32_t m_cabacWaZone0PMinQp = 4; 899 static const uint32_t m_cabacWaZone1PMinQp = 6; 900 static const uint32_t m_cabacWaZone2PMinQp = 8; 901 static const uint32_t m_cabacWaZone3PMinQp = 10; 902 903 static const uint32_t m_initMBEncCurbeCmNormalIFrame[m_mbencCurbeSizeInDword]; 904 static const uint32_t m_initMBEncCurbeCmNormalIField[m_mbencCurbeSizeInDword]; 905 static const uint32_t m_initMBEncCurbeCmNormalPFrame[m_mbencCurbeSizeInDword]; 906 static const uint32_t m_initMBEncCurbeCmNormalPField[m_mbencCurbeSizeInDword]; 907 static const uint32_t m_initMBEncCurbeCmNormalBFrame[m_mbencCurbeSizeInDword]; 908 static const uint32_t m_initMBEncCurbeCmNormalBField[m_mbencCurbeSizeInDword]; 909 static const uint32_t m_initMBEncCurbeCmIFrameDist[m_mbencCurbeSizeInDword]; 910 static const uint32_t m_initMeCurbeCm[39]; 911 static const int32_t m_brcBtCounts[CODECHAL_ENCODE_BRC_IDX_NUM]; 912 static const int32_t m_brcCurbeSize[CODECHAL_ENCODE_BRC_IDX_NUM]; 913 static const uint32_t m_trellisQuantizationRounding[NUM_TARGET_USAGE_MODES]; 914 915 //! 916 //! \brief Constructor 917 //! 918 CodechalEncodeAvcEncG8( 919 CodechalHwInterface * hwInterface, 920 CodechalDebugInterface *debugInterface, 921 PCODECHAL_STANDARD_INFO standardInfo); 922 923 ~CodechalEncodeAvcEncG8(); 924 925 static MOS_STATUS GetKernelHeaderAndSize( 926 void *pvBinary, 927 EncOperation operation, 928 uint32_t krnStateIdx, 929 void *krnHeader, 930 uint32_t *krnSize); 931 932 void UpdateSSDSliceCount(); 933 934 virtual MOS_STATUS InitMbBrcConstantDataBuffer( 935 PCODECHAL_ENCODE_AVC_INIT_MBBRC_CONSTANT_DATA_BUFFER_PARAMS params); 936 937 virtual MOS_STATUS InitializeState(); 938 939 //! 940 //! \brief Init ME kernel state 941 //! 942 //! \return MOS_STATUS 943 //! MOS_STATUS_SUCCESS if success, else fail reason 944 //! 945 virtual MOS_STATUS InitKernelStateMe(); 946 947 virtual MOS_STATUS InitKernelStateMbEnc(); 948 949 virtual MOS_STATUS InitKernelStateWP(); 950 951 virtual MOS_STATUS InitKernelStateBrc(); 952 953 virtual MOS_STATUS GetMbEncKernelStateIdx( 954 CodechalEncodeIdOffsetParams* params, 955 uint32_t* kernelOffset); 956 957 virtual MOS_STATUS InitBrcConstantBuffer(PCODECHAL_ENCODE_AVC_INIT_BRC_CONSTANT_BUFFER_PARAMS params); 958 959 virtual MOS_STATUS GetTrellisQuantization( 960 PCODECHAL_ENCODE_AVC_TQ_INPUT_PARAMS params, 961 PCODECHAL_ENCODE_AVC_TQ_PARAMS trellisQuantParams); 962 963 virtual MOS_STATUS SetCurbeAvcWP( 964 PCODECHAL_ENCODE_AVC_WP_CURBE_PARAMS params); 965 966 virtual MOS_STATUS SetCurbeAvcMbEnc( 967 PCODECHAL_ENCODE_AVC_MBENC_CURBE_PARAMS params); 968 969 virtual MOS_STATUS SetCurbeAvcBrcInitReset( 970 PCODECHAL_ENCODE_AVC_BRC_INIT_RESET_CURBE_PARAMS params); 971 972 virtual MOS_STATUS SetCurbeAvcFrameBrcUpdate( 973 PCODECHAL_ENCODE_AVC_BRC_UPDATE_CURBE_PARAMS params); 974 975 virtual MOS_STATUS SendAvcBrcFrameUpdateSurfaces( 976 PMOS_COMMAND_BUFFER pCmdBuffer, 977 PCODECHAL_ENCODE_AVC_BRC_UPDATE_SURFACE_PARAMS params); 978 979 virtual MOS_STATUS SetCurbeAvcBrcBlockCopy( 980 PCODECHAL_ENCODE_AVC_BRC_BLOCK_COPY_CURBE_PARAMS params); 981 982 virtual MOS_STATUS SendAvcMbEncSurfaces( 983 PMOS_COMMAND_BUFFER pCmdBuffer, 984 PCODECHAL_ENCODE_AVC_MBENC_SURFACE_PARAMS params); 985 986 virtual MOS_STATUS SendAvcWPSurfaces( 987 PMOS_COMMAND_BUFFER pCmdBuffer, 988 PCODECHAL_ENCODE_AVC_WP_SURFACE_PARAMS params); 989 990 virtual MOS_STATUS SendMeSurfaces( 991 PMOS_COMMAND_BUFFER pCmdBuffer, 992 MeSurfaceParams* params); 993 994 virtual MOS_STATUS SetCurbeMe(MeCurbeParams* params); 995 //! 996 //! \brief initial multi ref Qp BRC constant Buffer. 997 //! 998 //! \param [in] params 999 //! BRC init constant buffer params. 1000 //! 1001 //! \return MOS_STATUS 1002 //! MOS_STATUS_SUCCESS if success, else fail reason 1003 MOS_STATUS InitBrcConstantBufferMultiRefQP(PCODECHAL_ENCODE_AVC_INIT_BRC_CONSTANT_BUFFER_PARAMS params); 1004 1005 }; 1006 1007 using PCodechalEncodeAvcEncG8 = CodechalEncodeAvcEncG8*; 1008 1009 #endif // __CODECHAL_ENCODE_AVC_G8_H__ 1010