1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef AMD_BLOCK_MSR_ZEN_H 4 #define AMD_BLOCK_MSR_ZEN_H 5 6 /* 7 * The MCAX CTL/STATUS/ADDR/MISC0 registers are aliases for the legacy MCA registers starting 8 * at 0x00000400 which can still be used instead of the MCAX ones. Each MCAX bank has 16 9 * registers while the legacy MCA banks only had 4 registers each. 10 */ 11 #define MCAX_MSR_BASE 0xc0002000 12 #define MCAX_BANK_SIZE 0x10 13 #define MCAX_CTL_OFFSET 0x0 14 #define MCAX_STATUS_OFFSET 0x1 15 #define MCAX_ADDR_OFFSET 0x2 16 #define MCAX_MISC0_OFFSET 0x3 17 #define MCAX_CONFIG_OFFSET 0x4 18 #define MCAX_IPID_OFFSET 0x5 19 #define MCAX_SYND_OFFSET 0x6 20 #define MCAX_RESERVED_OFFSET 0x7 21 #define MCAX_DESTAT_OFFSET 0x8 22 #define MCAX_DEADDR_OFFSET 0x9 23 #define MCAX_MISC1_OFFSET 0xa 24 #define MCAX_MISC2_OFFSET 0xb 25 #define MCAX_MISC3_OFFSET 0xc 26 #define MCAX_MISC4_OFFSET 0xd 27 #define MCAX_MSR(bank, offset) (MCAX_MSR_BASE + (bank) * MCAX_BANK_SIZE + (offset)) 28 #define MCAX_CTL_MSR(bank) MCAX_MSR(bank, MCAX_CTL_OFFSET) 29 #define MCAX_STATUS_MSR(bank) MCAX_MSR(bank, MCAX_STATUS_OFFSET) 30 #define MCAX_ADDR_MSR(bank) MCAX_MSR(bank, MCAX_ADDR_OFFSET) 31 #define MCAX_MISC0_MSR(bank) MCAX_MSR(bank, MCAX_MISC0_OFFSET) 32 #define MCAX_CONFIG_MSR(bank) MCAX_MSR(bank, MCAX_CONFIG_OFFSET) 33 #define MCAX_IPID_MSR(bank) MCAX_MSR(bank, MCAX_IPID_OFFSET) 34 #define MCAX_SYND_MSR(bank) MCAX_MSR(bank, MCAX_SYND_OFFSET) 35 #define MCAX_DESTAT_MSR(bank) MCAX_MSR(bank, MCAX_DESTAT_OFFSET) 36 #define MCAX_DEADDR_MSR(bank) MCAX_MSR(bank, MCAX_DEADDR_OFFSET) 37 #define MCAX_MISC1_MSR(bank) MCAX_MSR(bank, MCAX_MISC1_OFFSET) 38 #define MCAX_MISC2_MSR(bank) MCAX_MSR(bank, MCAX_MISC2_OFFSET) 39 #define MCAX_MISC3_MSR(bank) MCAX_MSR(bank, MCAX_MISC3_OFFSET) 40 #define MCAX_MISC4_MSR(bank) MCAX_MSR(bank, MCAX_MISC4_OFFSET) 41 42 /* 43 * The MCA CTL_MASK moved to a new location in the fam 17h+ CPUs and accessing the legacy 44 * CTL_MASK MSR starting at 0xc0010044 on fam17h+ CPUs will cause a general protection fault. 45 */ 46 #define MCA_CTL_MASK_MSR_0 0xc0010400 47 #define MCA_CTL_MASK_MSR(bank) (MCA_CTL_MASK_MSR_0 + (bank)) 48 49 #endif /* AMD_BLOCK_MSR_ZEN_H */ 50