Home
last modified time | relevance | path

Searched defs:MI1 (Results 1 – 25 of 35) sorted by relevance

12

/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMicroMipsSizeReduction.cpp398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr()
464 MachineInstr *MI1 = Arguments->MI; in ReduceXWtoXWP() local
621 MachineInstr *MI1 = Arguments->MI; in ReduceMoveToMovep() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/
H A DMicroMipsSizeReduction.cpp398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr()
464 MachineInstr *MI1 = Arguments->MI; in ReduceXWtoXWP() local
621 MachineInstr *MI1 = Arguments->MI; in ReduceMoveToMovep() local
/aosp_15_r20/external/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp386 const MachineInstr &MI1, in produceSameValue()
570 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
585 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp420 const MachineInstr &MI1, in produceSameValue()
676 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
691 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
H A DDFAPacketizer.cpp301 bool VLIWPacketizerList::alias(const MachineInstr &MI1, in alias()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp427 const MachineInstr &MI1, in produceSameValue()
706 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
726 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
H A DDFAPacketizer.cpp301 bool VLIWPacketizerList::alias(const MachineInstr &MI1, in alias()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/
H A DAArch64MachineScheduler.cpp36 static bool mayOverlapWrite(const MachineInstr &MI0, const MachineInstr &MI1, in mayOverlapWrite()
H A DAArch64CollectLOH.cpp285 const MachineInstr *MI1; ///< Second instruction involved in the LOH member
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp285 const MachineInstr *MI1; ///< Second instruction involved in the LOH member
/aosp_15_r20/external/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp364 int64_t OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, unsigned N1, in getAddrDispShift()
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp399 int64_t X86OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, in getAddrDispShift()
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp146 MachineInstr &MI1 = *SU.getInstr(); in apply() local
H A DHexagonInstrInfo.cpp2615 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1, in isToBeScheduledASAP()
2934 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1, in addLatencyToSchedule()
H A DHexagonVLIWPacketizer.cpp959 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp398 int64_t X86OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, in getAddrDispShift()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp1484 auto MI1 = in expandLSLW4Rd() local
1570 auto MI1 = in expandLSLW12Rd() local
1682 auto MI1 = in expandLSRW4Rd() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/
H A DLoadStoreOpt.cpp103 bool GISelAddressing::aliasIsKnownForLoadStore(const MachineInstr &MI1, in aliasIsKnownForLoadStore()
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp457 MachineInstr *MI1 = *I1; in hoistAndMergeSGPRInits() local
H A DAMDGPUSubtarget.cpp779 MachineInstr &MI1 = *SUa->getInstr(); in apply() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp268 MachineInstr &MI1 = *SU.getInstr(); in apply() local
H A DHexagonVLIWPacketizer.cpp966 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements()
H A DHexagonInstrInfo.cpp2683 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1, in isToBeScheduledASAP()
3031 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1, in addLatencyToSchedule()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp465 MachineInstr *MI1 = *I1; in hoistAndMergeSGPRInits() local
/aosp_15_r20/external/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp844 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements()

12