ddrphy_wo_pll_reg.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c) - OpenGrok cross reference for /aosp_15_r20/external/coreboot/src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h

/* SPDX-License-Identifier: BSD-3-Clause */

#ifndef __DDRPHY_WO_PLL_REG_H__
#define __DDRPHY_WO_PLL_REG_H__

/* ----------------- Register Definitions ------------------- */
#define B0_DLL_ARPI0					0x00000080
	#define B0_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B0	BIT(1)
	#define B0_DLL_ARPI0_RG_ARPI_RESETB_B0		BIT(3)
	#define B0_DLL_ARPI0_RG_ARPI_LS_EN_B0		BIT(4)
	#define B0_DLL_ARPI0_RG_ARPI_LS_SEL_B0		BIT(5)
	#define B0_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B0	BIT(6)
#define B0_DLL_ARPI1					0x00000084
	#define B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0	BIT(11)
	#define B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0	BIT(13)
	#define B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0	BIT(14)
	#define B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0	BIT(15)
	#define B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0	BIT(17)
	#define B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0	BIT(19)
	#define B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT	BIT(20)
	#define B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0	BIT(21)
	#define B0_DLL_ARPI1_RG_ARPI_SET_UPDN_B0	GENMASK(30, 28)
#define B0_DLL_ARPI2					0x00000088
	#define B0_DLL_ARPI2_RG_ARDLL_PHDET_EN_B0	BIT(0)
	#define B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0	BIT(10)
	#define B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0	BIT(11)
	#define B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0		BIT(13)
	#define B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0		BIT(14)
	#define B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0		BIT(15)
	#define B0_DLL_ARPI2_RG_ARPI_CG_FB_B0		BIT(17)
	#define B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0		BIT(19)
	#define B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0	BIT(27)
	#define B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0		BIT(31)
#define B0_DLL_ARPI3					0x0000008c
	#define B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0	BIT(11)
	#define B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0		BIT(13)
	#define B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0		BIT(14)
	#define B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0		BIT(15)
	#define B0_DLL_ARPI3_RG_ARPI_FB_EN_B0		BIT(17)
	#define B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0		BIT(19)
#define B0_DLL_ARPI4					0x00000090
	#define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQSIEN_B0	BIT(11)
	#define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQ_B0	BIT(13)
	#define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQM_B0	BIT(14)
	#define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQS_B0	BIT(15)
	#define B0_DLL_ARPI4_RG_ARPI_BYPASS_FB_B0	BIT(17)
	#define B0_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_B0	BIT(19)
#define B0_DLL_ARPI5					0x00000094
	#define B0_DLL_ARPI5_RG_ARDLL_DIV_MCTL_B0	GENMASK(3, 2)
	#define B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0	GENMASK(7, 4)
	#define B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0	BIT(8)
	#define B0_DLL_ARPI5_B0_DLL_ARPI5_RFU		GENMASK(23, 12)
	#define B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0	BIT(25)
	#define B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0	BIT(26)
	#define B0_DLL_ARPI5_B0_DLL_ARPI5_RFU1		BIT(31)
#define B0_DQ0						0x00000098
	#define B0_DQ0_RG_RX_ARDQ0_OFFC_B0		GENMASK(3, 0)
	#define B0_DQ0_RG_RX_ARDQ1_OFFC_B0		GENMASK(7, 4)
	#define B0_DQ0_RG_RX_ARDQ2_OFFC_B0		GENMASK(11, 8)
	#define B0_DQ0_RG_RX_ARDQ3_OFFC_B0		GENMASK(15, 12)
	#define B0_DQ0_RG_RX_ARDQ4_OFFC_B0		GENMASK(19, 16)
	#define B0_DQ0_RG_RX_ARDQ5_OFFC_B0		GENMASK(23, 20)
	#define B0_DQ0_RG_RX_ARDQ6_OFFC_B0		GENMASK(27, 24)
	#define B0_DQ0_RG_RX_ARDQ7_OFFC_B0		GENMASK(31, 28)
#define B0_DQ1						0x0000009c
	#define B0_DQ1_RG_RX_ARDQM0_OFFC_B0		GENMASK(3, 0)
#define B0_DQ2						0x000000a0
	#define B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0	BIT(16)
	#define B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0		BIT(17)
	#define B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0	BIT(18)
	#define B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0		BIT(19)
	#define B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0		BIT(20)
	#define B0_DQ2_RG_TX_ARDQ_OE_DIS_B0		BIT(21)
#define B0_DQ3						0x000000a4
	#define B0_DQ3_RG_ARDQ_ATPG_EN_B0		BIT(0)
	#define B0_DQ3_RG_RX_ARDQ_SMT_EN_B0		BIT(1)
	#define B0_DQ3_RG_TX_ARDQ_EN_B0			BIT(2)
	#define B0_DQ3_RG_ARDQ_RESETB_B0		BIT(3)
	#define B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0	BIT(5)
	#define B0_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B0	BIT(6)
	#define B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0		BIT(7)
	#define B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0	BIT(10)
	#define B0_DQ3_RG_RX_ARDQ_OFFC_EN_B0		BIT(11)
	#define B0_DQ3_RG_RX_ARDQS0_SWAP_EN_B0		BIT(15)
#define B0_DQ4						0x000000a8
	#define B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0		GENMASK(6, 0)
	#define B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0		GENMASK(14, 8)
	#define B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0		GENMASK(21, 16)
	#define B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0		GENMASK(29, 24)
#define B0_DQ5						0x000000ac
	#define B0_DQ5_B0_DQ5_RFU			GENMASK(7, 0)
	#define B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0	GENMASK(13, 8)
	#define B0_DQ5_RG_RX_ARDQ_VREF_EN_B0		BIT(16)
	#define B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0	BIT(17)
	#define B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0		GENMASK(23, 20)
	#define B0_DQ5_RG_RX_ARDQ_EYE_EN_B0		BIT(24)
	#define B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0	BIT(25)
	#define B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0		BIT(31)
#define B0_DQ6						0x000000b0
	#define B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0		GENMASK(1, 0)
	#define B0_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B0		BIT(2)
	#define B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0	BIT(3)
	#define B0_DQ6_RG_TX_ARDQ_SER_MODE_B0		BIT(4)
	#define B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0	BIT(5)
	#define B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0	BIT(6)
	#define B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0	BIT(7)
	#define B0_DQ6_RG_RX_ARDQ_LPBK_EN_B0		BIT(8)
	#define B0_DQ6_RG_RX_ARDQ_O1_SEL_B0		BIT(9)
	#define B0_DQ6_RG_RX_ARDQ_JM_SEL_B0		BIT(11)
	#define B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0		BIT(12)
	#define B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0	GENMASK(15, 14)
	#define B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0		BIT(16)
	#define B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0		BIT(17)
	#define B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0		BIT(18)
	#define B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0		BIT(19)
	#define B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0	BIT(24)
	#define B0_DQ6_RG_RX_ARDQ_EYE_OE_GATE_EN_B0	BIT(28)
	#define B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0	BIT(31)
#define B0_DQ7						0x000000b4
	#define B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0		BIT(0)
	#define B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0		BIT(1)
	#define B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0		BIT(2)
	#define B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0		BIT(3)
	#define B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0		BIT(4)
	#define B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0		BIT(5)
	#define B0_DQ7_RG_TX_ARDQ_PULL_DN_B0		BIT(6)
	#define B0_DQ7_RG_TX_ARDQ_PULL_UP_B0		BIT(7)
	#define B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y	BIT(16)
#define B0_DQ8						0x000000b8
	#define B0_DQ8_RG_TX_ARDQ_EN_LP4P_B0		BIT(0)
	#define B0_DQ8_RG_TX_ARDQ_EN_CAP_LP4P_B0	BIT(1)
	#define B0_DQ8_RG_TX_ARDQ_CAP_DET_B0		BIT(2)
	#define B0_DQ8_RG_TX_ARDQ_CKE_MCK4X_SEL_B0	GENMASK(4, 3)
	#define B0_DQ8_RG_ARPI_TX_CG_DQ_EN_B0		BIT(5)
	#define B0_DQ8_RG_ARPI_TX_CG_DQM_EN_B0		BIT(6)
	#define B0_DQ8_RG_ARPI_TX_CG_DQS_EN_B0		BIT(7)
	#define B0_DQ8_RG_RX_ARDQS_BURST_E1_EN_B0	BIT(8)
	#define B0_DQ8_RG_RX_ARDQS_BURST_E2_EN_B0	BIT(9)
	#define B0_DQ8_RG_RX_ARDQS_DQSSTB_CG_EN_B0	BIT(10)
	#define B0_DQ8_RG_RX_ARDQS_GATE_EN_MODE_B0	BIT(12)
	#define B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0	BIT(13)
	#define B0_DQ8_RG_ARDLL_RESETB_B0		BIT(15)
#define B0_DQ9						0x000000bc
	#define B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0	BIT(0)
	#define B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0	BIT(4)
	#define B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0	BIT(5)
	#define B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0	BIT(7)
	#define B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0		GENMASK(15, 8)
	#define B0_DQ9_R_DMDQSIEN_VALID_LAT_B0		GENMASK(18, 16)
	#define B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0		GENMASK(22, 20)
	#define B0_DQ9_R_DMRXDVS_VALID_LAT_B0		GENMASK(26, 24)
	#define B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0		GENMASK(30, 28)
#define RFU_0X0C0					0x000000c0
	#define RFU_0X0C0_RESERVED_0X0C0		GENMASK(31, 0)
#define RFU_0X0C4					0x000000c4
	#define RFU_0X0C4_RESERVED_0X0C4		GENMASK(31, 0)
#define RFU_0X0C8					0x000000c8
	#define RFU_0X0C8_RESERVED_0X0C8		GENMASK(31, 0)
#define RFU_0X0CC					0x000000cc
	#define RFU_0X0CC_RESERVED_0X0CC		GENMASK(31, 0)
#define B0_TX_MCK					0x000000d0
	#define B0_TX_MCK_R_DM_TX_MCK_FRUN_B0		GENMASK(9, 0)
#define RFU_0X0D4					0x000000d4
	#define RFU_0X0D4_RESERVED_0X0D4		GENMASK(31, 0)
#define RFU_0X0D8					0x000000d8
	#define RFU_0X0D8_RESERVED_0X0D8		GENMASK(31, 0)
#define RFU_0X0DC					0x000000dc
	#define RFU_0X0DC_RESERVED_0X0DC		GENMASK(31, 0)
#define B1_DLL_ARPI0					0x00000100
	#define B1_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B1	BIT(1)
	#define B1_DLL_ARPI0_RG_ARPI_RESETB_B1		BIT(3)
	#define B1_DLL_ARPI0_RG_ARPI_LS_EN_B1		BIT(4)
	#define B1_DLL_ARPI0_RG_ARPI_LS_SEL_B1		BIT(5)
	#define B1_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B1	BIT(6)
#define B1_DLL_ARPI1					0x00000104
	#define B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1	BIT(11)
	#define B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1	BIT(13)
	#define B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1	BIT(14)
	#define B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1	BIT(15)
	#define B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1	BIT(17)
	#define B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1	BIT(19)
	#define B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT	BIT(20)
	#define B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1	BIT(21)
	#define B1_DLL_ARPI1_RG_ARPI_SET_UPDN_B1	GENMASK(30, 28)
#define B1_DLL_ARPI2					0x00000108
	#define B1_DLL_ARPI2_RG_ARDLL_PHDET_EN_B1	BIT(0)
	#define B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1	BIT(10)
	#define B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1	BIT(11)
	#define B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1		BIT(13)
	#define B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1		BIT(14)
	#define B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1		BIT(15)
	#define B1_DLL_ARPI2_RG_ARPI_CG_FB_B1		BIT(17)
	#define B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1		BIT(19)
	#define B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1	BIT(27)
	#define B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1		BIT(31)
#define B1_DLL_ARPI3					0x0000010c
	#define B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1	BIT(11)
	#define B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1		BIT(13)
	#define B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1		BIT(14)
	#define B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1		BIT(15)
	#define B1_DLL_ARPI3_RG_ARPI_FB_EN_B1		BIT(17)
	#define B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1		BIT(19)
#define B1_DLL_ARPI4					0x00000110
	#define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQSIEN_B1	BIT(11)
	#define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQ_B1	BIT(13)
	#define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQM_B1	BIT(14)
	#define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQS_B1	BIT(15)
	#define B1_DLL_ARPI4_RG_ARPI_BYPASS_FB_B1	BIT(17)
	#define B1_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_B1	BIT(19)
#define B1_DLL_ARPI5					0x00000114
	#define B1_DLL_ARPI5_RG_ARDLL_DIV_MCTL_B1	GENMASK(3, 2)
	#define B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1	GENMASK(7, 4)
	#define B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1	BIT(8)
	#define B1_DLL_ARPI5_B1_DLL_ARPI5_RFU		GENMASK(23, 12)
	#define B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1	BIT(25)
	#define B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1	BIT(26)
	#define B1_DLL_ARPI5_B1_DLL_ARPI5_RFU1		BIT(31)
#define B1_DQ0						0x00000118
	#define B1_DQ0_RG_RX_ARDQ0_OFFC_B1		GENMASK(3, 0)
	#define B1_DQ0_RG_RX_ARDQ1_OFFC_B1		GENMASK(7, 4)
	#define B1_DQ0_RG_RX_ARDQ2_OFFC_B1		GENMASK(11, 8)
	#define B1_DQ0_RG_RX_ARDQ3_OFFC_B1		GENMASK(15, 12)
	#define B1_DQ0_RG_RX_ARDQ4_OFFC_B1		GENMASK(19, 16)
	#define B1_DQ0_RG_RX_ARDQ5_OFFC_B1		GENMASK(23, 20)
	#define B1_DQ0_RG_RX_ARDQ6_OFFC_B1		GENMASK(27, 24)
	#define B1_DQ0_RG_RX_ARDQ7_OFFC_B1		GENMASK(31, 28)
#define B1_DQ1						0x0000011c
	#define B1_DQ1_RG_RX_ARDQM0_OFFC_B1		GENMASK(3, 0)
#define B1_DQ2						0x00000120
	#define B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1	BIT(16)
	#define B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1		BIT(17)
	#define B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1	BIT(18)
	#define B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1		BIT(19)
	#define B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1		BIT(20)
	#define B1_DQ2_RG_TX_ARDQ_OE_DIS_B1		BIT(21)
#define B1_DQ3						0x00000124
	#define B1_DQ3_RG_ARDQ_ATPG_EN_B1		BIT(0)
	#define B1_DQ3_RG_RX_ARDQ_SMT_EN_B1		BIT(1)
	#define B1_DQ3_RG_TX_ARDQ_EN_B1			BIT(2)
	#define B1_DQ3_RG_ARDQ_RESETB_B1		BIT(3)
	#define B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1	BIT(5)
	#define B1_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B1	BIT(6)
	#define B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1		BIT(7)
	#define B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1	BIT(10)
	#define B1_DQ3_RG_RX_ARDQ_OFFC_EN_B1		BIT(11)
	#define B1_DQ3_RG_RX_ARDQS0_SWAP_EN_B1		BIT(15)
#define B1_DQ4						0x00000128
	#define B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1		GENMASK(6, 0)
	#define B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1		GENMASK(14, 8)
	#define B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1		GENMASK(21, 16)
	#define B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1		GENMASK(29, 24)
#define B1_DQ5						0x0000012c
	#define B1_DQ5_B1_DQ5_RFU			GENMASK(7, 0)
	#define B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1	GENMASK(13, 8)
	#define B1_DQ5_RG_RX_ARDQ_VREF_EN_B1		BIT(16)
	#define B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1	BIT(17)
	#define B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1		GENMASK(23, 20)
	#define B1_DQ5_RG_RX_ARDQ_EYE_EN_B1		BIT(24)
	#define B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1	BIT(25)
	#define B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1		BIT(31)
#define B1_DQ6						0x00000130
	#define B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1		GENMASK(1, 0)
	#define B1_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B1		BIT(2)
	#define B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1	BIT(3)
	#define B1_DQ6_RG_TX_ARDQ_SER_MODE_B1		BIT(4)
	#define B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1	BIT(5)
	#define B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1	BIT(6)
	#define B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1	BIT(7)
	#define B1_DQ6_RG_RX_ARDQ_LPBK_EN_B1		BIT(8)
	#define B1_DQ6_RG_RX_ARDQ_O1_SEL_B1		BIT(9)
	#define B1_DQ6_RG_RX_ARDQ_JM_SEL_B1		BIT(11)
	#define B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1		BIT(12)
	#define B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1	GENMASK(15, 14)
	#define B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1		BIT(16)
	#define B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1		BIT(17)
	#define B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1		BIT(18)
	#define B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1		BIT(19)
	#define B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1	BIT(24)
	#define B1_DQ6_RG_RX_ARDQ_EYE_OE_GATE_EN_B1	BIT(28)
	#define B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1	BIT(31)
#define B1_DQ7						0x00000134
	#define B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1		BIT(0)
	#define B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1		BIT(1)
	#define B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1		BIT(2)
	#define B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1		BIT(3)
	#define B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1		BIT(4)
	#define B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1		BIT(5)
	#define B1_DQ7_RG_TX_ARDQ_PULL_DN_B1		BIT(6)
	#define B1_DQ7_RG_TX_ARDQ_PULL_UP_B1		BIT(7)
	#define B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y	BIT(16)
#define B1_DQ8						0x00000138
	#define B1_DQ8_RG_TX_ARDQ_EN_LP4P_B1		BIT(0)
	#define B1_DQ8_RG_TX_ARDQ_EN_CAP_LP4P_B1	BIT(1)
	#define B1_DQ8_RG_TX_ARDQ_CAP_DET_B1		BIT(2)
	#define B1_DQ8_RG_TX_ARDQ_CKE_MCK4X_SEL_B1	GENMASK(4, 3)
	#define B1_DQ8_RG_ARPI_TX_CG_DQ_EN_B1		BIT(5)
	#define B1_DQ8_RG_ARPI_TX_CG_DQM_EN_B1		BIT(6)
	#define B1_DQ8_RG_ARPI_TX_CG_DQS_EN_B1		BIT(7)
	#define B1_DQ8_RG_RX_ARDQS_BURST_E1_EN_B1	BIT(8)
	#define B1_DQ8_RG_RX_ARDQS_BURST_E2_EN_B1	BIT(9)
	#define B1_DQ8_RG_RX_ARDQS_DQSSTB_CG_EN_B1	BIT(10)
	#define B1_DQ8_RG_RX_ARDQS_GATE_EN_MODE_B1	BIT(12)
	#define B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1	BIT(13)
	#define B1_DQ8_RG_ARDLL_RESETB_B1		BIT(15)
#define B1_DQ9						0x0000013c
	#define B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1	BIT(0)
	#define B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1	BIT(4)
	#define B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1	BIT(5)
	#define B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1	BIT(7)
	#define B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1		GENMASK(15, 8)
	#define B1_DQ9_R_DMDQSIEN_VALID_LAT_B1		GENMASK(18, 16)
	#define B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1		GENMASK(22, 20)
	#define B1_DQ9_R_DMRXDVS_VALID_LAT_B1		GENMASK(26, 24)
	#define B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1		GENMASK(30, 28)
#define RFU_0X140					0x00000140
	#define RFU_0X140_RESERVED_0X140		GENMASK(31, 0)
#define RFU_0X144					0x00000144
	#define RFU_0X144_RESERVED_0X144		GENMASK(31, 0)
#define RFU_0X148					0x00000148
	#define RFU_0X148_RESERVED_0X148		GENMASK(31, 0)
#define RFU_0X14C					0x0000014c
	#define RFU_0X14C_RESERVED_0X14C		GENMASK(31, 0)
#define B1_TX_MCK					0x00000150
	#define B1_TX_MCK_R_DM_TX_MCK_FRUN_B1		GENMASK(9, 0)
#define RFU_0X154					0x00000154
	#define RFU_0X154_RESERVED_0X154		GENMASK(31, 0)
#define RFU_0X158					0x00000158
	#define RFU_0X158_RESERVED_0X158		GENMASK(31, 0)
#define RFU_0X15C					0x0000015c
	#define RFU_0X15C_RESERVED_0X15C		GENMASK(31, 0)
#define CA_DLL_ARPI0					0x00000180
	#define CA_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_CA	BIT(1)
	#define CA_DLL_ARPI0_RG_ARPI_RESETB_CA		BIT(3)
	#define CA_DLL_ARPI0_RG_ARPI_LS_EN_CA		BIT(4)
	#define CA_DLL_ARPI0_RG_ARPI_LS_SEL_CA		BIT(5)
	#define CA_DLL_ARPI0_RG_ARPI_MCK8X_SEL_CA	BIT(6)
#define CA_DLL_ARPI1					0x00000184
	#define CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN	BIT(11)
	#define CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN	BIT(13)
	#define CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN	BIT(15)
	#define CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN		BIT(16)
	#define CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA	BIT(17)
	#define CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA	BIT(19)
	#define CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT	BIT(20)
	#define CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA	BIT(21)
	#define CA_DLL_ARPI1_RG_ARPI_SET_UPDN_CA	GENMASK(30, 28)
#define CA_DLL_ARPI2					0x00000188
	#define CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA	BIT(0)
	#define CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA	BIT(10)
	#define CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN		BIT(11)
	#define CA_DLL_ARPI2_RG_ARPI_CG_CMD		BIT(13)
	#define CA_DLL_ARPI2_RG_ARPI_CG_CLK		BIT(15)
	#define CA_DLL_ARPI2_RG_ARPI_CG_CS		BIT(16)
	#define CA_DLL_ARPI2_RG_ARPI_CG_FB_CA		BIT(17)
	#define CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA		BIT(19)
	#define CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA	BIT(27)
	#define CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA		BIT(31)
#define CA_DLL_ARPI3					0x0000018c
	#define CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN		BIT(11)
	#define CA_DLL_ARPI3_RG_ARPI_CMD_EN		BIT(13)
	#define CA_DLL_ARPI3_RG_ARPI_CLK_EN		BIT(15)
	#define CA_DLL_ARPI3_RG_ARPI_CS_EN		BIT(16)
	#define CA_DLL_ARPI3_RG_ARPI_FB_EN_CA		BIT(17)
	#define CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA		BIT(19)
#define CA_DLL_ARPI4					0x00000190
	#define CA_DLL_ARPI4_RG_ARPI_BYPASS_CLKIEN	BIT(11)
	#define CA_DLL_ARPI4_RG_ARPI_BYPASS_CMD		BIT(13)
	#define CA_DLL_ARPI4_RG_ARPI_BYPASS_CLK		BIT(15)
	#define CA_DLL_ARPI4_RG_ARPI_BYPASS_CS		BIT(16)
	#define CA_DLL_ARPI4_RG_ARPI_BYPASS_FB_CA	BIT(17)
	#define CA_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_CA	BIT(19)
#define CA_DLL_ARPI5					0x00000194
	#define CA_DLL_ARPI5_RG_ARDLL_DIV_MCTL_CA	GENMASK(3, 2)
	#define CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA	GENMASK(7, 4)
	#define CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA	BIT(8)
	#define CA_DLL_ARPI5_CA_DLL_ARPI5_RFU		GENMASK(23, 12)
	#define CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA	BIT(25)
	#define CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA	BIT(26)
#define CA_CMD0						0x00000198
	#define CA_CMD0_RG_RX_ARCA0_OFFC		GENMASK(3, 0)
	#define CA_CMD0_RG_RX_ARCA1_OFFC		GENMASK(7, 4)
	#define CA_CMD0_RG_RX_ARCA2_OFFC		GENMASK(11, 8)
	#define CA_CMD0_RG_RX_ARCA3_OFFC		GENMASK(15, 12)
	#define CA_CMD0_RG_RX_ARCA4_OFFC		GENMASK(19, 16)
	#define CA_CMD0_RG_RX_ARCA5_OFFC		GENMASK(23, 20)
#define CA_CMD1						0x0000019c
	#define CA_CMD1_RG_RX_ARCS0_OFFC		GENMASK(3, 0)
	#define CA_CMD1_RG_RX_ARCS1_OFFC		GENMASK(7, 4)
	#define CA_CMD1_RG_RX_ARCS2_OFFC		GENMASK(11, 8)
	#define CA_CMD1_RG_RX_ARCKE0_OFFC		GENMASK(15, 12)
	#define CA_CMD1_RG_RX_ARCKE1_OFFC		GENMASK(19, 16)
	#define CA_CMD1_RG_RX_ARCKE2_OFFC		GENMASK(23, 20)
#define CA_CMD2						0x000001a0
	#define CA_CMD2_RG_TX_ARCLK_ODTEN_DIS		BIT(16)
	#define CA_CMD2_RG_TX_ARCLK_OE_DIS		BIT(17)
	#define CA_CMD2_RG_TX_ARCMD_ODTEN_DIS		BIT(20)
	#define CA_CMD2_RG_TX_ARCMD_OE_DIS		BIT(21)
#define CA_CMD3						0x000001a4
	#define CA_CMD3_RG_ARCMD_ATPG_EN		BIT(0)
	#define CA_CMD3_RG_RX_ARCMD_SMT_EN		BIT(1)
	#define CA_CMD3_RG_TX_ARCMD_EN			BIT(2)
	#define CA_CMD3_RG_ARCMD_RESETB			BIT(3)
	#define CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN		BIT(5)
	#define CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN		BIT(7)
	#define CA_CMD3_RG_RX_ARCMD_STBENCMP_EN		BIT(10)
	#define CA_CMD3_RG_RX_ARCMD_OFFC_EN		BIT(11)
	#define CA_CMD3_RG_RX_ARCLK_SWAP_EN		BIT(15)
#define CA_CMD4						0x000001a8
	#define CA_CMD4_RG_RX_ARCLK_EYE_R_DLY		GENMASK(6, 0)
	#define CA_CMD4_RG_RX_ARCLK_EYE_F_DLY		GENMASK(14, 8)
	#define CA_CMD4_RG_RX_ARCMD_EYE_R_DLY		GENMASK(21, 16)
	#define CA_CMD4_RG_RX_ARCMD_EYE_F_DLY		GENMASK(29, 24)
#define CA_CMD5						0x000001ac
	#define CA_CMD5_CA_CMD5_RFU			GENMASK(7, 0)
	#define CA_CMD5_RG_RX_ARCMD_EYE_VREF_SEL	GENMASK(13, 8)
	#define CA_CMD5_RG_RX_ARCMD_VREF_EN		BIT(16)
	#define CA_CMD5_RG_RX_ARCMD_EYE_VREF_EN		BIT(17)
	#define CA_CMD5_RG_RX_ARCMD_EYE_SEL		GENMASK(23, 20)
	#define CA_CMD5_RG_RX_ARCMD_EYE_EN		BIT(24)
	#define CA_CMD5_RG_RX_ARCMD_EYE_STBEN_RESETB	BIT(25)
	#define CA_CMD5_RG_RX_ARCLK_DVS_EN		BIT(31)
#define CA_CMD6						0x000001b0
	#define CA_CMD6_RG_RX_ARCMD_BIAS_PS		GENMASK(1, 0)
	#define CA_CMD6_RG_TX_ARCMD_OE_EXT_DIS		BIT(2)
	#define CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS	BIT(3)
	#define CA_CMD6_RG_TX_ARCMD_SER_MODE		BIT(4)
	#define CA_CMD6_RG_RX_ARCMD_RPRE_TOG_EN		BIT(5)
	#define CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN		BIT(6)
	#define CA_CMD6_RG_RX_ARCMD_OP_BIAS_SW_EN	BIT(7)
	#define CA_CMD6_RG_RX_ARCMD_LPBK_EN		BIT(8)
	#define CA_CMD6_RG_RX_ARCMD_O1_SEL		BIT(9)
	#define CA_CMD6_RG_RX_ARCMD_JM_SEL		BIT(11)
	#define CA_CMD6_RG_RX_ARCMD_BIAS_EN		BIT(12)
	#define CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL	GENMASK(15, 14)
	#define CA_CMD6_RG_RX_ARCMD_DDR4_SEL		BIT(16)
	#define CA_CMD6_RG_TX_ARCMD_DDR4_SEL		BIT(17)
	#define CA_CMD6_RG_RX_ARCMD_DDR3_SEL		BIT(18)
	#define CA_CMD6_RG_TX_ARCMD_DDR3_SEL		BIT(19)
	#define CA_CMD6_RG_RX_ARCMD_EYE_DLY_DQS_BYPASS	BIT(24)
	#define CA_CMD6_RG_RX_ARCMD_EYE_OE_GATE_EN	BIT(28)
	#define CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL	BIT(31)
#define CA_CMD7						0x000001b4
	#define CA_CMD7_RG_TX_ARCLKB_PULL_DN		BIT(0)
	#define CA_CMD7_RG_TX_ARCLKB_PULL_UP		BIT(1)
	#define CA_CMD7_RG_TX_ARCLK_PULL_DN		BIT(2)
	#define CA_CMD7_RG_TX_ARCLK_PULL_UP		BIT(3)
	#define CA_CMD7_RG_TX_ARCS_PULL_DN		BIT(4)
	#define CA_CMD7_RG_TX_ARCS_PULL_UP		BIT(5)
	#define CA_CMD7_RG_TX_ARCMD_PULL_DN		BIT(6)
	#define CA_CMD7_RG_TX_ARCMD_PULL_UP		BIT(7)
	#define CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y	BIT(16)
#define CA_CMD8						0x000001b8
	#define CA_CMD8_RG_RRESETB_DRVP			GENMASK(4, 0)
	#define CA_CMD8_RG_RRESETB_DRVN			GENMASK(12, 8)
	#define CA_CMD8_RG_RX_RRESETB_SMT_EN		BIT(16)
	#define CA_CMD8_RG_TX_RRESETB_SCAN_IN_EN	BIT(17)
	#define CA_CMD8_RG_TX_RRESETB_DDR4_SEL		BIT(18)
	#define CA_CMD8_RG_TX_RRESETB_DDR3_SEL		BIT(19)
	#define CA_CMD8_RG_TX_RRESETB_PULL_DN		BIT(20)
	#define CA_CMD8_RG_TX_RRESETB_PULL_UP		BIT(21)
#define CA_CMD9						0x000001bc
	#define CA_CMD9_RG_TX_ARCMD_EN_LP4P		BIT(0)
	#define CA_CMD9_RG_TX_ARCMD_EN_CAP_LP4P		BIT(1)
	#define CA_CMD9_RG_TX_ARCMD_CAP_DET		BIT(2)
	#define CA_CMD9_RG_TX_ARCMD_CKE_MCK4X_SEL	GENMASK(4, 3)
	#define CA_CMD9_RG_ARPI_TX_CG_CS_EN		BIT(5)
	#define CA_CMD9_RG_ARPI_TX_CG_CA_EN		BIT(6)
	#define CA_CMD9_RG_ARPI_TX_CG_CLK_EN		BIT(7)
	#define CA_CMD9_RG_RX_ARCLK_DQSIEN_BURST_E1_EN	BIT(8)
	#define CA_CMD9_RG_RX_ARCLK_DQSIEN_BURST_E2_EN	BIT(9)
	#define CA_CMD9_RG_RX_ARCLK_DQSSTB_CG_EN	BIT(10)
	#define CA_CMD9_RG_RX_ARCLK_GATE_EN_MODE	BIT(12)
	#define CA_CMD9_RG_RX_ARCLK_SER_RST_MODE	BIT(13)
	#define CA_CMD9_RG_ARDLL_RESETB_CA		BIT(15)
	#define CA_CMD9_RG_TX_ARCMD_LP3_CKE_SEL		BIT(16)
	#define CA_CMD9_RG_TX_ARCMD_LP4_CKE_SEL		BIT(17)
	#define CA_CMD9_RG_TX_ARCMD_LP4X_CKE_SEL	BIT(18)
	#define CA_CMD9_RG_TX_ARCMD_LSH_DQM_CG_EN	BIT(20)
	#define CA_CMD9_RG_TX_ARCMD_LSH_DQS_CG_EN	BIT(21)
	#define CA_CMD9_RG_TX_ARCMD_LSH_DQ_CG_EN	BIT(22)
	#define CA_CMD9_RG_TX_ARCMD_OE_SUS_EN		BIT(24)
	#define CA_CMD9_RG_TX_ARCMD_ODTEN_OE_SUS_EN	BIT(25)
#define CA_CMD10					0x000001c0
	#define CA_CMD10_RG_RX_ARCMD_STBEN_RESETB	BIT(0)
	#define CA_CMD10_RG_RX_ARCLK_STBEN_RESETB	BIT(4)
	#define CA_CMD10_RG_RX_ARCLK_DQSIENMODE		BIT(5)
	#define CA_CMD10_R_DMRXFIFO_STBENCMP_EN_CA	BIT(7)
	#define CA_CMD10_R_IN_GATE_EN_LOW_OPT_CA	GENMASK(15, 8)
	#define CA_CMD10_R_DMDQSIEN_VALID_LAT_CA	GENMASK(18, 16)
	#define CA_CMD10_R_DMDQSIEN_RDSEL_LAT_CA	GENMASK(22, 20)
	#define CA_CMD10_R_DMRXDVS_VALID_LAT_CA		GENMASK(26, 24)
	#define CA_CMD10_R_DMRXDVS_RDSEL_LAT_CA		GENMASK(30, 28)
#define RFU_0X1C4					0x000001c4
	#define RFU_0X1C4_RESERVED_0X1C4		GENMASK(31, 0)
#define RFU_0X1C8					0x000001c8
	#define RFU_0X1C8_RESERVED_0X1C8		GENMASK(31, 0)
#define RFU_0X1CC					0x000001cc
	#define RFU_0X1CC_RESERVED_0X1CC		GENMASK(31, 0)
#define CA_TX_MCK					0x000001d0
	#define CA_TX_MCK_R_DM_TX_MCK_FRUN_CA		GENMASK(12, 0)
	#define CA_TX_MCK_R_DMRESETB_DRVP_FRPHY		GENMASK(25, 21)
	#define CA_TX_MCK_R_DMRESETB_DRVN_FRPHY		GENMASK(30, 26)
	#define CA_TX_MCK_R_DMRESET_FRPHY_OPT		BIT(31)
#define RFU_0X1D4					0x000001d4
	#define RFU_0X1D4_RESERVED_0X1D4		GENMASK(31, 0)
#define RFU_0X1D8					0x000001d8
	#define RFU_0X1D8_RESERVED_0X1D8		GENMASK(31, 0)
#define RFU_0X1DC					0x000001dc
	#define RFU_0X1DC_RESERVED_0X1DC		GENMASK(31, 0)
#define MISC_EXTLB0					0x00000200
	#define MISC_EXTLB0_R_EXTLB_LFSR_INI_0		GENMASK(15, 0)
	#define MISC_EXTLB0_R_EXTLB_LFSR_INI_1		GENMASK(31, 16)
#define MISC_EXTLB1					0x00000204
	#define MISC_EXTLB1_R_EXTLB_LFSR_INI_2		GENMASK(15, 0)
	#define MISC_EXTLB1_R_EXTLB_LFSR_INI_3		GENMASK(31, 16)
#define MISC_EXTLB2					0x00000208
	#define MISC_EXTLB2_R_EXTLB_LFSR_INI_4		GENMASK(15, 0)
	#define MISC_EXTLB2_R_EXTLB_LFSR_INI_5		GENMASK(31, 16)
#define MISC_EXTLB3					0x0000020c
	#define MISC_EXTLB3_R_EXTLB_LFSR_INI_6		GENMASK(15, 0)
	#define MISC_EXTLB3_R_EXTLB_LFSR_INI_7		GENMASK(31, 16)
#define MISC_EXTLB4					0x00000210
	#define MISC_EXTLB4_R_EXTLB_LFSR_INI_8		GENMASK(15, 0)
	#define MISC_EXTLB4_R_EXTLB_LFSR_INI_9		GENMASK(31, 16)
#define MISC_EXTLB5					0x00000214
	#define MISC_EXTLB5_R_EXTLB_LFSR_INI_10		GENMASK(15, 0)
	#define MISC_EXTLB5_R_EXTLB_LFSR_INI_11		GENMASK(31, 16)
#define MISC_EXTLB6					0x00000218
	#define MISC_EXTLB6_R_EXTLB_LFSR_INI_12		GENMASK(15, 0)
	#define MISC_EXTLB6_R_EXTLB_LFSR_INI_13		GENMASK(31, 16)
#define MISC_EXTLB7					0x0000021c
	#define MISC_EXTLB7_R_EXTLB_LFSR_INI_14		GENMASK(15, 0)
	#define MISC_EXTLB7_R_EXTLB_LFSR_INI_15		GENMASK(31, 16)
#define MISC_EXTLB8					0x00000220
	#define MISC_EXTLB8_R_EXTLB_LFSR_INI_16		GENMASK(15, 0)
	#define MISC_EXTLB8_R_EXTLB_LFSR_INI_17		GENMASK(31, 16)
#define MISC_EXTLB9					0x00000224
	#define MISC_EXTLB9_R_EXTLB_LFSR_INI_18		GENMASK(15, 0)
	#define MISC_EXTLB9_R_EXTLB_LFSR_INI_19		GENMASK(31, 16)
#define MISC_EXTLB10					0x00000228
	#define MISC_EXTLB10_R_EXTLB_LFSR_INI_20	GENMASK(15, 0)
	#define MISC_EXTLB10_R_EXTLB_LFSR_INI_21	GENMASK(31, 16)
#define MISC_EXTLB11					0x0000022c
	#define MISC_EXTLB11_R_EXTLB_LFSR_INI_22	GENMASK(15, 0)
	#define MISC_EXTLB11_R_EXTLB_LFSR_INI_23	GENMASK(31, 16)
#define MISC_EXTLB12					0x00000230
	#define MISC_EXTLB12_R_EXTLB_LFSR_INI_24	GENMASK(15, 0)
	#define MISC_EXTLB12_R_EXTLB_LFSR_INI_25	GENMASK(31, 16)
#define MISC_EXTLB13					0x00000234
	#define MISC_EXTLB13_R_EXTLB_LFSR_INI_26	GENMASK(15, 0)
	#define MISC_EXTLB13_R_EXTLB_LFSR_INI_27	GENMASK(31, 16)
#define MISC_EXTLB14					0x00000238
	#define MISC_EXTLB14_R_EXTLB_LFSR_INI_28	GENMASK(15, 0)
	#define MISC_EXTLB14_R_EXTLB_LFSR_INI_29	GENMASK(31, 16)
#define MISC_EXTLB15					0x0000023c
	#define MISC_EXTLB15_R_EXTLB_LFSR_INI_30	GENMASK(15, 0)
	#define MISC_EXTLB15_MISC_EXTLB15_RFU		GENMASK(31, 16)
#define MISC_EXTLB16					0x00000240
	#define MISC_EXTLB16_R_EXTLB_LFSR_TAP		GENMASK(15, 0)
	#define MISC_EXTLB16_R_EXTLB_OE_DQB0_ON		BIT(16)
	#define MISC_EXTLB16_R_EXTLB_OE_DQM0_ON		BIT(17)
	#define MISC_EXTLB16_R_EXTLB_OE_DQS0_ON		BIT(18)
	#define MISC_EXTLB16_R_EXTLB_OE_DQB1_ON		BIT(19)
	#define MISC_EXTLB16_R_EXTLB_OE_DQM1_ON		BIT(20)
	#define MISC_EXTLB16_R_EXTLB_OE_DQS1_ON		BIT(21)
	#define MISC_EXTLB16_R_EXTLB_ODTEN_DQB0_ON	BIT(22)
	#define MISC_EXTLB16_R_EXTLB_ODTEN_DQM0_ON	BIT(23)
	#define MISC_EXTLB16_R_EXTLB_ODTEN_DQS0_ON	BIT(24)
	#define MISC_EXTLB16_R_EXTLB_ODTEN_DQB1_ON	BIT(25)
	#define MISC_EXTLB16_R_EXTLB_ODTEN_DQM1_ON	BIT(26)
	#define MISC_EXTLB16_R_EXTLB_ODTEN_DQS1_ON	BIT(27)
#define MISC_EXTLB17					0x00000244
	#define MISC_EXTLB17_R_EXTLB			BIT(0)
	#define MISC_EXTLB17_R_EXTLB_RX_SWRST		BIT(1)
	#define MISC_EXTLB17_R_EXTLB_TX_EN		BIT(2)
	#define MISC_EXTLB17_R_EXTLB_TX_EN_OTHERCH_SEL	BIT(3)
	#define MISC_EXTLB17_R_INTLB_ARCLK_MUXSEL	BIT(4)
	#define MISC_EXTLB17_R_INTLB_DRDF_CA_MUXSEL	BIT(5)
	#define MISC_EXTLB17_R_EXTLB_TX_PRE_ON		BIT(7)
	#define MISC_EXTLB17_R_EXTLB_RX_LENGTH_M1	GENMASK(31, 8)
#define MISC_EXTLB18					0x00000248
	#define MISC_EXTLB18_R_TX_EN_SRC_SEL		BIT(0)
	#define MISC_EXTLB18_R_OTH_TX_EN_SRC_SEL	BIT(1)
	#define MISC_EXTLB18_R_LPBK_DQ_MODE_FOR_CA	BIT(3)
	#define MISC_EXTLB18_R_LPBK_DQ_TX_MODE		BIT(4)
	#define MISC_EXTLB18_R_LPBK_CA_TX_MODE		BIT(5)
	#define MISC_EXTLB18_R_LPBK_DQ_RX_MODE		BIT(8)
	#define MISC_EXTLB18_R_LPBK_CA_RX_MODE		BIT(9)
	#define MISC_EXTLB18_R_TX_TRIG_SRC_SEL		GENMASK(19, 16)
	#define MISC_EXTLB18_R_OTH_TX_TRIG_SRC_SEL	GENMASK(23, 20)
#define MISC_EXTLB19					0x0000024c
	#define MISC_EXTLB19_R_EXTLB_LFSR_ENABLE	BIT(0)
	#define MISC_EXTLB19_R_EXTLB_SSO_ENABLE		BIT(1)
	#define MISC_EXTLB19_R_EXTLB_XTALK_ENABLE	BIT(2)
	#define MISC_EXTLB19_R_EXTLB_LEADLAG_DBG_ENABLE	BIT(3)
	#define MISC_EXTLB19_R_EXTLB_DBG_SEL		GENMASK(20, 16)
	#define MISC_EXTLB19_R_LPBK_DC_TOG_MODE		BIT(23)
	#define MISC_EXTLB19_R_LPBK_DC_TOG_TIMER	GENMASK(31, 24)
#define MISC_EXTLB20					0x00000250
	#define MISC_EXTLB20_R_XTALK_TX_00_TOG_CYCLE	GENMASK(3, 0)
	#define MISC_EXTLB20_R_XTALK_TX_01_TOG_CYCLE	GENMASK(7, 4)
	#define MISC_EXTLB20_R_XTALK_TX_02_TOG_CYCLE	GENMASK(11, 8)
	#define MISC_EXTLB20_R_XTALK_TX_03_TOG_CYCLE	GENMASK(15, 12)
	#define MISC_EXTLB20_R_XTALK_TX_04_TOG_CYCLE	GENMASK(19, 16)
	#define MISC_EXTLB20_R_XTALK_TX_05_TOG_CYCLE	GENMASK(23, 20)
	#define MISC_EXTLB20_R_XTALK_TX_06_TOG_CYCLE	GENMASK(27, 24)
	#define MISC_EXTLB20_R_XTALK_TX_07_TOG_CYCLE	GENMASK(31, 28)
#define MISC_EXTLB21					0x00000254
	#define MISC_EXTLB21_R_XTALK_TX_08_TOG_CYCLE	GENMASK(3, 0)
	#define MISC_EXTLB21_R_XTALK_TX_09_TOG_CYCLE	GENMASK(7, 4)
	#define MISC_EXTLB21_R_XTALK_TX_10_TOG_CYCLE	GENMASK(11, 8)
	#define MISC_EXTLB21_R_XTALK_TX_11_TOG_CYCLE	GENMASK(15, 12)
	#define MISC_EXTLB21_R_XTALK_TX_12_TOG_CYCLE	GENMASK(19, 16)
	#define MISC_EXTLB21_R_XTALK_TX_13_TOG_CYCLE	GENMASK(23, 20)
	#define MISC_EXTLB21_R_XTALK_TX_14_TOG_CYCLE	GENMASK(27, 24)
	#define MISC_EXTLB21_R_XTALK_TX_15_TOG_CYCLE	GENMASK(31, 28)
#define MISC_EXTLB22					0x00000258
	#define MISC_EXTLB22_R_XTALK_TX_16_TOG_CYCLE	GENMASK(3, 0)
	#define MISC_EXTLB22_R_XTALK_TX_17_TOG_CYCLE	GENMASK(7, 4)
	#define MISC_EXTLB22_R_XTALK_TX_18_TOG_CYCLE	GENMASK(11, 8)
	#define MISC_EXTLB22_R_XTALK_TX_19_TOG_CYCLE	GENMASK(15, 12)
	#define MISC_EXTLB22_R_XTALK_TX_20_TOG_CYCLE	GENMASK(19, 16)
	#define MISC_EXTLB22_R_XTALK_TX_21_TOG_CYCLE	GENMASK(23, 20)
	#define MISC_EXTLB22_R_XTALK_TX_22_TOG_CYCLE	GENMASK(27, 24)
	#define MISC_EXTLB22_R_XTALK_TX_23_TOG_CYCLE	GENMASK(31, 28)
#define MISC_EXTLB23					0x0000025c
	#define MISC_EXTLB23_R_XTALK_TX_24_TOG_CYCLE	GENMASK(3, 0)
	#define MISC_EXTLB23_R_XTALK_TX_25_TOG_CYCLE	GENMASK(7, 4)
	#define MISC_EXTLB23_R_XTALK_TX_26_TOG_CYCLE	GENMASK(11, 8)
	#define MISC_EXTLB23_R_XTALK_TX_27_TOG_CYCLE	GENMASK(15, 12)
	#define MISC_EXTLB23_R_XTALK_TX_28_TOG_CYCLE	GENMASK(19, 16)
	#define MISC_EXTLB23_R_XTALK_TX_29_TOG_CYCLE	GENMASK(23, 20)
	#define MISC_EXTLB23_R_XTALK_TX_30_TOG_CYCLE	GENMASK(27, 24)
	#define MISC_EXTLB23_R_XTALK_TX_31_TOG_CYCLE	GENMASK(31, 28)
#define DVFS_EMI_CLK					0x00000260
	#define DVFS_EMI_CLK_RG_DLL_SHUFFLE		BIT(24)
	#define DVFS_EMI_CLK_RG_52M_104M_SEL		BIT(29)
	#define DVFS_EMI_CLK_RG_GATING_EMI_NEW		GENMASK(31, 30)
#define MISC_VREF_CTRL					0x00000264
	#define MISC_VREF_CTRL_VREF_CTRL_RFU		GENMASK(30, 16)
	#define MISC_VREF_CTRL_RG_RVREF_VREF_EN		BIT(31)
#define MISC_IMP_CTRL0					0x00000268
	#define MISC_IMP_CTRL0_RG_IMP_OCD_PUCMP_EN	BIT(3)
	#define MISC_IMP_CTRL0_RG_IMP_EN		BIT(4)
	#define MISC_IMP_CTRL0_RG_RIMP_DDR4_SEL		BIT(5)
	#define MISC_IMP_CTRL0_RG_RIMP_DDR3_SEL		BIT(6)
#define MISC_IMP_CTRL1					0x0000026c
	#define MISC_IMP_CTRL1_RG_RIMP_BIAS_EN		BIT(4)
	#define MISC_IMP_CTRL1_RG_RIMP_ODT_EN		BIT(5)
	#define MISC_IMP_CTRL1_RG_RIMP_PRE_EN		BIT(6)
	#define MISC_IMP_CTRL1_RG_RIMP_VREF_EN		BIT(7)
	#define MISC_IMP_CTRL1_RG_RIMP_DRV05		BIT(16)
	#define MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT	BIT(31)
#define MISC_SHU_OPT					0x00000270
	#define MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN	BIT(0)
	#define MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN	GENMASK(3, 2)
	#define MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN	BIT(8)
	#define MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN	GENMASK(11, 10)
	#define MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN	BIT(16)
	#define MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN	GENMASK(19, 18)
#define MISC_SPM_CTRL0					0x00000274
	#define MISC_SPM_CTRL0_PHY_SPM_CTL0		GENMASK(31, 0)
#define MISC_SPM_CTRL1					0x00000278
	#define MISC_SPM_CTRL1_RG_ARDMSUS_10		BIT(0)
	#define MISC_SPM_CTRL1_RG_ARDMSUS_10_B0		BIT(1)
	#define MISC_SPM_CTRL1_RG_ARDMSUS_10_B1		BIT(2)
	#define MISC_SPM_CTRL1_RG_ARDMSUS_10_CA		BIT(3)
	#define MISC_SPM_CTRL1_SPM_DVFS_CONTROL_SEL	BIT(16)
	#define MISC_SPM_CTRL1_RG_DR_SHU_LEVEL		GENMASK(18, 17)
	#define MISC_SPM_CTRL1_RG_PHYPLL_SHU_EN		BIT(19)
	#define MISC_SPM_CTRL1_RG_PHYPLL2_SHU_EN	BIT(20)
	#define MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW	BIT(21)
	#define MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW	BIT(22)
	#define MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE	BIT(23)
	#define MISC_SPM_CTRL1_RG_DR_SHU_EN		BIT(24)
	#define MISC_SPM_CTRL1_RG_DDRPHY_DB_CK_CH0_EN	BIT(25)
	#define MISC_SPM_CTRL1_RG_DDRPHY_DB_CK_CH1_EN	BIT(26)
#define MISC_SPM_CTRL2					0x0000027c
	#define MISC_SPM_CTRL2_PHY_SPM_CTL2		GENMASK(31, 0)
#define MISC_SPM_CTRL3					0x00000280
	#define MISC_SPM_CTRL3_PHY_SPM_CTL3		GENMASK(31, 0)
#define MISC_CG_CTRL0					0x00000284
	#define MISC_CG_CTRL0_W_CHG_MEM			BIT(0)
	#define MISC_CG_CTRL0_CLK_MEM_SEL		GENMASK(5, 4)
	#define MISC_CG_CTRL0_CLK_MEM_INV		BIT(6)
	#define MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE	BIT(8)
	#define MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE	BIT(9)
	#define MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE	BIT(10)
	#define MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE	BIT(11)
	#define MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE	BIT(12)
	#define MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE	BIT(13)
	#define MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE	BIT(14)
	#define MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE	BIT(15)
	#define MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE	BIT(16)
	#define MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE	BIT(17)
	#define MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN	BIT(18)
	#define MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE	BIT(19)
	#define MISC_CG_CTRL0_RG_CG_DRAMC_CHB_CK_OFF	BIT(20)
	#define MISC_CG_CTRL0_RG_DBG_OUT_SEL		BIT(21)
	#define MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF	BIT(22)
	#define MISC_CG_CTRL0_RG_DA_RREF_CK_SEL		BIT(28)
	#define MISC_CG_CTRL0_RG_FREERUN_MCK_CG		BIT(29)
	#define MISC_CG_CTRL0_RG_FREERUN_MCK_CHB_SEL	BIT(30)
	#define MISC_CG_CTRL0_CLK_MEM_DFS_CFG	GENMASK(31, 0) //cc add
#define MISC_CG_CTRL1					0x00000288
	#define MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL	GENMASK(31, 0)
#define MISC_CG_CTRL2					0x0000028c
	#define MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG	BIT(0)
	#define MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL	GENMASK(5, 1)
	#define MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON	BIT(6)
	#define MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN		BIT(7)
	#define MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN		BIT(8)
	#define MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT	GENMASK(15, 9)
	#define MISC_CG_CTRL2_RG_MEM_DCM_FSEL		GENMASK(20, 16)
	#define MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL	GENMASK(25, 21)
	#define MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF	BIT(26)
	#define MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE	BIT(28)
	#define MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE	BIT(29)
	#define MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE	BIT(31)
	#define MISC_CG_CTRL2_RG_MEM_DCM_CTL		GENMASK(31, 0)
#define MISC_CG_CTRL3					0x00000290
	#define MISC_CG_CTRL3_R_LBK_CG_CTRL		GENMASK(31, 0)
#define MISC_CG_CTRL4					0x00000294
	#define MISC_CG_CTRL4_R_PHY_MCK_CG_CTRL		GENMASK(31, 0)
#define MISC_CG_CTRL5					0x00000298
	#define MISC_CG_CTRL5_RESERVE			GENMASK(15, 0)
	#define MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN		BIT(16)
	#define MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN		BIT(17)
	#define MISC_CG_CTRL5_R_CA_DLY_DCM_EN		BIT(18)
	#define MISC_CG_CTRL5_R_DQ1_PI_DCM_EN		BIT(20)
	#define MISC_CG_CTRL5_R_DQ0_PI_DCM_EN		BIT(21)
	#define MISC_CG_CTRL5_R_CA_PI_DCM_EN		BIT(22)
#define MISC_CTRL0					0x0000029c
	#define MISC_CTRL0_R_DMDQSIEN_SYNCOPT		GENMASK(3, 0)
	#define MISC_CTRL0_R_DMDQSIEN_OUTSEL		GENMASK(7, 4)
	#define MISC_CTRL0_R_DMSTBEN_SYNCOPT		BIT(8)
	#define MISC_CTRL0_R_DMSTBEN_OUTSEL		BIT(9)
	#define MISC_CTRL0_IMPCAL_CHAB_EN		BIT(10)
	#define MISC_CTRL0_R_DMVALID_DLY_OPT		BIT(11)
	#define MISC_CTRL0_R_DMVALID_NARROW_IG		BIT(12)
	#define MISC_CTRL0_R_DMVALID_DLY		GENMASK(15, 13)
	#define MISC_CTRL0_R_DMDQSIEN_DEPTH_HALF	BIT(16)
	#define MISC_CTRL0_R_DMRDSEL_DIV2_OPT		BIT(17)
	#define MISC_CTRL0_IMPCAL_LP_ECO_OPT		BIT(18)
	#define MISC_CTRL0_IMPCAL_CDC_ECO_OPT		BIT(19)
	#define MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT		BIT(20)
	#define MISC_CTRL0_IMPCAL_CTL_CK_SEL		BIT(21)
	#define MISC_CTRL0_R_DMDQSIEN_FIFO_EN		BIT(24)
	#define MISC_CTRL0_R_DMSTBENCMP_FIFO_EN		BIT(25)
	#define MISC_CTRL0_R_DMSTBENCMP_RK_FIFO_EN	BIT(26)
	#define MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF	BIT(27)
	#define MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL	BIT(28)
	#define MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL	BIT(29)
	#define MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL	BIT(30)
	#define MISC_CTRL0_R_STBENCMP_DIV4CK_EN		BIT(31)
#define MISC_CTRL1					0x000002a0
	#define MISC_CTRL1_R_DMPHYRST			BIT(1)
	#define MISC_CTRL1_R_DM_TX_ARCLK_OE		BIT(2)
	#define MISC_CTRL1_R_DM_TX_ARCMD_OE		BIT(3)
	#define MISC_CTRL1_R_DMMCTLPLL_CKSEL		GENMASK(5, 4)
	#define MISC_CTRL1_R_DMMUXCA			BIT(6)
	#define MISC_CTRL1_R_DMARPIDQ_SW		BIT(7)
	#define MISC_CTRL1_R_DMPINMUX			GENMASK(9, 8)
	#define MISC_CTRL1_R_DMARPICA_SW_UPDX		BIT(10)
	#define MISC_CTRL1_CK_BFE_DCM_EN		BIT(11)
	#define MISC_CTRL1_R_DMRRESETB_I_OPT		BIT(12)
	#define MISC_CTRL1_R_DMDA_RRESETB_I		BIT(13)
	#define MISC_CTRL1_R_DMMUXCA_SEC		BIT(14)
	#define MISC_CTRL1_R_DQ2DM_SWAP			BIT(15)
	#define MISC_CTRL1_R_DMDRAMCLKEN0		GENMASK(19, 16)
	#define MISC_CTRL1_R_DMDRAMCLKEN1		GENMASK(23, 20)
	#define MISC_CTRL1_R_DMDQSIENCG_EN		BIT(24)
	#define MISC_CTRL1_R_DMSTBENCMP_RK_OPT		BIT(25)
	#define MISC_CTRL1_R_WL_DOWNSP			BIT(26)
	#define MISC_CTRL1_R_DMODTDISOE_A		BIT(27)
	#define MISC_CTRL1_R_DMODTDISOE_B		BIT(28)
	#define MISC_CTRL1_R_DMODTDISOE_C		BIT(29)
	#define MISC_CTRL1_R_DMDA_RRESETB_E		BIT(31)
#define MISC_CTRL2					0x000002a4
	#define MISC_CTRL2_PLL_SHU_GP			GENMASK(1, 0)
#define MISC_CTRL3					0x000002a8
	#define MISC_CTRL3_ARPI_CG_CMD_OPT		GENMASK(1, 0)
	#define MISC_CTRL3_ARPI_CG_CLK_OPT		GENMASK(3, 2)
	#define MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT		BIT(4)
	#define MISC_CTRL3_ARPI_CG_MCK_CA_OPT		BIT(5)
	#define MISC_CTRL3_ARPI_CG_MCTL_CA_OPT		BIT(6)
	#define MISC_CTRL3_DDRPHY_MCK_MPDIV_CG_CA_SEL	GENMASK(9, 8)
	#define MISC_CTRL3_DRAM_CLK_NEW_CA_EN_SEL	GENMASK(15, 12)
	#define MISC_CTRL3_ARPI_CG_DQ_OPT		GENMASK(17, 16)
	#define MISC_CTRL3_ARPI_CG_DQS_OPT		GENMASK(19, 18)
	#define MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT		BIT(20)
	#define MISC_CTRL3_ARPI_CG_MCK_DQ_OPT		BIT(21)
	#define MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT		BIT(22)
	#define MISC_CTRL3_DDRPHY_MCK_MPDIV_CG_DQ_SEL	GENMASK(25, 24)
	#define MISC_CTRL3_R_DDRPHY_COMB_CG_IG		BIT(26)
	#define MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG	BIT(27)
	#define MISC_CTRL3_DRAM_CLK_NEW_DQ_EN_SEL	GENMASK(31, 28)
#define MISC_CTRL4					0x000002ac
	#define MISC_CTRL4_RG_PW_CON_CHA_0		GENMASK(31, 0)
#define MISC_CTRL5					0x000002b0
	#define MISC_CTRL5_RG_PW_CON_CHA_1		GENMASK(31, 0)
#define MISC_EXTLB_RX0					0x000002b4
	#define MISC_EXTLB_RX0_R_EXTLB_LFSR_RX_INI_0	GENMASK(15, 0)
	#define MISC_EXTLB_RX0_R_EXTLB_LFSR_RX_INI_1	GENMASK(31, 16)
#define MISC_EXTLB_RX1					0x000002b8
	#define MISC_EXTLB_RX1_R_EXTLB_LFSR_RX_INI_2	GENMASK(15, 0)
	#define MISC_EXTLB_RX1_R_EXTLB_LFSR_RX_INI_3	GENMASK(31, 16)
#define MISC_EXTLB_RX2					0x000002bc
	#define MISC_EXTLB_RX2_R_EXTLB_LFSR_RX_INI_4	GENMASK(15, 0)
	#define MISC_EXTLB_RX2_R_EXTLB_LFSR_RX_INI_5	GENMASK(31, 16)
#define MISC_EXTLB_RX3					0x000002c0
	#define MISC_EXTLB_RX3_R_EXTLB_LFSR_RX_INI_6	GENMASK(15, 0)
	#define MISC_EXTLB_RX3_R_EXTLB_LFSR_RX_INI_7	GENMASK(31, 16)
#define MISC_EXTLB_RX4					0x000002c4
	#define MISC_EXTLB_RX4_R_EXTLB_LFSR_RX_INI_8	GENMASK(15, 0)
	#define MISC_EXTLB_RX4_R_EXTLB_LFSR_RX_INI_9	GENMASK(31, 16)
#define MISC_EXTLB_RX5					0x000002c8
	#define MISC_EXTLB_RX5_R_EXTLB_LFSR_RX_INI_10	GENMASK(15, 0)
	#define MISC_EXTLB_RX5_R_EXTLB_LFSR_RX_INI_11	GENMASK(31, 16)
#define MISC_EXTLB_RX6					0x000002cc
	#define MISC_EXTLB_RX6_R_EXTLB_LFSR_RX_INI_12	GENMASK(15, 0)
	#define MISC_EXTLB_RX6_R_EXTLB_LFSR_RX_INI_13	GENMASK(31, 16)
#define MISC_EXTLB_RX7					0x000002d0
	#define MISC_EXTLB_RX7_R_EXTLB_LFSR_RX_INI_14	GENMASK(15, 0)
	#define MISC_EXTLB_RX7_R_EXTLB_LFSR_RX_INI_15	GENMASK(31, 16)
#define MISC_EXTLB_RX8					0x000002d4
	#define MISC_EXTLB_RX8_R_EXTLB_LFSR_RX_INI_16	GENMASK(15, 0)
	#define MISC_EXTLB_RX8_R_EXTLB_LFSR_RX_INI_17	GENMASK(31, 16)
#define MISC_EXTLB_RX9					0x000002d8
	#define MISC_EXTLB_RX9_R_EXTLB_LFSR_RX_INI_18	GENMASK(15, 0)
	#define MISC_EXTLB_RX9_R_EXTLB_LFSR_RX_INI_19	GENMASK(31, 16)
#define MISC_EXTLB_RX10					0x000002dc
	#define MISC_EXTLB_RX10_R_EXTLB_LFSR_RX_INI_20	GENMASK(15, 0)
	#define MISC_EXTLB_RX10_R_EXTLB_LFSR_RX_INI_21	GENMASK(31, 16)
#define MISC_EXTLB_RX11					0x000002e0
	#define MISC_EXTLB_RX11_R_EXTLB_LFSR_RX_INI_22	GENMASK(15, 0)
	#define MISC_EXTLB_RX11_R_EXTLB_LFSR_RX_INI_23	GENMASK(31, 16)
#define MISC_EXTLB_RX12					0x000002e4
	#define MISC_EXTLB_RX12_R_EXTLB_LFSR_RX_INI_24	GENMASK(15, 0)
	#define MISC_EXTLB_RX12_R_EXTLB_LFSR_RX_INI_25	GENMASK(31, 16)
#define MISC_EXTLB_RX13					0x000002e8
	#define MISC_EXTLB_RX13_R_EXTLB_LFSR_RX_INI_26	GENMASK(15, 0)
	#define MISC_EXTLB_RX13_R_EXTLB_LFSR_RX_INI_27	GENMASK(31, 16)
#define MISC_EXTLB_RX14					0x000002ec
	#define MISC_EXTLB_RX14_R_EXTLB_LFSR_RX_INI_28	GENMASK(15, 0)
	#define MISC_EXTLB_RX14_R_EXTLB_LFSR_RX_INI_29	GENMASK(31, 16)
#define MISC_EXTLB_RX15					0x000002f0
	#define MISC_EXTLB_RX15_R_EXTLB_LFSR_RX_INI_30	GENMASK(15, 0)
	#define MISC_EXTLB_RX15_MISC_EXTLB_RX15_RFU	GENMASK(31, 16)
#define MISC_EXTLB_RX16					0x000002f4
	#define MISC_EXTLB_RX16_R_EXTLB_RX_GATE_DELSEL_DQB0	GENMASK(6, 0)
	#define MISC_EXTLB_RX16_R_EXTLB_RX_GATE_DELSEL_DQB1	GENMASK(14, 8)
	#define MISC_EXTLB_RX16_R_EXTLB_RX_GATE_DELSEL_CA	GENMASK(22, 16)
#define MISC_EXTLB_RX17					0x000002f8
	#define MISC_EXTLB_RX17_R_XTALK_RX_00_TOG_CYCLE	GENMASK(3, 0)
	#define MISC_EXTLB_RX17_R_XTALK_RX_01_TOG_CYCLE	GENMASK(7, 4)
	#define MISC_EXTLB_RX17_R_XTALK_RX_02_TOG_CYCLE	GENMASK(11, 8)
	#define MISC_EXTLB_RX17_R_XTALK_RX_03_TOG_CYCLE	GENMASK(15, 12)
	#define MISC_EXTLB_RX17_R_XTALK_RX_04_TOG_CYCLE	GENMASK(19, 16)
	#define MISC_EXTLB_RX17_R_XTALK_RX_05_TOG_CYCLE	GENMASK(23, 20)
	#define MISC_EXTLB_RX17_R_XTALK_RX_06_TOG_CYCLE	GENMASK(27, 24)
	#define MISC_EXTLB_RX17_R_XTALK_RX_07_TOG_CYCLE	GENMASK(31, 28)
#define MISC_EXTLB_RX18					0x000002fc
	#define MISC_EXTLB_RX18_R_XTALK_RX_08_TOG_CYCLE	GENMASK(3, 0)
	#define MISC_EXTLB_RX18_R_XTALK_RX_09_TOG_CYCLE	GENMASK(7, 4)
	#define MISC_EXTLB_RX18_R_XTALK_RX_10_TOG_CYCLE	GENMASK(11, 8)
	#define MISC_EXTLB_RX18_R_XTALK_RX_11_TOG_CYCLE	GENMASK(15, 12)
	#define MISC_EXTLB_RX18_R_XTALK_RX_12_TOG_CYCLE	GENMASK(19, 16)
	#define MISC_EXTLB_RX18_R_XTALK_RX_13_TOG_CYCLE	GENMASK(23, 20)
	#define MISC_EXTLB_RX18_R_XTALK_RX_14_TOG_CYCLE	GENMASK(27, 24)
	#define MISC_EXTLB_RX18_R_XTALK_RX_15_TOG_CYCLE	GENMASK(31, 28)
#define MISC_EXTLB_RX19					0x00000300
	#define MISC_EXTLB_RX19_R_XTALK_RX_16_TOG_CYCLE	GENMASK(3, 0)
	#define MISC_EXTLB_RX19_R_XTALK_RX_17_TOG_CYCLE	GENMASK(7, 4)
	#define MISC_EXTLB_RX19_R_XTALK_RX_18_TOG_CYCLE	GENMASK(11, 8)
	#define MISC_EXTLB_RX19_R_XTALK_RX_19_TOG_CYCLE	GENMASK(15, 12)
	#define MISC_EXTLB_RX19_R_XTALK_RX_20_TOG_CYCLE	GENMASK(19, 16)
	#define MISC_EXTLB_RX19_R_XTALK_RX_21_TOG_CYCLE	GENMASK(23, 20)
	#define MISC_EXTLB_RX19_R_XTALK_RX_22_TOG_CYCLE	GENMASK(27, 24)
	#define MISC_EXTLB_RX19_R_XTALK_RX_23_TOG_CYCLE	GENMASK(31, 28)
#define MISC_EXTLB_RX20					0x00000304
	#define MISC_EXTLB_RX20_R_XTALK_RX_24_TOG_CYCLE	GENMASK(3, 0)
	#define MISC_EXTLB_RX20_R_XTALK_RX_25_TOG_CYCLE	GENMASK(7, 4)
	#define MISC_EXTLB_RX20_R_XTALK_RX_26_TOG_CYCLE	GENMASK(11, 8)
	#define MISC_EXTLB_RX20_R_XTALK_RX_27_TOG_CYCLE	GENMASK(15, 12)
	#define MISC_EXTLB_RX20_R_XTALK_RX_28_TOG_CYCLE	GENMASK(19, 16)
	#define MISC_EXTLB_RX20_R_XTALK_RX_29_TOG_CYCLE	GENMASK(23, 20)
	#define MISC_EXTLB_RX20_R_XTALK_RX_30_TOG_CYCLE	GENMASK(27, 24)
	#define MISC_EXTLB_RX20_R_XTALK_RX_31_TOG_CYCLE	GENMASK(31, 28)
#define CKMUX_SEL					0x00000308
	#define CKMUX_SEL_R_PHYCTRLMUX			BIT(0)
	#define CKMUX_SEL_R_PHYCTRLDCM			BIT(1)
	#define CKMUX_SEL_FB_CK_MUX			GENMASK(17, 16)
	#define CKMUX_SEL_FMEM_CK_MUX			GENMASK(19, 18)
#define RFU_0X30C					0x0000030c
	#define RFU_0X30C_RESERVED_0X30C		GENMASK(31, 0)
#define RFU_0X310					0x00000310
	#define RFU_0X310_RESERVED_0X310		GENMASK(31, 0)
#define RFU_0X314					0x00000314
	#define RFU_0X314_RESERVED_0X314		GENMASK(31, 0)
#define RFU_0X318					0x00000318
	#define RFU_0X318_RESERVED_0X318		GENMASK(31, 0)
#define RFU_0X31C					0x0000031c
	#define RFU_0X31C_RESERVED_0X31C		GENMASK(31, 0)
#define RFU_0X320					0x00000320
	#define RFU_0X320_RESERVED_0X320		GENMASK(31, 0)
#define RFU_0X324					0x00000324
	#define RFU_0X324_RESERVED_0X324		GENMASK(31, 0)
#define RFU_0X328					0x00000328
	#define RFU_0X328_RESERVED_0X328		GENMASK(31, 0)
#define RFU_0X32C					0x0000032c
	#define RFU_0X32C_RESERVED_0X32C		GENMASK(31, 0)
#define RFU_0X330					0x00000330
	#define RFU_0X330_RESERVED_0X330		GENMASK(31, 0)
#define RFU_0X334					0x00000334
	#define RFU_0X334_RESERVED_0X334		GENMASK(31, 0)
#define RFU_0X338					0x00000338
	#define RFU_0X338_RESERVED_0X338		GENMASK(31, 0)
#define RFU_0X33C					0x0000033c
	#define RFU_0X33C_RESERVED_0X33C		GENMASK(31, 0)
#define MISC_STBERR_RK0_R				0x00000510
	#define MISC_STBERR_RK0_R_STBERR_RK0_R		GENMASK(15, 0)
	#define MISC_STBERR_RK0_R_STBENERR_ALL		BIT(16)
	#define MISC_STBERR_RK0_R_RX_ARDQ0_FIFO_STBEN_ERR_B0	BIT(24)
	#define MISC_STBERR_RK0_R_RX_ARDQ4_FIFO_STBEN_ERR_B0	BIT(25)
	#define MISC_STBERR_RK0_R_RX_ARDQ0_FIFO_STBEN_ERR_B1	BIT(26)
	#define MISC_STBERR_RK0_R_RX_ARDQ4_FIFO_STBEN_ERR_B1	BIT(27)
	#define MISC_STBERR_RK0_R_RX_ARCA0_FIFO_STBEN_ERR	BIT(28)
	#define MISC_STBERR_RK0_R_RX_ARCA4_FIFO_STBEN_ERR	BIT(29)
	#define MISC_STBERR_RK0_R_DA_RPHYPLLGP_CK_SEL	BIT(31)
#define MISC_STBERR_RK0_F				0x00000514
	#define MISC_STBERR_RK0_F_STBERR_RK0_F		GENMASK(15, 0)
#define MISC_STBERR_RK1_R				0x00000518
	#define MISC_STBERR_RK1_R_STBERR_RK1_R		GENMASK(15, 0)
#define MISC_STBERR_RK1_F				0x0000051c
	#define MISC_STBERR_RK1_F_STBERR_RK1_F		GENMASK(15, 0)
#define MISC_STBERR_RK2_R				0x00000520
	#define MISC_STBERR_RK2_R_STBERR_RK2_R		GENMASK(15, 0)
#define MISC_STBERR_RK2_F				0x00000524
	#define MISC_STBERR_RK2_F_STBERR_RK2_F		GENMASK(15, 0)
#define MISC_RXDVS0					0x000005e0
	#define MISC_RXDVS0_R_RX_DLY_TRACK_RO_SEL	GENMASK(2, 0)
	#define MISC_RXDVS0_R_DA_DQX_R_DLY_RO_SEL	GENMASK(11, 8)
	#define MISC_RXDVS0_R_DA_CAX_R_DLY_RO_SEL	GENMASK(15, 12)
#define MISC_RXDVS2					0x000005e8
	#define MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF	BIT(0)
	#define MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG	BIT(8)
	#define MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN	BIT(16)
	#define MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR	BIT(17)
	#define MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN	BIT(18)
#define RFU_0X5EC					0x000005ec
	#define RFU_0X5EC_RESERVED_0X5EC		GENMASK(31, 0)
#define B0_RXDVS0					0x000005f0
	#define B0_RXDVS0_R_RX_RANKINSEL_B0		BIT(0)
	#define B0_RXDVS0_B0_RXDVS0_RFU			GENMASK(3, 1)
	#define B0_RXDVS0_R_RX_RANKINCTL_B0		GENMASK(7, 4)
	#define B0_RXDVS0_R_DVS_SW_UP_B0		BIT(8)
	#define B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0	BIT(9)
	#define B0_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_B0	BIT(10)
	#define B0_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_B0	BIT(11)
	#define B0_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_B0	GENMASK(13, 12)
	#define B0_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_B0	GENMASK(18, 16)
	#define B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0	BIT(19)
	#define B0_RXDVS0_R_RX_DLY_RK_OPT_B0		GENMASK(21, 20)
	#define B0_RXDVS0_R_HWRESTORE_ENA_B0		BIT(22)
	#define B0_RXDVS0_R_HWSAVE_MODE_ENA_B0		BIT(24)
	#define B0_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_B0	BIT(26)
	#define B0_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_B0	BIT(27)
	#define B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0	BIT(28)
	#define B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0	BIT(29)
	#define B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0		BIT(30)
	#define B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0		BIT(31)
#define B0_RXDVS1					0x000005f4
	#define B0_RXDVS1_B0_RXDVS1_RFU			GENMASK(15, 0)
	#define B0_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_B0	BIT(16)
	#define B0_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B0	BIT(17)
#define RFU_0X5F8					0x000005f8
	#define RFU_0X5F8_RESERVED_0X5F8		GENMASK(31, 0)
#define RFU_0X5FC					0x000005fc
	#define RFU_0X5FC_RESERVED_0X5FC		GENMASK(31, 0)
#define R0_B0_RXDVS0					0x00000600
	#define R0_B0_RXDVS0_R_RK0_B0_DVS_LEAD_LAG_CNT_CLR	BIT(26)
	#define R0_B0_RXDVS0_R_RK0_B0_DVS_SW_CNT_CLR	BIT(27)
	#define R0_B0_RXDVS0_R_RK0_B0_DVS_SW_CNT_ENA	BIT(31)
#define R0_B0_RXDVS1					0x00000604
	#define R0_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG	GENMASK(15, 0)
	#define R0_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD	GENMASK(31, 16)
#define R0_B0_RXDVS2					0x00000608
	#define R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0	GENMASK(17, 16)
	#define R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0	GENMASK(19, 18)
	#define R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0	BIT(23)
	#define R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0	GENMASK(25, 24)
	#define R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0	GENMASK(27, 26)
	#define R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0	BIT(28)
	#define R0_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0	BIT(29)
	#define R0_B0_RXDVS2_R_RK0_DVS_MODE_B0		GENMASK(31, 30)
#define R0_B0_RXDVS7					0x0000061c
	#define R0_B0_RXDVS7_RG_RK0_ARDQ_MIN_DLY_B0	GENMASK(5, 0)
	#define R0_B0_RXDVS7_RG_RK0_ARDQ_MIN_DLY_B0_RFU	GENMASK(7, 6)
	#define R0_B0_RXDVS7_RG_RK0_ARDQ_MAX_DLY_B0	GENMASK(13, 8)
	#define R0_B0_RXDVS7_RG_RK0_ARDQ_MAX_DLY_B0_RFU	GENMASK(15, 14)
	#define R0_B0_RXDVS7_RG_RK0_ARDQS0_MIN_DLY_B0	GENMASK(22, 16)
	#define R0_B0_RXDVS7_RG_RK0_ARDQS0_MIN_DLY_B0_RFU	BIT(23)
	#define R0_B0_RXDVS7_RG_RK0_ARDQS0_MAX_DLY_B0	GENMASK(30, 24)
	#define R0_B0_RXDVS7_RG_RK0_ARDQS0_MAX_DLY_B0_RFU	BIT(31)
#define RFU_0X620					0x00000620
	#define RFU_0X620_RESERVED_0X620		GENMASK(31, 0)
#define RFU_0X624					0x00000624
	#define RFU_0X624_RESERVED_0X624		GENMASK(31, 0)
#define RFU_0X628					0x00000628
	#define RFU_0X628_RESERVED_0X628		GENMASK(31, 0)
#define RFU_0X62C					0x0000062c
	#define RFU_0X62C_RESERVED_0X62C		GENMASK(31, 0)
#define B1_RXDVS0					0x00000670
	#define B1_RXDVS0_R_RX_RANKINSEL_B1		BIT(0)
	#define B1_RXDVS0_B1_RXDVS0_RFU			GENMASK(3, 1)
	#define B1_RXDVS0_R_RX_RANKINCTL_B1		GENMASK(7, 4)
	#define B1_RXDVS0_R_DVS_SW_UP_B1		BIT(8)
	#define B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1	BIT(9)
	#define B1_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_B1	BIT(10)
	#define B1_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_B1	BIT(11)
	#define B1_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_B1	GENMASK(13, 12)
	#define B1_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_B1	GENMASK(18, 16)
	#define B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1	BIT(19)
	#define B1_RXDVS0_R_RX_DLY_RK_OPT_B1		GENMASK(21, 20)
	#define B1_RXDVS0_R_HWRESTORE_ENA_B1		BIT(22)
	#define B1_RXDVS0_R_HWSAVE_MODE_ENA_B1		BIT(24)
	#define B1_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_B1	BIT(26)
	#define B1_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_B1	BIT(27)
	#define B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1	BIT(28)
	#define B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1	BIT(29)
	#define B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1		BIT(30)
	#define B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1		BIT(31)
#define B1_RXDVS1					0x00000674
	#define B1_RXDVS1_B1_RXDVS1_RFU			GENMASK(15, 0)
	#define B1_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_B1	BIT(16)
	#define B1_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B1	BIT(17)
#define RFU_0X678					0x00000678
	#define RFU_0X678_RESERVED_0X678		GENMASK(31, 0)
#define RFU_0X67C					0x0000067c
	#define RFU_0X67C_RESERVED_0X67C		GENMASK(31, 0)
#define R0_B1_RXDVS0					0x00000680
	#define R0_B1_RXDVS0_R_RK0_B1_DVS_LEAD_LAG_CNT_CLR	BIT(26)
	#define R0_B1_RXDVS0_R_RK0_B1_DVS_SW_CNT_CLR	BIT(27)
	#define R0_B1_RXDVS0_R_RK0_B1_DVS_SW_CNT_ENA	BIT(31)
#define R0_B1_RXDVS1					0x00000684
	#define R0_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG	GENMASK(15, 0)
	#define R0_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD	GENMASK(31, 16)
#define R0_B1_RXDVS2					0x00000688
	#define R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1	GENMASK(17, 16)
	#define R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1	GENMASK(19, 18)
	#define R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1	BIT(23)
	#define R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1	GENMASK(25, 24)
	#define R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1	GENMASK(27, 26)
	#define R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1	BIT(28)
	#define R0_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1	BIT(29)
	#define R0_B1_RXDVS2_R_RK0_DVS_MODE_B1		GENMASK(31, 30)
#define R0_B1_RXDVS7					0x0000069c
	#define R0_B1_RXDVS7_RG_RK0_ARDQ_MIN_DLY_B1	GENMASK(5, 0)
	#define R0_B1_RXDVS7_RG_RK0_ARDQ_MIN_DLY_B1_RFU	GENMASK(7, 6)
	#define R0_B1_RXDVS7_RG_RK0_ARDQ_MAX_DLY_B1	GENMASK(13, 8)
	#define R0_B1_RXDVS7_RG_RK0_ARDQ_MAX_DLY_B1_RFU	GENMASK(15, 14)
	#define R0_B1_RXDVS7_RG_RK0_ARDQS0_MIN_DLY_B1	GENMASK(22, 16)
	#define R0_B1_RXDVS7_RG_RK0_ARDQS0_MIN_DLY_B1_RFU	BIT(23)
	#define R0_B1_RXDVS7_RG_RK0_ARDQS0_MAX_DLY_B1	GENMASK(30, 24)
	#define R0_B1_RXDVS7_RG_RK0_ARDQS0_MAX_DLY_B1_RFU	BIT(31)
#define RFU_0X6A0					0x000006a0
	#define RFU_0X6A0_RESERVED_0X6A0		GENMASK(31, 0)
#define RFU_0X6A4					0x000006a4
	#define RFU_0X6A4_RESERVED_0X6A4		GENMASK(31, 0)
#define RFU_0X6A8					0x000006a8
	#define RFU_0X6A8_RESERVED_0X6A8		GENMASK(31, 0)
#define RFU_0X6AC					0x000006ac
	#define RFU_0X6AC_RESERVED_0X6AC		GENMASK(31, 0)
#define CA_RXDVS0					0x000006f0
	#define CA_RXDVS0_R_RX_RANKINSEL_CA		BIT(0)
	#define CA_RXDVS0_CA_RXDVS0_RFU			GENMASK(3, 1)
	#define CA_RXDVS0_R_RX_RANKINCTL_CA		GENMASK(7, 4)
	#define CA_RXDVS0_R_DVS_SW_UP_CA		BIT(8)
	#define CA_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_CA	BIT(9)
	#define CA_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_CA	BIT(10)
	#define CA_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_CA	BIT(11)
	#define CA_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_CA	GENMASK(13, 12)
	#define CA_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_CA	GENMASK(18, 16)
	#define CA_RXDVS0_R_DMRXDVS_CNTCMP_OPT_CA	BIT(19)
	#define CA_RXDVS0_R_RX_DLY_RK_OPT_CA		GENMASK(21, 20)
	#define CA_RXDVS0_R_HWRESTORE_ENA_CA		BIT(22)
	#define CA_RXDVS0_R_HWSAVE_MODE_ENA_CA		BIT(24)
	#define CA_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_CA	BIT(26)
	#define CA_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_CA	BIT(27)
	#define CA_RXDVS0_R_RX_DLY_TRACK_CG_EN_CA	BIT(28)
	#define CA_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_CA	BIT(29)
	#define CA_RXDVS0_R_RX_DLY_TRACK_CLR_CA		BIT(30)
	#define CA_RXDVS0_R_RX_DLY_TRACK_ENA_CA		BIT(31)
#define CA_RXDVS1					0x000006f4
	#define CA_RXDVS1_CA_RXDVS1_RFU			GENMASK(15, 0)
	#define CA_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_CA	BIT(16)
	#define CA_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_CA	BIT(17)
#define RFU_0X6F8					0x000006f8
	#define RFU_0X6F8_RESERVED_0X6F8		GENMASK(31, 0)
#define RFU_0X6FC					0x000006fc
	#define RFU_0X6FC_RESERVED_0X6FC		GENMASK(31, 0)
#define R0_CA_RXDVS0					0x00000700
	#define R0_CA_RXDVS0_R_RK0_CA_DVS_LEAD_LAG_CNT_CLR	BIT(26)
	#define R0_CA_RXDVS0_R_RK0_CA_DVS_SW_CNT_CLR	BIT(27)
	#define R0_CA_RXDVS0_R_RK0_CA_DVS_SW_CNT_ENA	BIT(31)
#define R0_CA_RXDVS1					0x00000704
	#define R0_CA_RXDVS1_R_RK0_CA_DVS_TH_LAG	GENMASK(15, 0)
	#define R0_CA_RXDVS1_R_RK0_CA_DVS_TH_LEAD	GENMASK(31, 16)
#define R0_CA_RXDVS2					0x00000708
	#define R0_CA_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_CA	GENMASK(17, 16)
	#define R0_CA_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_CA	GENMASK(19, 18)
	#define R0_CA_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_CA	BIT(23)
	#define R0_CA_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_CA	GENMASK(25, 24)
	#define R0_CA_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_CA	GENMASK(27, 26)
	#define R0_CA_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_CA	BIT(28)
	#define R0_CA_RXDVS2_R_RK0_DVS_FDLY_MODE_CA	BIT(29)
	#define R0_CA_RXDVS2_R_RK0_DVS_MODE_CA		GENMASK(31, 30)
#define R0_CA_RXDVS9					0x00000724
	#define R0_CA_RXDVS9_RG_RK0_ARCMD_MIN_DLY	GENMASK(5, 0)
	#define R0_CA_RXDVS9_RG_RK0_ARCMD_MIN_DLY_RFU	GENMASK(7, 6)
	#define R0_CA_RXDVS9_RG_RK0_ARCMD_MAX_DLY	GENMASK(13, 8)
	#define R0_CA_RXDVS9_RG_RK0_ARCMD_MAX_DLY_RFU	GENMASK(15, 14)
	#define R0_CA_RXDVS9_RG_RK0_ARCLK_MIN_DLY	GENMASK(22, 16)
	#define R0_CA_RXDVS9_RG_RK0_ARCLK_MIN_DLY_RFU	BIT(23)
	#define R0_CA_RXDVS9_RG_RK0_ARCLK_MAX_DLY	GENMASK(30, 24)
	#define R0_CA_RXDVS9_RG_RK0_ARCLK_MAX_DLY_RFU	BIT(31)
#define RFU_0X728					0x00000728
	#define RFU_0X728_RESERVED_0X728		GENMASK(31, 0)
#define RFU_0X72C					0x0000072c
	#define RFU_0X72C_RESERVED_0X72C		GENMASK(31, 0)
#define R1_B0_RXDVS0					0x00000800
	#define R1_B0_RXDVS0_R_RK1_B0_DVS_LEAD_LAG_CNT_CLR	BIT(26)
	#define R1_B0_RXDVS0_R_RK1_B0_DVS_SW_CNT_CLR	BIT(27)
	#define R1_B0_RXDVS0_R_RK1_B0_DVS_SW_CNT_ENA	BIT(31)
#define R1_B0_RXDVS1					0x00000804
	#define R1_B0_RXDVS1_R_RK1_B0_DVS_TH_LAG	GENMASK(15, 0)
	#define R1_B0_RXDVS1_R_RK1_B0_DVS_TH_LEAD	GENMASK(31, 16)
#define R1_B0_RXDVS2					0x00000808
	#define R1_B0_RXDVS2_R_RK1_RX_DLY_FAL_DQS_SCALE_B0	GENMASK(17, 16)
	#define R1_B0_RXDVS2_R_RK1_RX_DLY_FAL_DQ_SCALE_B0	GENMASK(19, 18)
	#define R1_B0_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B0	BIT(23)
	#define R1_B0_RXDVS2_R_RK1_RX_DLY_RIS_DQS_SCALE_B0	GENMASK(25, 24)
	#define R1_B0_RXDVS2_R_RK1_RX_DLY_RIS_DQ_SCALE_B0	GENMASK(27, 26)
	#define R1_B0_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B0	BIT(28)
	#define R1_B0_RXDVS2_R_RK1_DVS_FDLY_MODE_B0	BIT(29)
	#define R1_B0_RXDVS2_R_RK1_DVS_MODE_B0		GENMASK(31, 30)
#define R1_B0_RXDVS7					0x0000081c
	#define R1_B0_RXDVS7_RG_RK1_ARDQ_MIN_DLY_B0	GENMASK(5, 0)
	#define R1_B0_RXDVS7_RG_RK1_ARDQ_MIN_DLY_B0_RFU	GENMASK(7, 6)
	#define R1_B0_RXDVS7_RG_RK1_ARDQ_MAX_DLY_B0	GENMASK(13, 8)
	#define R1_B0_RXDVS7_RG_RK1_ARDQ_MAX_DLY_B0_RFU	GENMASK(15, 14)
	#define R1_B0_RXDVS7_RG_RK1_ARDQS0_MIN_DLY_B0	GENMASK(22, 16)
	#define R1_B0_RXDVS7_RG_RK1_ARDQS0_MIN_DLY_B0_RFU	BIT(23)
	#define R1_B0_RXDVS7_RG_RK1_ARDQS0_MAX_DLY_B0	GENMASK(30, 24)
	#define R1_B0_RXDVS7_RG_RK1_ARDQS0_MAX_DLY_B0_RFU	BIT(31)
#define RFU_0X820					0x00000820
	#define RFU_0X820_RESERVED_0X820		GENMASK(31, 0)
#define RFU_0X824					0x00000824
	#define RFU_0X824_RESERVED_0X824		GENMASK(31, 0)
#define RFU_0X828					0x00000828
	#define RFU_0X828_RESERVED_0X828		GENMASK(31, 0)
#define RFU_0X82C					0x0000082c
	#define RFU_0X82C_RESERVED_0X82C		GENMASK(31, 0)
#define R1_B1_RXDVS0					0x00000880
	#define R1_B1_RXDVS0_R_RK1_B1_DVS_LEAD_LAG_CNT_CLR	BIT(26)
	#define R1_B1_RXDVS0_R_RK1_B1_DVS_SW_CNT_CLR	BIT(27)
	#define R1_B1_RXDVS0_R_RK1_B1_DVS_SW_CNT_ENA	BIT(31)
#define R1_B1_RXDVS1					0x00000884
	#define R1_B1_RXDVS1_R_RK1_B1_DVS_TH_LAG	GENMASK(15, 0)
	#define R1_B1_RXDVS1_R_RK1_B1_DVS_TH_LEAD	GENMASK(31, 16)
#define R1_B1_RXDVS2					0x00000888
	#define R1_B1_RXDVS2_R_RK1_RX_DLY_FAL_DQS_SCALE_B1	GENMASK(17, 16)
	#define R1_B1_RXDVS2_R_RK1_RX_DLY_FAL_DQ_SCALE_B1	GENMASK(19, 18)
	#define R1_B1_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B1	BIT(23)
	#define R1_B1_RXDVS2_R_RK1_RX_DLY_RIS_DQS_SCALE_B1	GENMASK(25, 24)
	#define R1_B1_RXDVS2_R_RK1_RX_DLY_RIS_DQ_SCALE_B1	GENMASK(27, 26)
	#define R1_B1_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B1	BIT(28)
	#define R1_B1_RXDVS2_R_RK1_DVS_FDLY_MODE_B1	BIT(29)
	#define R1_B1_RXDVS2_R_RK1_DVS_MODE_B1		GENMASK(31, 30)
#define R1_B1_RXDVS7					0x0000089c
	#define R1_B1_RXDVS7_RG_RK1_ARDQ_MIN_DLY_B1	GENMASK(5, 0)
	#define R1_B1_RXDVS7_RG_RK1_ARDQ_MIN_DLY_B1_RFU	GENMASK(7, 6)
	#define R1_B1_RXDVS7_RG_RK1_ARDQ_MAX_DLY_B1	GENMASK(13, 8)
	#define R1_B1_RXDVS7_RG_RK1_ARDQ_MAX_DLY_B1_RFU	GENMASK(15, 14)
	#define R1_B1_RXDVS7_RG_RK1_ARDQS0_MIN_DLY_B1	GENMASK(22, 16)
	#define R1_B1_RXDVS7_RG_RK1_ARDQS0_MIN_DLY_B1_RFU	BIT(23)
	#define R1_B1_RXDVS7_RG_RK1_ARDQS0_MAX_DLY_B1	GENMASK(30, 24)
	#define R1_B1_RXDVS7_RG_RK1_ARDQS0_MAX_DLY_B1_RFU	BIT(31)
#define RFU_0X8A0					0x000008a0
	#define RFU_0X8A0_RESERVED_0X8A0		GENMASK(31, 0)
#define RFU_0X8A4					0x000008a4
	#define RFU_0X8A4_RESERVED_0X8A4		GENMASK(31, 0)
#define RFU_0X8A8					0x000008a8
	#define RFU_0X8A8_RESERVED_0X8A8		GENMASK(31, 0)
#define RFU_0X8AC					0x000008ac
	#define RFU_0X8AC_RESERVED_0X8AC		GENMASK(31, 0)
#define R1_CA_RXDVS0					0x00000900
	#define R1_CA_RXDVS0_R_RK1_CA_DVS_LEAD_LAG_CNT_CLR	BIT(26)
	#define R1_CA_RXDVS0_R_RK1_CA_DVS_SW_CNT_CLR	BIT(27)
	#define R1_CA_RXDVS0_R_RK1_CA_DVS_SW_CNT_ENA	BIT(31)
#define R1_CA_RXDVS1					0x00000904
	#define R1_CA_RXDVS1_R_RK1_CA_DVS_TH_LAG	GENMASK(15, 0)
	#define R1_CA_RXDVS1_R_RK1_CA_DVS_TH_LEAD	GENMASK(31, 16)
#define R1_CA_RXDVS2					0x00000908
	#define R1_CA_RXDVS2_R_RK1_RX_DLY_FAL_DQS_SCALE_CA	GENMASK(17, 16)
	#define R1_CA_RXDVS2_R_RK1_RX_DLY_FAL_DQ_SCALE_CA	GENMASK(19, 18)
	#define R1_CA_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_CA	BIT(23)
	#define R1_CA_RXDVS2_R_RK1_RX_DLY_RIS_DQS_SCALE_CA	GENMASK(25, 24)
	#define R1_CA_RXDVS2_R_RK1_RX_DLY_RIS_DQ_SCALE_CA	GENMASK(27, 26)
	#define R1_CA_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_CA	BIT(28)
	#define R1_CA_RXDVS2_R_RK1_DVS_FDLY_MODE_CA	BIT(29)
	#define R1_CA_RXDVS2_R_RK1_DVS_MODE_CA		GENMASK(31, 30)
#define R1_CA_RXDVS9					0x00000924
	#define R1_CA_RXDVS9_RG_RK1_ARCMD_MIN_DLY	GENMASK(5, 0)
	#define R1_CA_RXDVS9_RG_RK1_ARCMD_MIN_DLY_RFU	GENMASK(7, 6)
	#define R1_CA_RXDVS9_RG_RK1_ARCMD_MAX_DLY	GENMASK(13, 8)
	#define R1_CA_RXDVS9_RG_RK1_ARCMD_MAX_DLY_RFU	GENMASK(15, 14)
	#define R1_CA_RXDVS9_RG_RK1_ARCLK_MIN_DLY	GENMASK(22, 16)
	#define R1_CA_RXDVS9_RG_RK1_ARCLK_MIN_DLY_RFU	BIT(23)
	#define R1_CA_RXDVS9_RG_RK1_ARCLK_MAX_DLY	GENMASK(30, 24)
	#define R1_CA_RXDVS9_RG_RK1_ARCLK_MAX_DLY_RFU	BIT(31)
#define RFU_0X928					0x00000928
	#define RFU_0X928_RESERVED_0X928		GENMASK(31, 0)
#define RFU_0X92C					0x0000092c
	#define RFU_0X92C_RESERVED_0X92C		GENMASK(31, 0)
#define R2_B0_RXDVS0					0x00000a00
	#define R2_B0_RXDVS0_R_RK2_B0_DVS_LEAD_LAG_CNT_CLR	BIT(26)
	#define R2_B0_RXDVS0_R_RK2_B0_DVS_SW_CNT_CLR	BIT(27)
	#define R2_B0_RXDVS0_R_RK2_B0_DVS_SW_CNT_ENA	BIT(31)
#define R2_B0_RXDVS1					0x00000a04
	#define R2_B0_RXDVS1_R_RK2_B0_DVS_TH_LAG	GENMASK(15, 0)
	#define R2_B0_RXDVS1_R_RK2_B0_DVS_TH_LEAD	GENMASK(31, 16)
#define R2_B0_RXDVS2					0x00000a08
	#define R2_B0_RXDVS2_R_RK2_RX_DLY_FAL_DQS_SCALE_B0	GENMASK(17, 16)
	#define R2_B0_RXDVS2_R_RK2_RX_DLY_FAL_DQ_SCALE_B0	GENMASK(19, 18)
	#define R2_B0_RXDVS2_R_RK2_RX_DLY_FAL_TRACK_GATE_ENA_B0	BIT(23)
	#define R2_B0_RXDVS2_R_RK2_RX_DLY_RIS_DQS_SCALE_B0	GENMASK(25, 24)
	#define R2_B0_RXDVS2_R_RK2_RX_DLY_RIS_DQ_SCALE_B0	GENMASK(27, 26)
	#define R2_B0_RXDVS2_R_RK2_RX_DLY_RIS_TRACK_GATE_ENA_B0	BIT(28)
	#define R2_B0_RXDVS2_R_RK2_DVS_FDLY_MODE_B0	BIT(29)
	#define R2_B0_RXDVS2_R_RK2_DVS_MODE_B0		GENMASK(31, 30)
#define R2_B0_RXDVS7					0x00000a1c
	#define R2_B0_RXDVS7_RG_RK2_ARDQ_MIN_DLY_B0	GENMASK(5, 0)
	#define R2_B0_RXDVS7_RG_RK2_ARDQ_MIN_DLY_B0_RFU	GENMASK(7, 6)
	#define R2_B0_RXDVS7_RG_RK2_ARDQ_MAX_DLY_B0	GENMASK(13, 8)
	#define R2_B0_RXDVS7_RG_RK2_ARDQ_MAX_DLY_B0_RFU	GENMASK(15, 14)
	#define R2_B0_RXDVS7_RG_RK2_ARDQS0_MIN_DLY_B0	GENMASK(22, 16)
	#define R2_B0_RXDVS7_RG_RK2_ARDQS0_MIN_DLY_B0_RFU	BIT(23)
	#define R2_B0_RXDVS7_RG_RK2_ARDQS0_MAX_DLY_B0	GENMASK(30, 24)
	#define R2_B0_RXDVS7_RG_RK2_ARDQS0_MAX_DLY_B0_RFU	BIT(31)
#define RFU_0XA20					0x00000a20
	#define RFU_0XA20_RESERVED_0XA20		GENMASK(31, 0)
#define RFU_0XA24					0x00000a24
	#define RFU_0XA24_RESERVED_0XA24		GENMASK(31, 0)
#define RFU_0XA28					0x00000a28
	#define RFU_0XA28_RESERVED_0XA28		GENMASK(31, 0)
#define RFU_0XA2C					0x00000a2c
	#define RFU_0XA2C_RESERVED_0XA2C		GENMASK(31, 0)
#define R2_B1_RXDVS0					0x00000a80
	#define R2_B1_RXDVS0_R_RK2_B1_DVS_LEAD_LAG_CNT_CLR	BIT(26)
	#define R2_B1_RXDVS0_R_RK2_B1_DVS_SW_CNT_CLR	BIT(27)
	#define R2_B1_RXDVS0_R_RK2_B1_DVS_SW_CNT_ENA	BIT(31)
#define R2_B1_RXDVS1					0x00000a84
	#define R2_B1_RXDVS1_R_RK2_B1_DVS_TH_LAG	GENMASK(15, 0)
	#define R2_B1_RXDVS1_R_RK2_B1_DVS_TH_LEAD	GENMASK(31, 16)
#define R2_B1_RXDVS2					0x00000a88
	#define R2_B1_RXDVS2_R_RK2_RX_DLY_FAL_DQS_SCALE_B1	GENMASK(17, 16)
	#define R2_B1_RXDVS2_R_RK2_RX_DLY_FAL_DQ_SCALE_B1	GENMASK(19, 18)
	#define R2_B1_RXDVS2_R_RK2_RX_DLY_FAL_TRACK_GATE_ENA_B1	BIT(23)
	#define R2_B1_RXDVS2_R_RK2_RX_DLY_RIS_DQS_SCALE_B1	GENMASK(25, 24)
	#define R2_B1_RXDVS2_R_RK2_RX_DLY_RIS_DQ_SCALE_B1	GENMASK(27, 26)
	#define R2_B1_RXDVS2_R_RK2_RX_DLY_RIS_TRACK_GATE_ENA_B1	BIT(28)
	#define R2_B1_RXDVS2_R_RK2_DVS_FDLY_MODE_B1	BIT(29)
	#define R2_B1_RXDVS2_R_RK2_DVS_MODE_B1		GENMASK(31, 30)
#define R2_B1_RXDVS7					0x00000a9c
	#define R2_B1_RXDVS7_RG_RK2_ARDQ_MIN_DLY_B1	GENMASK(5, 0)
	#define R2_B1_RXDVS7_RG_RK2_ARDQ_MIN_DLY_B1_RFU	GENMASK(7, 6)
	#define R2_B1_RXDVS7_RG_RK2_ARDQ_MAX_DLY_B1	GENMASK(13, 8)
	#define R2_B1_RXDVS7_RG_RK2_ARDQ_MAX_DLY_B1_RFU	GENMASK(15, 14)
	#define R2_B1_RXDVS7_RG_RK2_ARDQS0_MIN_DLY_B1	GENMASK(22, 16)
	#define R2_B1_RXDVS7_RG_RK2_ARDQS0_MIN_DLY_B1_RFU	BIT(23)
	#define R2_B1_RXDVS7_RG_RK2_ARDQS0_MAX_DLY_B1	GENMASK(30, 24)
	#define R2_B1_RXDVS7_RG_RK2_ARDQS0_MAX_DLY_B1_RFU	BIT(31)
#define RFU_0XAA0					0x00000aa0
	#define RFU_0XAA0_RESERVED_0XAA0		GENMASK(31, 0)
#define RFU_0XAA4					0x00000aa4
	#define RFU_0XAA4_RESERVED_0XAA4		GENMASK(31, 0)
#define RFU_0XAA8					0x00000aa8
	#define RFU_0XAA8_RESERVED_0XAA8		GENMASK(31, 0)
#define RFU_0XAAC					0x00000aac
	#define RFU_0XAAC_RESERVED_0XAAC		GENMASK(31, 0)
#define R2_CA_RXDVS0					0x00000b00
	#define R2_CA_RXDVS0_R_RK2_CA_DVS_LEAD_LAG_CNT_CLR	BIT(26)
	#define R2_CA_RXDVS0_R_RK2_CA_DVS_SW_CNT_CLR	BIT(27)
	#define R2_CA_RXDVS0_R_RK2_CA_DVS_SW_CNT_ENA	BIT(31)
#define R2_CA_RXDVS1					0x00000b04
	#define R2_CA_RXDVS1_R_RK2_CA_DVS_TH_LAG	GENMASK(15, 0)
	#define R2_CA_RXDVS1_R_RK2_CA_DVS_TH_LEAD	GENMASK(31, 16)
#define R2_CA_RXDVS2					0x00000b08
	#define R2_CA_RXDVS2_R_RK2_RX_DLY_FAL_DQS_SCALE_CA	GENMASK(17, 16)
	#define R2_CA_RXDVS2_R_RK2_RX_DLY_FAL_DQ_SCALE_CA	GENMASK(19, 18)
	#define R2_CA_RXDVS2_R_RK2_RX_DLY_FAL_TRACK_GATE_ENA_CA	BIT(23)
	#define R2_CA_RXDVS2_R_RK2_RX_DLY_RIS_DQS_SCALE_CA	GENMASK(25, 24)
	#define R2_CA_RXDVS2_R_RK2_RX_DLY_RIS_DQ_SCALE_CA	GENMASK(27, 26)
	#define R2_CA_RXDVS2_R_RK2_RX_DLY_RIS_TRACK_GATE_ENA_CA	BIT(28)
	#define R2_CA_RXDVS2_R_RK2_DVS_FDLY_MODE_CA	BIT(29)
	#define R2_CA_RXDVS2_R_RK2_DVS_MODE_CA		GENMASK(31, 30)
#define R2_CA_RXDVS9					0x00000b24
	#define R2_CA_RXDVS9_RG_RK2_ARCMD_MIN_DLY	GENMASK(5, 0)
	#define R2_CA_RXDVS9_RG_RK2_ARCMD_MIN_DLY_RFU	GENMASK(7, 6)
	#define R2_CA_RXDVS9_RG_RK2_ARCMD_MAX_DLY	GENMASK(13, 8)
	#define R2_CA_RXDVS9_RG_RK2_ARCMD_MAX_DLY_RFU	GENMASK(15, 14)
	#define R2_CA_RXDVS9_RG_RK2_ARCLK_MIN_DLY	GENMASK(22, 16)
	#define R2_CA_RXDVS9_RG_RK2_ARCLK_MIN_DLY_RFU	BIT(23)
	#define R2_CA_RXDVS9_RG_RK2_ARCLK_MAX_DLY	GENMASK(30, 24)
	#define R2_CA_RXDVS9_RG_RK2_ARCLK_MAX_DLY_RFU	BIT(31)
#define RFU_0XB28					0x00000b28
	#define RFU_0XB28_RESERVED_0XB28		GENMASK(31, 0)
#define RFU_0XB2C					0x00000b2c
	#define RFU_0XB2C_RESERVED_0XB2C		GENMASK(31, 0)
#define SHU1_B0_DQ0					0x00000c00
	#define SHU1_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0	BIT(4)
	#define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0	GENMASK(10, 8)
	#define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0_BIT2 BIT(10)//[10:10]	 //Francis added
	#define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0_BIT1 BIT(9)//[9:9]    //Francis added
	#define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0_BIT0 BIT(8)//[8:8]    //Francis added
	#define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0	GENMASK(14, 12)
	#define SHU1_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0	BIT(20)
	#define SHU1_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0	GENMASK(26, 24)
	#define SHU1_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0	GENMASK(30, 28)
	#define SHU1_B0_DQ0_R_LP4Y_WDN_MODE_DQS0	BIT(31)
#define SHU1_B0_DQ1					0x00000c04
	#define SHU1_B0_DQ1_RG_TX_ARDQ_DRVP_B0		GENMASK(4, 0)
	#define SHU1_B0_DQ1_RG_TX_ARDQ_DRVN_B0		GENMASK(12, 8)
	#define SHU1_B0_DQ1_RG_TX_ARDQ_ODTP_B0		GENMASK(20, 16)
	#define SHU1_B0_DQ1_RG_TX_ARDQ_ODTN_B0		GENMASK(28, 24)
#define SHU1_B0_DQ2					0x00000c08
	#define SHU1_B0_DQ2_RG_TX_ARDQS0_DRVP_B0	GENMASK(4, 0)
	#define SHU1_B0_DQ2_RG_TX_ARDQS0_DRVN_B0	GENMASK(12, 8)
	#define SHU1_B0_DQ2_RG_TX_ARDQS0_ODTP_B0	GENMASK(20, 16)
	#define SHU1_B0_DQ2_RG_TX_ARDQS0_ODTN_B0	GENMASK(28, 24)
#define SHU1_B0_DQ3					0x00000c0c
	#define SHU1_B0_DQ3_RG_TX_ARDQS0_PU_B0		GENMASK(1, 0)
	#define SHU1_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0	GENMASK(3, 2)
	#define SHU1_B0_DQ3_RG_TX_ARDQS0_PDB_B0		GENMASK(5, 4)
	#define SHU1_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0	GENMASK(7, 6)
	#define SHU1_B0_DQ3_RG_TX_ARDQ_PU_B0		GENMASK(9, 8)
	#define SHU1_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0	GENMASK(11, 10)
	#define SHU1_B0_DQ3_RG_TX_ARDQ_PDB_B0		GENMASK(13, 12)
	#define SHU1_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0	GENMASK(15, 14)
#define SHU1_B0_DQ4					0x00000c10
	#define SHU1_B0_DQ4_RG_ARPI_AA_MCK_DL_B0	GENMASK(5, 0)
	#define SHU1_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0	GENMASK(13, 8)
	#define SHU1_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0	GENMASK(21, 16)
#define SHU1_B0_DQ5					0x00000c14
	#define SHU1_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0	GENMASK(5, 0)
	#define SHU1_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0	BIT(6)
	#define SHU1_B0_DQ5_RG_ARPI_FB_B0		GENMASK(13, 8)
	#define SHU1_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0	GENMASK(18, 16)
	#define SHU1_B0_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B0	BIT(19)
	#define SHU1_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0	GENMASK(22, 20)
	#define SHU1_B0_DQ5_RG_ARPI_MCTL_B0		GENMASK(29, 24)
#define SHU1_B0_DQ6					0x00000c18
	#define SHU1_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0	GENMASK(5, 0)
	#define SHU1_B0_DQ6_RG_ARPI_RESERVE_B0		GENMASK(21, 6)
	#define SHU1_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0	GENMASK(23, 22)
	#define SHU1_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0	GENMASK(25, 24)
	#define SHU1_B0_DQ6_RG_ARPI_MIDPI_EN_B0		BIT(26)
	#define SHU1_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0	BIT(27)
	#define SHU1_B0_DQ6_RG_ARPI_CAP_SEL_B0		GENMASK(29, 28)
	#define SHU1_B0_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B0	BIT(31)
#define SHU1_B0_DQ7					0x00000c1c
	#define SHU1_B0_DQ7_R_DMRANKRXDVS_B0		GENMASK(3, 0)
	#define SHU1_B0_DQ7_MIDPI_ENABLE		BIT(4)
	#define SHU1_B0_DQ7_MIDPI_DIV4_ENABLE		BIT(5)
	#define SHU1_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0	BIT(6)
	#define SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0		BIT(7)
	#define SHU1_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0	GENMASK(11, 8)
	#define SHU1_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0	BIT(12)
	#define SHU1_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0	BIT(13)
	#define SHU1_B0_DQ7_R_DMRXTRACK_DQM_EN_B0	BIT(14)
	#define SHU1_B0_DQ7_R_DMRODTEN_B0		BIT(15)
	#define SHU1_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0	BIT(16)
	#define SHU1_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0	BIT(17)
	#define SHU1_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0	BIT(18)
	#define SHU1_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0	BIT(19)
	#define SHU1_B0_DQ7_R_LP4Y_SDN_MODE_DQS0	BIT(20)
	#define SHU1_B0_DQ7_R_DMRXRANK_DQ_EN_B0		BIT(24)
	#define SHU1_B0_DQ7_R_DMRXRANK_DQ_LAT_B0	GENMASK(27, 25)
	#define SHU1_B0_DQ7_R_DMRXRANK_DQS_EN_B0	BIT(28)
	#define SHU1_B0_DQ7_R_DMRXRANK_DQS_LAT_B0	GENMASK(31, 29)
#define SHU1_B0_DQ8					0x00000c20
	#define SHU1_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0	GENMASK(14, 0)
	#define SHU1_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0	BIT(15)
	#define SHU1_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0	BIT(19)
	#define SHU1_B0_DQ8_R_RMRODTEN_CG_IG_B0		BIT(20)
	#define SHU1_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0	BIT(21)
	#define SHU1_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0	BIT(22)
	#define SHU1_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0	BIT(23)
	#define SHU1_B0_DQ8_R_DMRXDLY_CG_IG_B0		BIT(24)
	#define SHU1_B0_DQ8_R_DMSTBEN_SYNC_CG_IG_B0	BIT(25)
	#define SHU1_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0	BIT(26)
	#define SHU1_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0	BIT(27)
	#define SHU1_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0	BIT(28)
	#define SHU1_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0	BIT(29)
	#define SHU1_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0	BIT(30)
	#define SHU1_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0	BIT(31)
#define SHU1_B0_DQ9					0x00000c24
	#define SHU1_B0_DQ9_RESERVED_0XC24		GENMASK(31, 0)
#define SHU1_B0_DQ10					0x00000c28
	#define SHU1_B0_DQ10_RESERVED_0XC28		GENMASK(31, 0)
#define SHU1_B0_DQ11					0x00000c2c
	#define SHU1_B0_DQ11_RESERVED_0XC2C		GENMASK(31, 0)
#define SHU1_B0_DQ12					0x00000c30
	#define SHU1_B0_DQ12_RESERVED_0XC30		GENMASK(31, 0)
#define SHU1_B0_DLL0					0x00000c34
	#define SHU1_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU	BIT(0)
	#define SHU1_B0_DLL0_B0_DLL0_RFU		BIT(3)
	#define SHU1_B0_DLL0_RG_ARDLL_FAST_PSJP_B0	BIT(4)
	#define SHU1_B0_DLL0_RG_ARDLL_PHDIV_B0		BIT(9)
	#define SHU1_B0_DLL0_RG_ARDLL_PHJUMP_EN_B0	BIT(10)
	#define SHU1_B0_DLL0_RG_ARDLL_P_GAIN_B0		GENMASK(15, 12)
	#define SHU1_B0_DLL0_RG_ARDLL_IDLECNT_B0	GENMASK(19, 16)
	#define SHU1_B0_DLL0_RG_ARDLL_GAIN_B0		GENMASK(23, 20)
	#define SHU1_B0_DLL0_RG_ARDLL_PHDET_IN_SWAP_B0	BIT(30)
	#define SHU1_B0_DLL0_RG_ARDLL_PHDET_OUT_SEL_B0	BIT(31)
#define SHU1_B0_DLL1					0x00000c38
	#define SHU1_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0	BIT(0)
	#define SHU1_B0_DLL1_RG_ARDLL_PS_EN_B0		BIT(1)
	#define SHU1_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0	BIT(2)
	#define SHU1_B0_DLL1_RG_ARDQ_REV_B0		GENMASK(31, 8)
#define SHU1_B1_DQ0					0x00000c80
	#define SHU1_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1	BIT(4)
	#define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1	GENMASK(10, 8)
	#define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1_BIT2 BIT(10)//[10:10]	 //Francis added
	#define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1_BIT1 BIT(9)//[9:9]    //Francis added
	#define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1_BIT0 BIT(8)//[8:8]    //Francis added
	#define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1	GENMASK(14, 12)
	#define SHU1_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1	BIT(20)
	#define SHU1_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1	GENMASK(26, 24)
	#define SHU1_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1	GENMASK(30, 28)
	#define SHU1_B1_DQ0_R_LP4Y_WDN_MODE_DQS1	BIT(31)
#define SHU1_B1_DQ1					0x00000c84
	#define SHU1_B1_DQ1_RG_TX_ARDQ_DRVP_B1		GENMASK(4, 0)
	#define SHU1_B1_DQ1_RG_TX_ARDQ_DRVN_B1		GENMASK(12, 8)
	#define SHU1_B1_DQ1_RG_TX_ARDQ_ODTP_B1		GENMASK(20, 16)
	#define SHU1_B1_DQ1_RG_TX_ARDQ_ODTN_B1		GENMASK(28, 24)
#define SHU1_B1_DQ2					0x00000c88
	#define SHU1_B1_DQ2_RG_TX_ARDQS0_DRVP_B1	GENMASK(4, 0)
	#define SHU1_B1_DQ2_RG_TX_ARDQS0_DRVN_B1	GENMASK(12, 8)
	#define SHU1_B1_DQ2_RG_TX_ARDQS0_ODTP_B1	GENMASK(20, 16)
	#define SHU1_B1_DQ2_RG_TX_ARDQS0_ODTN_B1	GENMASK(28, 24)
#define SHU1_B1_DQ3					0x00000c8c
	#define SHU1_B1_DQ3_RG_TX_ARDQS0_PU_B1		GENMASK(1, 0)
	#define SHU1_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1	GENMASK(3, 2)
	#define SHU1_B1_DQ3_RG_TX_ARDQS0_PDB_B1		GENMASK(5, 4)
	#define SHU1_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1	GENMASK(7, 6)
	#define SHU1_B1_DQ3_RG_TX_ARDQ_PU_B1		GENMASK(9, 8)
	#define SHU1_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1	GENMASK(11, 10)
	#define SHU1_B1_DQ3_RG_TX_ARDQ_PDB_B1		GENMASK(13, 12)
	#define SHU1_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1	GENMASK(15, 14)
#define SHU1_B1_DQ4					0x00000c90
	#define SHU1_B1_DQ4_RG_ARPI_AA_MCK_DL_B1	GENMASK(5, 0)
	#define SHU1_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1	GENMASK(13, 8)
	#define SHU1_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1	GENMASK(21, 16)
#define SHU1_B1_DQ5					0x00000c94
	#define SHU1_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1	GENMASK(5, 0)
	#define SHU1_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1	BIT(6)
	#define SHU1_B1_DQ5_RG_ARPI_FB_B1		GENMASK(13, 8)
	#define SHU1_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1	GENMASK(18, 16)
	#define SHU1_B1_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B1	BIT(19)
	#define SHU1_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1	GENMASK(22, 20)
	#define SHU1_B1_DQ5_RG_ARPI_MCTL_B1		GENMASK(29, 24)
#define SHU1_B1_DQ6					0x00000c98
	#define SHU1_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1	GENMASK(5, 0)
	#define SHU1_B1_DQ6_RG_ARPI_RESERVE_B1		GENMASK(21, 6)
	#define SHU1_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1	GENMASK(23, 22)
	#define SHU1_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1	GENMASK(25, 24)
	#define SHU1_B1_DQ6_RG_ARPI_MIDPI_EN_B1		BIT(26)
	#define SHU1_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1	BIT(27)
	#define SHU1_B1_DQ6_RG_ARPI_CAP_SEL_B1		GENMASK(29, 28)
	#define SHU1_B1_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B1	BIT(31)
#define SHU1_B1_DQ7					0x00000c9c
	#define SHU1_B1_DQ7_R_DMRANKRXDVS_B1		GENMASK(3, 0)
	#define SHU1_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1	BIT(6)
	#define SHU1_B1_DQ7_R_DMDQMDBI_SHU_B1		BIT(7)
	#define SHU1_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1	GENMASK(11, 8)
	#define SHU1_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1	BIT(12)
	#define SHU1_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1	BIT(13)
	#define SHU1_B1_DQ7_R_DMRXTRACK_DQM_EN_B1	BIT(14)
	#define SHU1_B1_DQ7_R_DMRODTEN_B1		BIT(15)
	#define SHU1_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1	BIT(16)
	#define SHU1_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1	BIT(17)
	#define SHU1_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1	BIT(18)
	#define SHU1_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1	BIT(19)
	#define SHU1_B1_DQ7_R_LP4Y_SDN_MODE_DQS1	BIT(20)
	#define SHU1_B1_DQ7_R_DMRXRANK_DQ_EN_B1		BIT(24)
	#define SHU1_B1_DQ7_R_DMRXRANK_DQ_LAT_B1	GENMASK(27, 25)
	#define SHU1_B1_DQ7_R_DMRXRANK_DQS_EN_B1	BIT(28)
	#define SHU1_B1_DQ7_R_DMRXRANK_DQS_LAT_B1	GENMASK(31, 29)
#define SHU1_B1_DQ8					0x00000ca0
	#define SHU1_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1	GENMASK(14, 0)
	#define SHU1_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1	BIT(15)
	#define SHU1_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1	BIT(19)
	#define SHU1_B1_DQ8_R_RMRODTEN_CG_IG_B1		BIT(20)
	#define SHU1_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1	BIT(21)
	#define SHU1_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1	BIT(22)
	#define SHU1_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1	BIT(23)
	#define SHU1_B1_DQ8_R_DMRXDLY_CG_IG_B1		BIT(24)
	#define SHU1_B1_DQ8_R_DMSTBEN_SYNC_CG_IG_B1	BIT(25)
	#define SHU1_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1	BIT(26)
	#define SHU1_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1	BIT(27)
	#define SHU1_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1	BIT(28)
	#define SHU1_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1	BIT(29)
	#define SHU1_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1	BIT(30)
	#define SHU1_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1	BIT(31)
#define SHU1_B1_DQ9					0x00000ca4
	#define SHU1_B1_DQ9_RESERVED_0XCA4		GENMASK(31, 0)
#define SHU1_B1_DQ10					0x00000ca8
	#define SHU1_B1_DQ10_RESERVED_0XCA8		GENMASK(31, 0)
#define SHU1_B1_DQ11					0x00000cac
	#define SHU1_B1_DQ11_RESERVED_0XCAC		GENMASK(31, 0)
#define SHU1_B1_DQ12					0x00000cb0
	#define SHU1_B1_DQ12_RESERVED_0XCB0		GENMASK(31, 0)
#define SHU1_B1_DLL0					0x00000cb4
	#define SHU1_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU	BIT(0)
	#define SHU1_B1_DLL0_B1_DLL0_RFU		BIT(3)
	#define SHU1_B1_DLL0_RG_ARDLL_FAST_PSJP_B1	BIT(4)
	#define SHU1_B1_DLL0_RG_ARDLL_PHDIV_B1		BIT(9)
	#define SHU1_B1_DLL0_RG_ARDLL_PHJUMP_EN_B1	BIT(10)
	#define SHU1_B1_DLL0_RG_ARDLL_P_GAIN_B1		GENMASK(15, 12)
	#define SHU1_B1_DLL0_RG_ARDLL_IDLECNT_B1	GENMASK(19, 16)
	#define SHU1_B1_DLL0_RG_ARDLL_GAIN_B1		GENMASK(23, 20)
	#define SHU1_B1_DLL0_RG_ARDLL_PHDET_IN_SWAP_B1	BIT(30)
	#define SHU1_B1_DLL0_RG_ARDLL_PHDET_OUT_SEL_B1	BIT(31)
#define SHU1_B1_DLL1					0x00000cb8
	#define SHU1_B1_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B1	BIT(0)
	#define SHU1_B1_DLL1_RG_ARDLL_PS_EN_B1		BIT(1)
	#define SHU1_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1	BIT(2)
	#define SHU1_B1_DLL1_RG_ARDQ_REV_B1		GENMASK(31, 8)
#define SHU1_CA_CMD0					0x00000d00
	#define SHU1_CA_CMD0_RG_TX_ARCLK_PRE_EN		BIT(4)
	#define SHU1_CA_CMD0_RG_TX_ARCLK_DRVP_PRE	GENMASK(10, 8)
	#define SHU1_CA_CMD0_RG_TX_ARCLK_DRVP_PRE_BIT2 BIT(10)//[10:10]    //Francis added
	#define SHU1_CA_CMD0_RG_TX_ARCLK_DRVP_PRE_BIT1 BIT(9)//[9:9]    //Francis added
	#define SHU1_CA_CMD0_RG_TX_ARCLK_DRVP_PRE_BIT0 BIT(8)//[8:8]    //Francis added
	#define SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE	GENMASK(14, 12)
	#define SHU1_CA_CMD0_RG_CGEN_FMEM_CK_CG_DLL	BIT(17)
	#define SHU1_CA_CMD0_RG_FB_CK_MUX		GENMASK(19, 18)
	#define SHU1_CA_CMD0_RG_TX_ARCMD_PRE_EN		BIT(20)
	#define SHU1_CA_CMD0_RG_TX_ARCMD_DRVP_PRE	GENMASK(26, 24)
	#define SHU1_CA_CMD0_RG_TX_ARCMD_DRVN_PRE	GENMASK(30, 28)
	#define SHU1_CA_CMD0_R_LP4Y_WDN_MODE_CLK	BIT(31)
#define SHU1_CA_CMD1					0x00000d04
	#define SHU1_CA_CMD1_RG_TX_ARCMD_DRVP		GENMASK(4, 0)
	#define SHU1_CA_CMD1_RG_TX_ARCMD_DRVN		GENMASK(12, 8)
	#define SHU1_CA_CMD1_RG_TX_ARCMD_ODTP		GENMASK(20, 16)
	#define SHU1_CA_CMD1_RG_TX_ARCMD_ODTN		GENMASK(28, 24)
#define SHU1_CA_CMD2					0x00000d08
	#define SHU1_CA_CMD2_RG_TX_ARCLK_DRVP		GENMASK(4, 0)
	#define SHU1_CA_CMD2_RG_TX_ARCLK_DRVN		GENMASK(12, 8)
	#define SHU1_CA_CMD2_RG_TX_ARCLK_ODTP		GENMASK(20, 16)
	#define SHU1_CA_CMD2_RG_TX_ARCLK_ODTN		GENMASK(28, 24)
#define SHU1_CA_CMD3					0x00000d0c
	#define SHU1_CA_CMD3_RG_TX_ARCLK_PU		GENMASK(1, 0)
	#define SHU1_CA_CMD3_RG_TX_ARCLK_PU_PRE		GENMASK(3, 2)
	#define SHU1_CA_CMD3_RG_TX_ARCLK_PDB		GENMASK(5, 4)
	#define SHU1_CA_CMD3_RG_TX_ARCLK_PDB_PRE	GENMASK(7, 6)
	#define SHU1_CA_CMD3_RG_TX_ARCMD_PU		GENMASK(9, 8)
	#define SHU1_CA_CMD3_RG_TX_ARCMD_PU_BIT1	BIT(9)//[9:9]	 //Francis added
	#define SHU1_CA_CMD3_RG_TX_ARCMD_PU_BIT0	BIT(8)//[8:8]	 //Francis added
	#define SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE		GENMASK(11, 10)
	#define SHU1_CA_CMD3_RG_TX_ARCMD_PDB		GENMASK(13, 12)
	#define SHU1_CA_CMD3_RG_TX_ARCMD_PDB_PRE	GENMASK(15, 14)
	#define SHU1_CA_CMD3_ARCMD_REV_BIT_06 		BIT(22)//[22:22]	//Francis added
	#define SHU1_CA_CMD3_ARCMD_REV_BIT_05 		BIT(21)//[21:21]	//Francis added
	#define SHU1_CA_CMD3_ARCMD_REV_BIT_04 		BIT(20)//[20:20]	//Francis added
	#define SHU1_CA_CMD3_ARCMD_REV_BIT_03 		BIT(19)//[19:19]	//Francis added
#define SHU1_CA_CMD4					0x00000d10
	#define SHU1_CA_CMD4_RG_ARPI_AA_MCK_DL_CA	GENMASK(5, 0)
	#define SHU1_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA	GENMASK(13, 8)
	#define SHU1_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA	GENMASK(21, 16)
#define SHU1_CA_CMD5					0x00000d14
	#define SHU1_CA_CMD5_RG_RX_ARCMD_VREF_SEL	GENMASK(5, 0)
	#define SHU1_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS	BIT(6)
	#define SHU1_CA_CMD5_RG_ARPI_FB_CA		GENMASK(13, 8)
	#define SHU1_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY	GENMASK(18, 16)
	#define SHU1_CA_CMD5_DA_RX_ARCLK_DQSIEN_RB_DLY	BIT(19)
	#define SHU1_CA_CMD5_RG_RX_ARCLK_DVS_DLY	GENMASK(22, 20)
	#define SHU1_CA_CMD5_RG_ARPI_MCTL_CA		GENMASK(29, 24)
#define SHU1_CA_CMD6					0x00000d18
	#define SHU1_CA_CMD6_RG_ARPI_OFFSET_CLKIEN	GENMASK(5, 0)
	#define SHU1_CA_CMD6_RG_ARPI_RESERVE_CA		GENMASK(21, 6)
	#define SHU1_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA	GENMASK(23, 22)
	#define SHU1_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA	GENMASK(25, 24)
	#define SHU1_CA_CMD6_RG_ARPI_MIDPI_EN_CA	BIT(26)
	#define SHU1_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA	BIT(27)
	#define SHU1_CA_CMD6_RG_ARPI_CAP_SEL_CA		GENMASK(29, 28)
	#define SHU1_CA_CMD6_RG_ARPI_MIDPI_BYPASS_EN_CA	BIT(31)
#define SHU1_CA_CMD7					0x00000d1c
	#define SHU1_CA_CMD7_R_DMRANKRXDVS_CA		GENMASK(3, 0)
	#define SHU1_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA	BIT(12)
	#define SHU1_CA_CMD7_R_DMRODTEN_CA		BIT(15)
	#define SHU1_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA	BIT(16)
	#define SHU1_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW	BIT(17)
	#define SHU1_CA_CMD7_R_DMTX_ARPI_CG_CLK_NEW	BIT(18)
	#define SHU1_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW	BIT(19)
	#define SHU1_CA_CMD7_R_LP4Y_SDN_MODE_CLK	BIT(20)
	#define SHU1_CA_CMD7_R_DMRXRANK_CMD_EN		BIT(24)
	#define SHU1_CA_CMD7_R_DMRXRANK_CMD_LAT		GENMASK(27, 25)
	#define SHU1_CA_CMD7_R_DMRXRANK_CLK_EN		BIT(28)
	#define SHU1_CA_CMD7_R_DMRXRANK_CLK_LAT		GENMASK(31, 29)
#define SHU1_CA_CMD8					0x00000d20
	#define SHU1_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA	GENMASK(14, 0)
	#define SHU1_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA	BIT(15)
	#define SHU1_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA	BIT(19)
	#define SHU1_CA_CMD8_R_RMRODTEN_CG_IG_CA	BIT(20)
	#define SHU1_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA	BIT(21)
	#define SHU1_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA	BIT(22)
	#define SHU1_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA	BIT(23)
	#define SHU1_CA_CMD8_R_DMRXDLY_CG_IG_CA		BIT(24)
	#define SHU1_CA_CMD8_R_DMSTBEN_SYNC_CG_IG_CA	BIT(25)
	#define SHU1_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA	BIT(26)
	#define SHU1_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA	BIT(27)
	#define SHU1_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA	BIT(28)
	#define SHU1_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA	BIT(29)
	#define SHU1_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA	BIT(30)
	#define SHU1_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA	BIT(31)
#define SHU1_CA_CMD9					0x00000d24
	#define SHU1_CA_CMD9_RESERVED_0XD24		GENMASK(31, 0)
#define SHU1_CA_CMD10					0x00000d28
	#define SHU1_CA_CMD10_RESERVED_0XD28		GENMASK(31, 0)
#define SHU1_CA_CMD11					0x00000d2c
	#define SHU1_CA_CMD11_RG_RIMP_REV		GENMASK(7, 0)
	#define SHU1_CA_CMD11_RG_RIMP_VREF_SEL		GENMASK(13, 8)
	#define SHU1_CA_CMD11_RG_TX_ARCKE_DRVP		GENMASK(21, 17)
	#define SHU1_CA_CMD11_RG_TX_ARCKE_DRVN		GENMASK(26, 22)
#define SHU1_CA_CMD12					0x00000d30
	#define SHU1_CA_CMD12_RESERVED_0XD30		GENMASK(31, 0)
#define SHU1_CA_DLL0					0x00000d34
	#define SHU1_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU	BIT(0)
	#define SHU1_CA_DLL0_CA_DLL0_RFU		BIT(3)
	#define SHU1_CA_DLL0_RG_ARDLL_FAST_PSJP_CA	BIT(4)
	#define SHU1_CA_DLL0_RG_ARDLL_PHDIV_CA		BIT(9)
	#define SHU1_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA	BIT(10)
	#define SHU1_CA_DLL0_RG_ARDLL_P_GAIN_CA		GENMASK(15, 12)
	#define SHU1_CA_DLL0_RG_ARDLL_IDLECNT_CA	GENMASK(19, 16)
	#define SHU1_CA_DLL0_RG_ARDLL_GAIN_CA		GENMASK(23, 20)
	#define SHU1_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA	BIT(30)
	#define SHU1_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA	BIT(31)
#define SHU1_CA_DLL1					0x00000d38
	#define SHU1_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA	BIT(0)
	#define SHU1_CA_DLL1_RG_ARDLL_PS_EN_CA		BIT(1)
	#define SHU1_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA	BIT(2)
	#define SHU1_CA_DLL1_RG_ARCMD_REV		GENMASK(31, 8)
#define SHU1_MISC0					0x00000df0
	#define SHU1_MISC0_R_RX_PIPE_BYPASS_EN		BIT(1)
	#define SHU1_MISC0_RG_CMD_TXPIPE_BYPASS_EN	BIT(2)
	#define SHU1_MISC0_RG_CK_TXPIPE_BYPASS_EN	BIT(3)
	#define SHU1_MISC0_RG_RVREF_SEL_DQ		GENMASK(21, 16)
	#define SHU1_MISC0_RG_RVREF_DDR4_SEL		BIT(22)
	#define SHU1_MISC0_RG_RVREF_DDR3_SEL		BIT(23)
	#define SHU1_MISC0_RG_RVREF_SEL_CMD		GENMASK(29, 24)
#define SHU1_R0_B0_DQ0					0x00000e00
	#define SHU1_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0	GENMASK(3, 0)
	#define SHU1_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0	GENMASK(7, 4)
	#define SHU1_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0	GENMASK(11, 8)
	#define SHU1_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0	GENMASK(15, 12)
	#define SHU1_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0	GENMASK(19, 16)
	#define SHU1_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0	GENMASK(23, 20)
	#define SHU1_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0	GENMASK(27, 24)
	#define SHU1_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0	GENMASK(31, 28)
#define SHU1_R0_B0_DQ1					0x00000e04
	#define SHU1_R0_B0_DQ1_RK0_TX_ARDQM0_DLY_B0	GENMASK(3, 0)
	#define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0_DLYB_B0	GENMASK(19, 16)
	#define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0B_DLYB_B0	GENMASK(23, 20)
	#define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0_DLY_B0	GENMASK(27, 24)
	#define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0B_DLY_B0	GENMASK(31, 28)
#define SHU1_R0_B0_DQ2					0x00000e08
	#define SHU1_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R0_B0_DQ2_RK0_RX_ARDQ0_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0	GENMASK(21, 16)
	#define SHU1_R0_B0_DQ2_RK0_RX_ARDQ1_F_DLY_B0	GENMASK(29, 24)
#define SHU1_R0_B0_DQ3					0x00000e0c
	#define SHU1_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R0_B0_DQ3_RK0_RX_ARDQ2_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0	GENMASK(21, 16)
	#define SHU1_R0_B0_DQ3_RK0_RX_ARDQ3_F_DLY_B0	GENMASK(29, 24)
#define SHU1_R0_B0_DQ4					0x00000e10
	#define SHU1_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R0_B0_DQ4_RK0_RX_ARDQ4_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0	GENMASK(21, 16)
	#define SHU1_R0_B0_DQ4_RK0_RX_ARDQ5_F_DLY_B0	GENMASK(29, 24)
#define SHU1_R0_B0_DQ5					0x00000e14
	#define SHU1_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R0_B0_DQ5_RK0_RX_ARDQ6_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0	GENMASK(21, 16)
	#define SHU1_R0_B0_DQ5_RK0_RX_ARDQ7_F_DLY_B0	GENMASK(29, 24)
#define SHU1_R0_B0_DQ6					0x00000e18
	#define SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0	GENMASK(22, 16)
	#define SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0	GENMASK(30, 24)
#define SHU1_R0_B0_DQ7					0x00000e1c
	#define SHU1_R0_B0_DQ7_RK0_ARPI_DQ_B0		GENMASK(13, 8)
	#define SHU1_R0_B0_DQ7_RK0_ARPI_DQM_B0		GENMASK(21, 16)
	#define SHU1_R0_B0_DQ7_RK0_ARPI_PBYTE_B0	GENMASK(29, 24)
#define RFU_0XE20					0x00000e20
	#define RFU_0XE20_RESERVED_0XE20		GENMASK(31, 0)
#define RFU_0XE24					0x00000e24
	#define RFU_0XE24_RESERVED_0XE24		GENMASK(31, 0)
#define RFU_0XE28					0x00000e28
	#define RFU_0XE28_RESERVED_0XE28		GENMASK(31, 0)
#define RFU_0XE2C					0x00000e2c
	#define RFU_0XE2C_RESERVED_0XE2C		GENMASK(31, 0)
#define SHU1_R0_B1_DQ0					0x00000e50
	#define SHU1_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1	GENMASK(3, 0)
	#define SHU1_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1	GENMASK(7, 4)
	#define SHU1_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1	GENMASK(11, 8)
	#define SHU1_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1	GENMASK(15, 12)
	#define SHU1_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1	GENMASK(19, 16)
	#define SHU1_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1	GENMASK(23, 20)
	#define SHU1_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1	GENMASK(27, 24)
	#define SHU1_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1	GENMASK(31, 28)
#define SHU1_R0_B1_DQ1					0x00000e54
	#define SHU1_R0_B1_DQ1_RK0_TX_ARDQM0_DLY_B1	GENMASK(3, 0)
	#define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0_DLYB_B1	GENMASK(19, 16)
	#define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0B_DLYB_B1	GENMASK(23, 20)
	#define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0_DLY_B1	GENMASK(27, 24)
	#define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0B_DLY_B1	GENMASK(31, 28)
#define SHU1_R0_B1_DQ2					0x00000e58
	#define SHU1_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R0_B1_DQ2_RK0_RX_ARDQ0_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1	GENMASK(21, 16)
	#define SHU1_R0_B1_DQ2_RK0_RX_ARDQ1_F_DLY_B1	GENMASK(29, 24)
#define SHU1_R0_B1_DQ3					0x00000e5c
	#define SHU1_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R0_B1_DQ3_RK0_RX_ARDQ2_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1	GENMASK(21, 16)
	#define SHU1_R0_B1_DQ3_RK0_RX_ARDQ3_F_DLY_B1	GENMASK(29, 24)
#define SHU1_R0_B1_DQ4					0x00000e60
	#define SHU1_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R0_B1_DQ4_RK0_RX_ARDQ4_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1	GENMASK(21, 16)
	#define SHU1_R0_B1_DQ4_RK0_RX_ARDQ5_F_DLY_B1	GENMASK(29, 24)
#define SHU1_R0_B1_DQ5					0x00000e64
	#define SHU1_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R0_B1_DQ5_RK0_RX_ARDQ6_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1	GENMASK(21, 16)
	#define SHU1_R0_B1_DQ5_RK0_RX_ARDQ7_F_DLY_B1	GENMASK(29, 24)
#define SHU1_R0_B1_DQ6					0x00000e68
	#define SHU1_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R0_B1_DQ6_RK0_RX_ARDQM0_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1	GENMASK(22, 16)
	#define SHU1_R0_B1_DQ6_RK0_RX_ARDQS0_F_DLY_B1	GENMASK(30, 24)
#define SHU1_R0_B1_DQ7					0x00000e6c
	#define SHU1_R0_B1_DQ7_RK0_ARPI_DQ_B1		GENMASK(13, 8)
	#define SHU1_R0_B1_DQ7_RK0_ARPI_DQM_B1		GENMASK(21, 16)
	#define SHU1_R0_B1_DQ7_RK0_ARPI_PBYTE_B1	GENMASK(29, 24)
#define RFU_0XE70					0x00000e70
	#define RFU_0XE70_RESERVED_0XE70		GENMASK(31, 0)
#define RFU_0XE74					0x00000e74
	#define RFU_0XE74_RESERVED_0XE74		GENMASK(31, 0)
#define RFU_0XE78					0x00000e78
	#define RFU_0XE78_RESERVED_0XE78		GENMASK(31, 0)
#define RFU_0XE7C					0x00000e7c
	#define RFU_0XE7C_RESERVED_0XE7C		GENMASK(31, 0)
#define SHU1_R0_CA_CMD0					0x00000ea0
	#define SHU1_R0_CA_CMD0_RK0_TX_ARCA0_DLY	GENMASK(3, 0)
	#define SHU1_R0_CA_CMD0_RK0_TX_ARCA1_DLY	GENMASK(7, 4)
	#define SHU1_R0_CA_CMD0_RK0_TX_ARCA2_DLY	GENMASK(11, 8)
	#define SHU1_R0_CA_CMD0_RK0_TX_ARCA3_DLY	GENMASK(15, 12)
	#define SHU1_R0_CA_CMD0_RK0_TX_ARCA4_DLY	GENMASK(19, 16)
	#define SHU1_R0_CA_CMD0_RK0_TX_ARCA5_DLY	GENMASK(23, 20)
	#define SHU1_R0_CA_CMD0_RK0_TX_ARCLK_DLYB	GENMASK(27, 24)
	#define SHU1_R0_CA_CMD0_RK0_TX_ARCLKB_DLYB	GENMASK(31, 28)
#define SHU1_R0_CA_CMD1					0x00000ea4
	#define SHU1_R0_CA_CMD1_RK0_TX_ARCKE0_DLY	GENMASK(3, 0)
	#define SHU1_R0_CA_CMD1_RK0_TX_ARCKE1_DLY	GENMASK(7, 4)
	#define SHU1_R0_CA_CMD1_RK0_TX_ARCKE2_DLY	GENMASK(11, 8)
	#define SHU1_R0_CA_CMD1_RK0_TX_ARCS0_DLY	GENMASK(15, 12)
	#define SHU1_R0_CA_CMD1_RK0_TX_ARCS1_DLY	GENMASK(19, 16)
	#define SHU1_R0_CA_CMD1_RK0_TX_ARCS2_DLY	GENMASK(23, 20)
	#define SHU1_R0_CA_CMD1_RK0_TX_ARCLK_DLY	GENMASK(27, 24)
	#define SHU1_R0_CA_CMD1_RK0_TX_ARCLKB_DLY	GENMASK(31, 28)
#define SHU1_R0_CA_CMD2					0x00000ea8
	#define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA0_R_DLY	GENMASK(5, 0)
	#define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA0_F_DLY	GENMASK(13, 8)
	#define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA1_R_DLY	GENMASK(21, 16)
	#define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA1_F_DLY	GENMASK(29, 24)
#define SHU1_R0_CA_CMD3					0x00000eac
	#define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA2_R_DLY	GENMASK(5, 0)
	#define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA2_F_DLY	GENMASK(13, 8)
	#define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA3_R_DLY	GENMASK(21, 16)
	#define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA3_F_DLY	GENMASK(29, 24)
#define SHU1_R0_CA_CMD4					0x00000eb0
	#define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA4_R_DLY	GENMASK(5, 0)
	#define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA4_F_DLY	GENMASK(13, 8)
	#define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA5_R_DLY	GENMASK(21, 16)
	#define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA5_F_DLY	GENMASK(29, 24)
#define SHU1_R0_CA_CMD5					0x00000eb4
	#define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCKE0_R_DLY	GENMASK(5, 0)
	#define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCKE0_F_DLY	GENMASK(13, 8)
	#define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCKE1_R_DLY	GENMASK(21, 16)
	#define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCKE1_F_DLY	GENMASK(29, 24)
#define SHU1_R0_CA_CMD6					0x00000eb8
	#define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCKE2_R_DLY	GENMASK(5, 0)
	#define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCKE2_F_DLY	GENMASK(13, 8)
	#define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCS0_R_DLY	GENMASK(21, 16)
	#define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCS0_F_DLY	GENMASK(29, 24)
#define SHU1_R0_CA_CMD7					0x00000ebc
	#define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCS1_R_DLY	GENMASK(5, 0)
	#define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCS1_F_DLY	GENMASK(13, 8)
	#define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCS2_R_DLY	GENMASK(21, 16)
	#define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCS2_F_DLY	GENMASK(29, 24)
#define SHU1_R0_CA_CMD8					0x00000ec0
	#define SHU1_R0_CA_CMD8_RG_RK0_RX_ARCLK_R_DLY	GENMASK(22, 16)
	#define SHU1_R0_CA_CMD8_RG_RK0_RX_ARCLK_F_DLY	GENMASK(30, 24)
#define SHU1_R0_CA_CMD9					0x00000ec4
	#define SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS		GENMASK(5, 0)
	#define SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD		GENMASK(13, 8)
	#define SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK		GENMASK(29, 24)
#define RFU_0XEC8					0x00000ec8
	#define RFU_0XEC8_RESERVED_0XEC8		GENMASK(31, 0)
#define RFU_0XECC					0x00000ecc
	#define RFU_0XECC_RESERVED_0XECC		GENMASK(31, 0)
#define SHU1_R1_B0_DQ0					0x00000f00
	#define SHU1_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0	GENMASK(3, 0)
	#define SHU1_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0	GENMASK(7, 4)
	#define SHU1_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0	GENMASK(11, 8)
	#define SHU1_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0	GENMASK(15, 12)
	#define SHU1_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0	GENMASK(19, 16)
	#define SHU1_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0	GENMASK(23, 20)
	#define SHU1_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0	GENMASK(27, 24)
	#define SHU1_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0	GENMASK(31, 28)
#define SHU1_R1_B0_DQ1					0x00000f04
	#define SHU1_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0	GENMASK(3, 0)
	#define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0_DLYB_B0	GENMASK(19, 16)
	#define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0B_DLYB_B0	GENMASK(23, 20)
	#define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0_DLY_B0	GENMASK(27, 24)
	#define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0B_DLY_B0	GENMASK(31, 28)
#define SHU1_R1_B0_DQ2					0x00000f08
	#define SHU1_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R1_B0_DQ2_RK1_RX_ARDQ0_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0	GENMASK(21, 16)
	#define SHU1_R1_B0_DQ2_RK1_RX_ARDQ1_F_DLY_B0	GENMASK(29, 24)
#define SHU1_R1_B0_DQ3					0x00000f0c
	#define SHU1_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R1_B0_DQ3_RK1_RX_ARDQ2_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0	GENMASK(21, 16)
	#define SHU1_R1_B0_DQ3_RK1_RX_ARDQ3_F_DLY_B0	GENMASK(29, 24)
#define SHU1_R1_B0_DQ4					0x00000f10
	#define SHU1_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R1_B0_DQ4_RK1_RX_ARDQ4_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0	GENMASK(21, 16)
	#define SHU1_R1_B0_DQ4_RK1_RX_ARDQ5_F_DLY_B0	GENMASK(29, 24)
#define SHU1_R1_B0_DQ5					0x00000f14
	#define SHU1_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R1_B0_DQ5_RK1_RX_ARDQ6_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0	GENMASK(21, 16)
	#define SHU1_R1_B0_DQ5_RK1_RX_ARDQ7_F_DLY_B0	GENMASK(29, 24)
#define SHU1_R1_B0_DQ6					0x00000f18
	#define SHU1_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R1_B0_DQ6_RK1_RX_ARDQM0_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0	GENMASK(22, 16)
	#define SHU1_R1_B0_DQ6_RK1_RX_ARDQS0_F_DLY_B0	GENMASK(30, 24)
#define SHU1_R1_B0_DQ7					0x00000f1c
	#define SHU1_R1_B0_DQ7_RK1_ARPI_DQ_B0		GENMASK(13, 8)
	#define SHU1_R1_B0_DQ7_RK1_ARPI_DQM_B0		GENMASK(21, 16)
	#define SHU1_R1_B0_DQ7_RK1_ARPI_PBYTE_B0	GENMASK(29, 24)
#define RFU_0XF20					0x00000f20
	#define RFU_0XF20_RESERVED_0XF20		GENMASK(31, 0)
#define RFU_0XF24					0x00000f24
	#define RFU_0XF24_RESERVED_0XF24		GENMASK(31, 0)
#define RFU_0XF28					0x00000f28
	#define RFU_0XF28_RESERVED_0XF28		GENMASK(31, 0)
#define RFU_0XF2C					0x00000f2c
	#define RFU_0XF2C_RESERVED_0XF2C		GENMASK(31, 0)
#define SHU1_R1_B1_DQ0					0x00000f50
	#define SHU1_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1	GENMASK(3, 0)
	#define SHU1_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1	GENMASK(7, 4)
	#define SHU1_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1	GENMASK(11, 8)
	#define SHU1_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1	GENMASK(15, 12)
	#define SHU1_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1	GENMASK(19, 16)
	#define SHU1_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1	GENMASK(23, 20)
	#define SHU1_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1	GENMASK(27, 24)
	#define SHU1_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1	GENMASK(31, 28)
#define SHU1_R1_B1_DQ1					0x00000f54
	#define SHU1_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1	GENMASK(3, 0)
	#define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0_DLYB_B1	GENMASK(19, 16)
	#define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0B_DLYB_B1	GENMASK(23, 20)
	#define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0_DLY_B1	GENMASK(27, 24)
	#define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0B_DLY_B1	GENMASK(31, 28)
#define SHU1_R1_B1_DQ2					0x00000f58
	#define SHU1_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R1_B1_DQ2_RK1_RX_ARDQ0_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1	GENMASK(21, 16)
	#define SHU1_R1_B1_DQ2_RK1_RX_ARDQ1_F_DLY_B1	GENMASK(29, 24)
#define SHU1_R1_B1_DQ3					0x00000f5c
	#define SHU1_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R1_B1_DQ3_RK1_RX_ARDQ2_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1	GENMASK(21, 16)
	#define SHU1_R1_B1_DQ3_RK1_RX_ARDQ3_F_DLY_B1	GENMASK(29, 24)
#define SHU1_R1_B1_DQ4					0x00000f60
	#define SHU1_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R1_B1_DQ4_RK1_RX_ARDQ4_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1	GENMASK(21, 16)
	#define SHU1_R1_B1_DQ4_RK1_RX_ARDQ5_F_DLY_B1	GENMASK(29, 24)
#define SHU1_R1_B1_DQ5					0x00000f64
	#define SHU1_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R1_B1_DQ5_RK1_RX_ARDQ6_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1	GENMASK(21, 16)
	#define SHU1_R1_B1_DQ5_RK1_RX_ARDQ7_F_DLY_B1	GENMASK(29, 24)
#define SHU1_R1_B1_DQ6					0x00000f68
	#define SHU1_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R1_B1_DQ6_RK1_RX_ARDQM0_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1	GENMASK(22, 16)
	#define SHU1_R1_B1_DQ6_RK1_RX_ARDQS0_F_DLY_B1	GENMASK(30, 24)
#define SHU1_R1_B1_DQ7					0x00000f6c
	#define SHU1_R1_B1_DQ7_RK1_ARPI_DQ_B1		GENMASK(13, 8)
	#define SHU1_R1_B1_DQ7_RK1_ARPI_DQM_B1		GENMASK(21, 16)
	#define SHU1_R1_B1_DQ7_RK1_ARPI_PBYTE_B1	GENMASK(29, 24)
#define RFU_0XF70					0x00000f70
	#define RFU_0XF70_RESERVED_0XF70		GENMASK(31, 0)
#define RFU_0XF74					0x00000f74
	#define RFU_0XF74_RESERVED_0XF74		GENMASK(31, 0)
#define RFU_0XF78					0x00000f78
	#define RFU_0XF78_RESERVED_0XF78		GENMASK(31, 0)
#define RFU_0XF7C					0x00000f7c
	#define RFU_0XF7C_RESERVED_0XF7C		GENMASK(31, 0)
#define SHU1_R1_CA_CMD0					0x00000fa0
	#define SHU1_R1_CA_CMD0_RK1_TX_ARCA0_DLY	GENMASK(3, 0)
	#define SHU1_R1_CA_CMD0_RK1_TX_ARCA1_DLY	GENMASK(7, 4)
	#define SHU1_R1_CA_CMD0_RK1_TX_ARCA2_DLY	GENMASK(11, 8)
	#define SHU1_R1_CA_CMD0_RK1_TX_ARCA3_DLY	GENMASK(15, 12)
	#define SHU1_R1_CA_CMD0_RK1_TX_ARCA4_DLY	GENMASK(19, 16)
	#define SHU1_R1_CA_CMD0_RK1_TX_ARCA5_DLY	GENMASK(23, 20)
	#define SHU1_R1_CA_CMD0_RK1_TX_ARCLK_DLYB	GENMASK(27, 24)
	#define SHU1_R1_CA_CMD0_RK1_TX_ARCLKB_DLYB	GENMASK(31, 28)
#define SHU1_R1_CA_CMD1					0x00000fa4
	#define SHU1_R1_CA_CMD1_RK1_TX_ARCKE0_DLY	GENMASK(3, 0)
	#define SHU1_R1_CA_CMD1_RK1_TX_ARCKE1_DLY	GENMASK(7, 4)
	#define SHU1_R1_CA_CMD1_RK1_TX_ARCKE2_DLY	GENMASK(11, 8)
	#define SHU1_R1_CA_CMD1_RK1_TX_ARCS0_DLY	GENMASK(15, 12)
	#define SHU1_R1_CA_CMD1_RK1_TX_ARCS1_DLY	GENMASK(19, 16)
	#define SHU1_R1_CA_CMD1_RK1_TX_ARCS2_DLY	GENMASK(23, 20)
	#define SHU1_R1_CA_CMD1_RK1_TX_ARCLK_DLY	GENMASK(27, 24)
	#define SHU1_R1_CA_CMD1_RK1_TX_ARCLKB_DLY	GENMASK(31, 28)
#define SHU1_R1_CA_CMD2					0x00000fa8
	#define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA0_R_DLY	GENMASK(5, 0)
	#define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA0_F_DLY	GENMASK(13, 8)
	#define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA1_R_DLY	GENMASK(21, 16)
	#define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA1_F_DLY	GENMASK(29, 24)
#define SHU1_R1_CA_CMD3					0x00000fac
	#define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA2_R_DLY	GENMASK(5, 0)
	#define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA2_F_DLY	GENMASK(13, 8)
	#define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA3_R_DLY	GENMASK(21, 16)
	#define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA3_F_DLY	GENMASK(29, 24)
#define SHU1_R1_CA_CMD4					0x00000fb0
	#define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA4_R_DLY	GENMASK(5, 0)
	#define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA4_F_DLY	GENMASK(13, 8)
	#define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA5_R_DLY	GENMASK(21, 16)
	#define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA5_F_DLY	GENMASK(29, 24)
#define SHU1_R1_CA_CMD5					0x00000fb4
	#define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCKE0_R_DLY	GENMASK(5, 0)
	#define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCKE0_F_DLY	GENMASK(13, 8)
	#define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCKE1_R_DLY	GENMASK(21, 16)
	#define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCKE1_F_DLY	GENMASK(29, 24)
#define SHU1_R1_CA_CMD6					0x00000fb8
	#define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCKE2_R_DLY	GENMASK(5, 0)
	#define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCKE2_F_DLY	GENMASK(13, 8)
	#define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCS0_R_DLY	GENMASK(21, 16)
	#define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCS0_F_DLY	GENMASK(29, 24)
#define SHU1_R1_CA_CMD7					0x00000fbc
	#define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCS1_R_DLY	GENMASK(5, 0)
	#define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCS1_F_DLY	GENMASK(13, 8)
	#define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCS2_R_DLY	GENMASK(21, 16)
	#define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCS2_F_DLY	GENMASK(29, 24)
#define SHU1_R1_CA_CMD8					0x00000fc0
	#define SHU1_R1_CA_CMD8_RG_RK1_RX_ARCLK_R_DLY	GENMASK(22, 16)
	#define SHU1_R1_CA_CMD8_RG_RK1_RX_ARCLK_F_DLY	GENMASK(30, 24)
#define SHU1_R1_CA_CMD9					0x00000fc4
	#define SHU1_R1_CA_CMD9_RG_RK1_ARPI_CS		GENMASK(5, 0)
	#define SHU1_R1_CA_CMD9_RG_RK1_ARPI_CMD		GENMASK(13, 8)
	#define SHU1_R1_CA_CMD9_RG_RK1_ARPI_CLK		GENMASK(29, 24)
#define RFU_0XFC8					0x00000fc8
	#define RFU_0XFC8_RESERVED_0XFC8		GENMASK(31, 0)
#define RFU_0XFCC					0x00000fcc
	#define RFU_0XFCC_RESERVED_0XFCC		GENMASK(31, 0)
#define SHU1_R2_B0_DQ0					0x00001000
	#define SHU1_R2_B0_DQ0_RK2_TX_ARDQ0_DLY_B0	GENMASK(3, 0)
	#define SHU1_R2_B0_DQ0_RK2_TX_ARDQ1_DLY_B0	GENMASK(7, 4)
	#define SHU1_R2_B0_DQ0_RK2_TX_ARDQ2_DLY_B0	GENMASK(11, 8)
	#define SHU1_R2_B0_DQ0_RK2_TX_ARDQ3_DLY_B0	GENMASK(15, 12)
	#define SHU1_R2_B0_DQ0_RK2_TX_ARDQ4_DLY_B0	GENMASK(19, 16)
	#define SHU1_R2_B0_DQ0_RK2_TX_ARDQ5_DLY_B0	GENMASK(23, 20)
	#define SHU1_R2_B0_DQ0_RK2_TX_ARDQ6_DLY_B0	GENMASK(27, 24)
	#define SHU1_R2_B0_DQ0_RK2_TX_ARDQ7_DLY_B0	GENMASK(31, 28)
#define SHU1_R2_B0_DQ1					0x00001004
	#define SHU1_R2_B0_DQ1_RK2_TX_ARDQM0_DLY_B0	GENMASK(3, 0)
	#define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0_DLYB_B0	GENMASK(19, 16)
	#define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0B_DLYB_B0	GENMASK(23, 20)
	#define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0_DLY_B0	GENMASK(27, 24)
	#define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0B_DLY_B0	GENMASK(31, 28)
#define SHU1_R2_B0_DQ2					0x00001008
	#define SHU1_R2_B0_DQ2_RK2_RX_ARDQ0_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R2_B0_DQ2_RK2_RX_ARDQ0_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R2_B0_DQ2_RK2_RX_ARDQ1_R_DLY_B0	GENMASK(21, 16)
	#define SHU1_R2_B0_DQ2_RK2_RX_ARDQ1_F_DLY_B0	GENMASK(29, 24)
#define SHU1_R2_B0_DQ3					0x0000100c
	#define SHU1_R2_B0_DQ3_RK2_RX_ARDQ2_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R2_B0_DQ3_RK2_RX_ARDQ2_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R2_B0_DQ3_RK2_RX_ARDQ3_R_DLY_B0	GENMASK(21, 16)
	#define SHU1_R2_B0_DQ3_RK2_RX_ARDQ3_F_DLY_B0	GENMASK(29, 24)
#define SHU1_R2_B0_DQ4					0x00001010
	#define SHU1_R2_B0_DQ4_RK2_RX_ARDQ4_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R2_B0_DQ4_RK2_RX_ARDQ4_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R2_B0_DQ4_RK2_RX_ARDQ5_R_DLY_B0	GENMASK(21, 16)
	#define SHU1_R2_B0_DQ4_RK2_RX_ARDQ5_F_DLY_B0	GENMASK(29, 24)
#define SHU1_R2_B0_DQ5					0x00001014
	#define SHU1_R2_B0_DQ5_RK2_RX_ARDQ6_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R2_B0_DQ5_RK2_RX_ARDQ6_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R2_B0_DQ5_RK2_RX_ARDQ7_R_DLY_B0	GENMASK(21, 16)
	#define SHU1_R2_B0_DQ5_RK2_RX_ARDQ7_F_DLY_B0	GENMASK(29, 24)
#define SHU1_R2_B0_DQ6					0x00001018
	#define SHU1_R2_B0_DQ6_RK2_RX_ARDQM0_R_DLY_B0	GENMASK(5, 0)
	#define SHU1_R2_B0_DQ6_RK2_RX_ARDQM0_F_DLY_B0	GENMASK(13, 8)
	#define SHU1_R2_B0_DQ6_RK2_RX_ARDQS0_R_DLY_B0	GENMASK(22, 16)
	#define SHU1_R2_B0_DQ6_RK2_RX_ARDQS0_F_DLY_B0	GENMASK(30, 24)
#define SHU1_R2_B0_DQ7					0x0000101c
	#define SHU1_R2_B0_DQ7_RK2_ARPI_DQ_B0		GENMASK(13, 8)
	#define SHU1_R2_B0_DQ7_RK2_ARPI_DQM_B0		GENMASK(21, 16)
	#define SHU1_R2_B0_DQ7_RK2_ARPI_PBYTE_B0	GENMASK(29, 24)
#define RFU_0X1020					0x00001020
	#define RFU_0X1020_RESERVED_0X1020		GENMASK(31, 0)
#define RFU_0X1024					0x00001024
	#define RFU_0X1024_RESERVED_0X1024		GENMASK(31, 0)
#define RFU_0X1028					0x00001028
	#define RFU_0X1028_RESERVED_0X1028		GENMASK(31, 0)
#define RFU_0X102C					0x0000102c
	#define RFU_0X102C_RESERVED_0X102C		GENMASK(31, 0)
#define SHU1_R2_B1_DQ0					0x00001050
	#define SHU1_R2_B1_DQ0_RK2_TX_ARDQ0_DLY_B1	GENMASK(3, 0)
	#define SHU1_R2_B1_DQ0_RK2_TX_ARDQ1_DLY_B1	GENMASK(7, 4)
	#define SHU1_R2_B1_DQ0_RK2_TX_ARDQ2_DLY_B1	GENMASK(11, 8)
	#define SHU1_R2_B1_DQ0_RK2_TX_ARDQ3_DLY_B1	GENMASK(15, 12)
	#define SHU1_R2_B1_DQ0_RK2_TX_ARDQ4_DLY_B1	GENMASK(19, 16)
	#define SHU1_R2_B1_DQ0_RK2_TX_ARDQ5_DLY_B1	GENMASK(23, 20)
	#define SHU1_R2_B1_DQ0_RK2_TX_ARDQ6_DLY_B1	GENMASK(27, 24)
	#define SHU1_R2_B1_DQ0_RK2_TX_ARDQ7_DLY_B1	GENMASK(31, 28)
#define SHU1_R2_B1_DQ1					0x00001054
	#define SHU1_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1	GENMASK(3, 0)
	#define SHU1_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1	GENMASK(27, 24)
	#define SHU1_R2_B1_DQ1_RK2_TX_ARDQS0B_DLY_B1	GENMASK(31, 28)
#define SHU1_R2_B1_DQ2					0x00001058
	#define SHU1_R2_B1_DQ2_RK2_RX_ARDQ0_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R2_B1_DQ2_RK2_RX_ARDQ0_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R2_B1_DQ2_RK2_RX_ARDQ1_R_DLY_B1	GENMASK(21, 16)
	#define SHU1_R2_B1_DQ2_RK2_RX_ARDQ1_F_DLY_B1	GENMASK(29, 24)
#define SHU1_R2_B1_DQ3					0x0000105c
	#define SHU1_R2_B1_DQ3_RK2_RX_ARDQ2_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R2_B1_DQ3_RK2_RX_ARDQ2_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R2_B1_DQ3_RK2_RX_ARDQ3_R_DLY_B1	GENMASK(21, 16)
	#define SHU1_R2_B1_DQ3_RK2_RX_ARDQ3_F_DLY_B1	GENMASK(29, 24)
#define SHU1_R2_B1_DQ4					0x00001060
	#define SHU1_R2_B1_DQ4_RK2_RX_ARDQ4_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R2_B1_DQ4_RK2_RX_ARDQ4_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R2_B1_DQ4_RK2_RX_ARDQ5_R_DLY_B1	GENMASK(21, 16)
	#define SHU1_R2_B1_DQ4_RK2_RX_ARDQ5_F_DLY_B1	GENMASK(29, 24)
#define SHU1_R2_B1_DQ5					0x00001064
	#define SHU1_R2_B1_DQ5_RK2_RX_ARDQ6_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R2_B1_DQ5_RK2_RX_ARDQ6_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R2_B1_DQ5_RK2_RX_ARDQ7_R_DLY_B1	GENMASK(21, 16)
	#define SHU1_R2_B1_DQ5_RK2_RX_ARDQ7_F_DLY_B1	GENMASK(29, 24)
#define SHU1_R2_B1_DQ6					0x00001068
	#define SHU1_R2_B1_DQ6_RK2_RX_ARDQM0_R_DLY_B1	GENMASK(5, 0)
	#define SHU1_R2_B1_DQ6_RK2_RX_ARDQM0_F_DLY_B1	GENMASK(13, 8)
	#define SHU1_R2_B1_DQ6_RK2_RX_ARDQS0_R_DLY_B1	GENMASK(22, 16)
	#define SHU1_R2_B1_DQ6_RK2_RX_ARDQS0_F_DLY_B1	GENMASK(30, 24)
#define SHU1_R2_B1_DQ7					0x0000106c
	#define SHU1_R2_B1_DQ7_RK2_ARPI_DQ_B1		GENMASK(13, 8)
	#define SHU1_R2_B1_DQ7_RK2_ARPI_DQM_B1		GENMASK(21, 16)
	#define SHU1_R2_B1_DQ7_RK2_ARPI_PBYTE_B1	GENMASK(29, 24)
#define RFU_0X1070					0x00001070
	#define RFU_0X1070_RESERVED_0X1070		GENMASK(31, 0)
#define RFU_0X1074					0x00001074
	#define RFU_0X1074_RESERVED_0X1074		GENMASK(31, 0)
#define RFU_0X1078					0x00001078
	#define RFU_0X1078_RESERVED_0X1078		GENMASK(31, 0)
#define RFU_0X107C					0x0000107c
	#define RFU_0X107C_RESERVED_0X107C		GENMASK(31, 0)
#define SHU1_R2_CA_CMD0					0x000010a0
	#define SHU1_R2_CA_CMD0_RK2_TX_ARCA0_DLY	GENMASK(3, 0)
	#define SHU1_R2_CA_CMD0_RK2_TX_ARCA1_DLY	GENMASK(7, 4)
	#define SHU1_R2_CA_CMD0_RK2_TX_ARCA2_DLY	GENMASK(11, 8)
	#define SHU1_R2_CA_CMD0_RK2_TX_ARCA3_DLY	GENMASK(15, 12)
	#define SHU1_R2_CA_CMD0_RK2_TX_ARCA4_DLY	GENMASK(19, 16)
	#define SHU1_R2_CA_CMD0_RK2_TX_ARCA5_DLY	GENMASK(23, 20)
	#define SHU1_R2_CA_CMD0_RK2_TX_ARCLK_DLYB	GENMASK(27, 24)
	#define SHU1_R2_CA_CMD0_RK2_TX_ARCLKB_DLYB	GENMASK(31, 28)
#define SHU1_R2_CA_CMD1					0x000010a4
	#define SHU1_R2_CA_CMD1_RK2_TX_ARCKE0_DLY	GENMASK(3, 0)
	#define SHU1_R2_CA_CMD1_RK2_TX_ARCKE1_DLY	GENMASK(7, 4)
	#define SHU1_R2_CA_CMD1_RK2_TX_ARCKE2_DLY	GENMASK(11, 8)
	#define SHU1_R2_CA_CMD1_RK2_TX_ARCS0_DLY	GENMASK(15, 12)
	#define SHU1_R2_CA_CMD1_RK2_TX_ARCS1_DLY	GENMASK(19, 16)
	#define SHU1_R2_CA_CMD1_RK2_TX_ARCS2_DLY	GENMASK(23, 20)
	#define SHU1_R2_CA_CMD1_RK2_TX_ARCLK_DLY	GENMASK(27, 24)
	#define SHU1_R2_CA_CMD1_RK2_TX_ARCLKB_DLY	GENMASK(31, 28)
#define SHU1_R2_CA_CMD2					0x000010a8
	#define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA0_R_DLY	GENMASK(5, 0)
	#define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA0_F_DLY	GENMASK(13, 8)
	#define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA1_R_DLY	GENMASK(21, 16)
	#define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA1_F_DLY	GENMASK(29, 24)
#define SHU1_R2_CA_CMD3					0x000010ac
	#define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA2_R_DLY	GENMASK(5, 0)
	#define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA2_F_DLY	GENMASK(13, 8)
	#define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA3_R_DLY	GENMASK(21, 16)
	#define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA3_F_DLY	GENMASK(29, 24)
#define SHU1_R2_CA_CMD4					0x000010b0
	#define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA4_R_DLY	GENMASK(5, 0)
	#define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA4_F_DLY	GENMASK(13, 8)
	#define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA5_R_DLY	GENMASK(21, 16)
	#define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA5_F_DLY	GENMASK(29, 24)
#define SHU1_R2_CA_CMD5					0x000010b4
	#define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE0_R_DLY	GENMASK(5, 0)
	#define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE0_F_DLY	GENMASK(13, 8)
	#define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE1_R_DLY	GENMASK(21, 16)
	#define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE1_F_DLY	GENMASK(29, 24)
#define SHU1_R2_CA_CMD6					0x000010b8
	#define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCKE2_R_DLY	GENMASK(5, 0)
	#define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCKE2_F_DLY	GENMASK(13, 8)
	#define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCS0_R_DLY	GENMASK(21, 16)
	#define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCS0_F_DLY	GENMASK(29, 24)
#define SHU1_R2_CA_CMD7					0x000010bc
	#define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS1_R_DLY	GENMASK(5, 0)
	#define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS1_F_DLY	GENMASK(13, 8)
	#define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS2_R_DLY	GENMASK(21, 16)
	#define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS2_F_DLY	GENMASK(29, 24)
#define SHU1_R2_CA_CMD8					0x000010c0
	#define SHU1_R2_CA_CMD8_RG_RK2_RX_ARCLK_R_DLY	GENMASK(22, 16)
	#define SHU1_R2_CA_CMD8_RG_RK2_RX_ARCLK_F_DLY	GENMASK(30, 24)
#define SHU1_R2_CA_CMD9					0x000010c4
	#define SHU1_R2_CA_CMD9_RG_RK2_ARPI_CS		GENMASK(5, 0)
	#define SHU1_R2_CA_CMD9_RG_RK2_ARPI_CMD		GENMASK(13, 8)
	#define SHU1_R2_CA_CMD9_RG_RK2_ARPI_CLK		GENMASK(29, 24)
#define RFU_0X10C8					0x000010c8
	#define RFU_0X10C8_RESERVED_0X10C8		GENMASK(31, 0)
#define RFU_0X10CC					0x000010cc
	#define RFU_0X10CC_RESERVED_0X10CC		GENMASK(31, 0)
#define SHU2_B0_DQ0					0x00001100
	#define SHU2_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0	BIT(4)
	#define SHU2_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0	GENMASK(10, 8)
	#define SHU2_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0	GENMASK(14, 12)
	#define SHU2_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0	BIT(20)
	#define SHU2_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0	GENMASK(26, 24)
	#define SHU2_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0	GENMASK(30, 28)
	#define SHU2_B0_DQ0_R_LP4Y_WDN_MODE_DQS0	BIT(31)
#define SHU2_B0_DQ1					0x00001104
	#define SHU2_B0_DQ1_RG_TX_ARDQ_DRVP_B0		GENMASK(4, 0)
	#define SHU2_B0_DQ1_RG_TX_ARDQ_DRVN_B0		GENMASK(12, 8)
	#define SHU2_B0_DQ1_RG_TX_ARDQ_ODTP_B0		GENMASK(20, 16)
	#define SHU2_B0_DQ1_RG_TX_ARDQ_ODTN_B0		GENMASK(28, 24)
#define SHU2_B0_DQ2					0x00001108
	#define SHU2_B0_DQ2_RG_TX_ARDQS0_DRVP_B0	GENMASK(4, 0)
	#define SHU2_B0_DQ2_RG_TX_ARDQS0_DRVN_B0	GENMASK(12, 8)
	#define SHU2_B0_DQ2_RG_TX_ARDQS0_ODTP_B0	GENMASK(20, 16)
	#define SHU2_B0_DQ2_RG_TX_ARDQS0_ODTN_B0	GENMASK(28, 24)
#define SHU2_B0_DQ3					0x0000110c
	#define SHU2_B0_DQ3_RG_TX_ARDQS0_PU_B0		GENMASK(1, 0)
	#define SHU2_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0	GENMASK(3, 2)
	#define SHU2_B0_DQ3_RG_TX_ARDQS0_PDB_B0		GENMASK(5, 4)
	#define SHU2_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0	GENMASK(7, 6)
	#define SHU2_B0_DQ3_RG_TX_ARDQ_PU_B0		GENMASK(9, 8)
	#define SHU2_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0	GENMASK(11, 10)
	#define SHU2_B0_DQ3_RG_TX_ARDQ_PDB_B0		GENMASK(13, 12)
	#define SHU2_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0	GENMASK(15, 14)
#define SHU2_B0_DQ4					0x00001110
	#define SHU2_B0_DQ4_RG_ARPI_AA_MCK_DL_B0	GENMASK(5, 0)
	#define SHU2_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0	GENMASK(13, 8)
	#define SHU2_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0	GENMASK(21, 16)
#define SHU2_B0_DQ5					0x00001114
	#define SHU2_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0	GENMASK(5, 0)
	#define SHU2_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0	BIT(6)
	#define SHU2_B0_DQ5_RG_ARPI_FB_B0		GENMASK(13, 8)
	#define SHU2_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0	GENMASK(18, 16)
	#define SHU2_B0_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B0	BIT(19)
	#define SHU2_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0	GENMASK(22, 20)
	#define SHU2_B0_DQ5_RG_ARPI_MCTL_B0		GENMASK(29, 24)
#define SHU2_B0_DQ6					0x00001118
	#define SHU2_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0	GENMASK(5, 0)
	#define SHU2_B0_DQ6_RG_ARPI_RESERVE_B0		GENMASK(21, 6)
	#define SHU2_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0	GENMASK(23, 22)
	#define SHU2_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0	GENMASK(25, 24)
	#define SHU2_B0_DQ6_RG_ARPI_MIDPI_EN_B0		BIT(26)
	#define SHU2_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0	BIT(27)
	#define SHU2_B0_DQ6_RG_ARPI_CAP_SEL_B0		GENMASK(29, 28)
	#define SHU2_B0_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B0	BIT(31)
#define SHU2_B0_DQ7					0x0000111c
	#define SHU2_B0_DQ7_R_DMRANKRXDVS_B0		GENMASK(3, 0)
	#define SHU2_B0_DQ7_MIDPI_ENABLE		BIT(4)
	#define SHU2_B0_DQ7_MIDPI_DIV4_ENABLE		BIT(5)
	#define SHU2_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0	BIT(6)
	#define SHU2_B0_DQ7_R_DMDQMDBI_SHU_B0		BIT(7)
	#define SHU2_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0	GENMASK(11, 8)
	#define SHU2_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0	BIT(12)
	#define SHU2_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0	BIT(13)
	#define SHU2_B0_DQ7_R_DMRXTRACK_DQM_EN_B0	BIT(14)
	#define SHU2_B0_DQ7_R_DMRODTEN_B0		BIT(15)
	#define SHU2_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0	BIT(16)
	#define SHU2_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0	BIT(17)
	#define SHU2_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0	BIT(18)
	#define SHU2_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0	BIT(19)
	#define SHU2_B0_DQ7_R_LP4Y_SDN_MODE_DQS0	BIT(20)
	#define SHU2_B0_DQ7_R_DMRXRANK_DQ_EN_B0		BIT(24)
	#define SHU2_B0_DQ7_R_DMRXRANK_DQ_LAT_B0	GENMASK(27, 25)
	#define SHU2_B0_DQ7_R_DMRXRANK_DQS_EN_B0	BIT(28)
	#define SHU2_B0_DQ7_R_DMRXRANK_DQS_LAT_B0	GENMASK(31, 29)
#define SHU2_B0_DQ8					0x00001120
	#define SHU2_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0	GENMASK(14, 0)
	#define SHU2_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0	BIT(15)
	#define SHU2_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0	BIT(19)
	#define SHU2_B0_DQ8_R_RMRODTEN_CG_IG_B0		BIT(20)
	#define SHU2_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0	BIT(21)
	#define SHU2_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0	BIT(22)
	#define SHU2_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0	BIT(23)
	#define SHU2_B0_DQ8_R_DMRXDLY_CG_IG_B0		BIT(24)
	#define SHU2_B0_DQ8_R_DMSTBEN_SYNC_CG_IG_B0	BIT(25)
	#define SHU2_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0	BIT(26)
	#define SHU2_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0	BIT(27)
	#define SHU2_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0	BIT(28)
	#define SHU2_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0	BIT(29)
	#define SHU2_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0	BIT(30)
	#define SHU2_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0	BIT(31)
#define SHU2_B0_DQ9					0x00001124
	#define SHU2_B0_DQ9_RESERVED_0X1124		GENMASK(31, 0)
#define SHU2_B0_DQ10					0x00001128
	#define SHU2_B0_DQ10_RESERVED_0X1128		GENMASK(31, 0)
#define SHU2_B0_DQ11					0x0000112c
	#define SHU2_B0_DQ11_RESERVED_0X112C		GENMASK(31, 0)
#define SHU2_B0_DQ12					0x00001130
	#define SHU2_B0_DQ12_RESERVED_0X1130		GENMASK(31, 0)
#define SHU2_B0_DLL0					0x00001134
	#define SHU2_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU	BIT(0)
	#define SHU2_B0_DLL0_B0_DLL0_RFU		BIT(3)
	#define SHU2_B0_DLL0_RG_ARDLL_FAST_PSJP_B0	BIT(4)
	#define SHU2_B0_DLL0_RG_ARDLL_PHDIV_B0		BIT(9)
	#define SHU2_B0_DLL0_RG_ARDLL_PHJUMP_EN_B0	BIT(10)
	#define SHU2_B0_DLL0_RG_ARDLL_P_GAIN_B0		GENMASK(15, 12)
	#define SHU2_B0_DLL0_RG_ARDLL_IDLECNT_B0	GENMASK(19, 16)
	#define SHU2_B0_DLL0_RG_ARDLL_GAIN_B0		GENMASK(23, 20)
	#define SHU2_B0_DLL0_RG_ARDLL_PHDET_IN_SWAP_B0	BIT(30)
	#define SHU2_B0_DLL0_RG_ARDLL_PHDET_OUT_SEL_B0	BIT(31)
#define SHU2_B0_DLL1					0x00001138
	#define SHU2_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0	BIT(0)
	#define SHU2_B0_DLL1_RG_ARDLL_PS_EN_B0		BIT(1)
	#define SHU2_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0	BIT(2)
	#define SHU2_B0_DLL1_RG_ARDQ_REV_B0		GENMASK(31, 8)
#define SHU2_B1_DQ0					0x00001180
	#define SHU2_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1	BIT(4)
	#define SHU2_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1	GENMASK(10, 8)
	#define SHU2_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1	GENMASK(14, 12)
	#define SHU2_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1	BIT(20)
	#define SHU2_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1	GENMASK(26, 24)
	#define SHU2_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1	GENMASK(30, 28)
	#define SHU2_B1_DQ0_R_LP4Y_WDN_MODE_DQS1	BIT(31)
#define SHU2_B1_DQ1					0x00001184
	#define SHU2_B1_DQ1_RG_TX_ARDQ_DRVP_B1		GENMASK(4, 0)
	#define SHU2_B1_DQ1_RG_TX_ARDQ_DRVN_B1		GENMASK(12, 8)
	#define SHU2_B1_DQ1_RG_TX_ARDQ_ODTP_B1		GENMASK(20, 16)
	#define SHU2_B1_DQ1_RG_TX_ARDQ_ODTN_B1		GENMASK(28, 24)
#define SHU2_B1_DQ2					0x00001188
	#define SHU2_B1_DQ2_RG_TX_ARDQS0_DRVP_B1	GENMASK(4, 0)
	#define SHU2_B1_DQ2_RG_TX_ARDQS0_DRVN_B1	GENMASK(12, 8)
	#define SHU2_B1_DQ2_RG_TX_ARDQS0_ODTP_B1	GENMASK(20, 16)
	#define SHU2_B1_DQ2_RG_TX_ARDQS0_ODTN_B1	GENMASK(28, 24)
#define SHU2_B1_DQ3					0x0000118c
	#define SHU2_B1_DQ3_RG_TX_ARDQS0_PU_B1		GENMASK(1, 0)
	#define SHU2_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1	GENMASK(3, 2)
	#define SHU2_B1_DQ3_RG_TX_ARDQS0_PDB_B1		GENMASK(5, 4)
	#define SHU2_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1	GENMASK(7, 6)
	#define SHU2_B1_DQ3_RG_TX_ARDQ_PU_B1		GENMASK(9, 8)
	#define SHU2_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1	GENMASK(11, 10)
	#define SHU2_B1_DQ3_RG_TX_ARDQ_PDB_B1		GENMASK(13, 12)
	#define SHU2_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1	GENMASK(15, 14)
#define SHU2_B1_DQ4					0x00001190
	#define SHU2_B1_DQ4_RG_ARPI_AA_MCK_DL_B1	GENMASK(5, 0)
	#define SHU2_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1	GENMASK(13, 8)
	#define SHU2_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1	GENMASK(21, 16)
#define SHU2_B1_DQ5					0x00001194
	#define SHU2_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1	GENMASK(5, 0)
	#define SHU2_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1	BIT(6)
	#define SHU2_B1_DQ5_RG_ARPI_FB_B1		GENMASK(13, 8)
	#define SHU2_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1	GENMASK(18, 16)
	#define SHU2_B1_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B1	BIT(19)
	#define SHU2_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1	GENMASK(22, 20)
	#define SHU2_B1_DQ5_RG_ARPI_MCTL_B1		GENMASK(29, 24)
#define SHU2_B1_DQ6					0x00001198
	#define SHU2_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1	GENMASK(5, 0)
	#define SHU2_B1_DQ6_RG_ARPI_RESERVE_B1		GENMASK(21, 6)
	#define SHU2_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1	GENMASK(23, 22)
	#define SHU2_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1	GENMASK(25, 24)
	#define SHU2_B1_DQ6_RG_ARPI_MIDPI_EN_B1		BIT(26)
	#define SHU2_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1	BIT(27)
	#define SHU2_B1_DQ6_RG_ARPI_CAP_SEL_B1		GENMASK(29, 28)
	#define SHU2_B1_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B1	BIT(31)
#define SHU2_B1_DQ7					0x0000119c
	#define SHU2_B1_DQ7_R_DMRANKRXDVS_B1		GENMASK(3, 0)
	#define SHU2_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1	BIT(6)
	#define SHU2_B1_DQ7_R_DMDQMDBI_SHU_B1		BIT(7)
	#define SHU2_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1	GENMASK(11, 8)
	#define SHU2_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1	BIT(12)
	#define SHU2_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1	BIT(13)
	#define SHU2_B1_DQ7_R_DMRXTRACK_DQM_EN_B1	BIT(14)
	#define SHU2_B1_DQ7_R_DMRODTEN_B1		BIT(15)
	#define SHU2_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1	BIT(16)
	#define SHU2_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1	BIT(17)
	#define SHU2_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1	BIT(18)
	#define SHU2_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1	BIT(19)
	#define SHU2_B1_DQ7_R_LP4Y_SDN_MODE_DQS1	BIT(20)
	#define SHU2_B1_DQ7_R_DMRXRANK_DQ_EN_B1		BIT(24)
	#define SHU2_B1_DQ7_R_DMRXRANK_DQ_LAT_B1	GENMASK(27, 25)
	#define SHU2_B1_DQ7_R_DMRXRANK_DQS_EN_B1	BIT(28)
	#define SHU2_B1_DQ7_R_DMRXRANK_DQS_LAT_B1	GENMASK(31, 29)
#define SHU2_B1_DQ8					0x000011a0
	#define SHU2_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1	GENMASK(14, 0)
	#define SHU2_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1	BIT(15)
	#define SHU2_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1	BIT(19)
	#define SHU2_B1_DQ8_R_RMRODTEN_CG_IG_B1		BIT(20)
	#define SHU2_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1	BIT(21)
	#define SHU2_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1	BIT(22)
	#define SHU2_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1	BIT(23)
	#define SHU2_B1_DQ8_R_DMRXDLY_CG_IG_B1		BIT(24)
	#define SHU2_B1_DQ8_R_DMSTBEN_SYNC_CG_IG_B1	BIT(25)
	#define SHU2_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1	BIT(26)
	#define SHU2_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1	BIT(27)
	#define SHU2_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1	BIT(28)
	#define SHU2_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1	BIT(29)
	#define SHU2_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1	BIT(30)
	#define SHU2_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1	BIT(31)
#define SHU2_B1_DQ9					0x000011a4
	#define SHU2_B1_DQ9_RESERVED_0X11A4		GENMASK(31, 0)
#define SHU2_B1_DQ10					0x000011a8
	#define SHU2_B1_DQ10_RESERVED_0X11A8		GENMASK(31, 0)
#define SHU2_B1_DQ11					0x000011ac
	#define SHU2_B1_DQ11_RESERVED_0X11AC		GENMASK(31, 0)
#define SHU2_B1_DQ12					0x000011b0
	#define SHU2_B1_DQ12_RESERVED_0X11B0		GENMASK(31, 0)
#define SHU2_B1_DLL0					0x000011b4
	#define SHU2_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU	BIT(0)
	#define SHU2_B1_DLL0_B1_DLL0_RFU		BIT(3)
	#define SHU2_B1_DLL0_RG_ARDLL_FAST_PSJP_B1	BIT(4)
	#define SHU2_B1_DLL0_RG_ARDLL_PHDIV_B1		BIT(9)
	#define SHU2_B1_DLL0_RG_ARDLL_PHJUMP_EN_B1	BIT(10)
	#define SHU2_B1_DLL0_RG_ARDLL_P_GAIN_B1		GENMASK(15, 12)
	#define SHU2_B1_DLL0_RG_ARDLL_IDLECNT_B1	GENMASK(19, 16)
	#define SHU2_B1_DLL0_RG_ARDLL_GAIN_B1		GENMASK(23, 20)
	#define SHU2_B1_DLL0_RG_ARDLL_PHDET_IN_SWAP_B1	BIT(30)
	#define SHU2_B1_DLL0_RG_ARDLL_PHDET_OUT_SEL_B1	BIT(31)
#define SHU2_B1_DLL1					0x000011b8
	#define SHU2_B1_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B1	BIT(0)
	#define SHU2_B1_DLL1_RG_ARDLL_PS_EN_B1		BIT(1)
	#define SHU2_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1	BIT(2)
	#define SHU2_B1_DLL1_RG_ARDQ_REV_B1		GENMASK(31, 8)
#define SHU2_CA_CMD0					0x00001200
	#define SHU2_CA_CMD0_RG_TX_ARCLK_PRE_EN		BIT(4)
	#define SHU2_CA_CMD0_RG_TX_ARCLK_DRVP_PRE	GENMASK(10, 8)
	#define SHU2_CA_CMD0_RG_TX_ARCLK_DRVN_PRE	GENMASK(14, 12)
	#define SHU2_CA_CMD0_RG_CGEN_FMEM_CK_CG_DLL	BIT(17)
	#define SHU2_CA_CMD0_RG_FB_CK_MUX		GENMASK(19, 18)
	#define SHU2_CA_CMD0_RG_TX_ARCMD_PRE_EN		BIT(20)
	#define SHU2_CA_CMD0_RG_TX_ARCMD_DRVP_PRE	GENMASK(26, 24)
	#define SHU2_CA_CMD0_RG_TX_ARCMD_DRVN_PRE	GENMASK(30, 28)
	#define SHU2_CA_CMD0_R_LP4Y_WDN_MODE_CLK	BIT(31)
#define SHU2_CA_CMD1					0x00001204
	#define SHU2_CA_CMD1_RG_TX_ARCMD_DRVP		GENMASK(4, 0)
	#define SHU2_CA_CMD1_RG_TX_ARCMD_DRVN		GENMASK(12, 8)
	#define SHU2_CA_CMD1_RG_TX_ARCMD_ODTP		GENMASK(20, 16)
	#define SHU2_CA_CMD1_RG_TX_ARCMD_ODTN		GENMASK(28, 24)
#define SHU2_CA_CMD2					0x00001208
	#define SHU2_CA_CMD2_RG_TX_ARCLK_DRVP		GENMASK(4, 0)
	#define SHU2_CA_CMD2_RG_TX_ARCLK_DRVN		GENMASK(12, 8)
	#define SHU2_CA_CMD2_RG_TX_ARCLK_ODTP		GENMASK(20, 16)
	#define SHU2_CA_CMD2_RG_TX_ARCLK_ODTN		GENMASK(28, 24)
#define SHU2_CA_CMD3					0x0000120c
	#define SHU2_CA_CMD3_RG_TX_ARCLK_PU		GENMASK(1, 0)
	#define SHU2_CA_CMD3_RG_TX_ARCLK_PU_PRE		GENMASK(3, 2)
	#define SHU2_CA_CMD3_RG_TX_ARCLK_PDB		GENMASK(5, 4)
	#define SHU2_CA_CMD3_RG_TX_ARCLK_PDB_PRE	GENMASK(7, 6)
	#define SHU2_CA_CMD3_RG_TX_ARCMD_PU		GENMASK(9, 8)
	#define SHU2_CA_CMD3_RG_TX_ARCMD_PU_PRE		GENMASK(11, 10)
	#define SHU2_CA_CMD3_RG_TX_ARCMD_PDB		GENMASK(13, 12)
	#define SHU2_CA_CMD3_RG_TX_ARCMD_PDB_PRE	GENMASK(15, 14)
#define SHU2_CA_CMD4					0x00001210
	#define SHU2_CA_CMD4_RG_ARPI_AA_MCK_DL_CA	GENMASK(5, 0)
	#define SHU2_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA	GENMASK(13, 8)
	#define SHU2_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA	GENMASK(21, 16)
#define SHU2_CA_CMD5					0x00001214
	#define SHU2_CA_CMD5_RG_RX_ARCMD_VREF_SEL	GENMASK(5, 0)
	#define SHU2_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS	BIT(6)
	#define SHU2_CA_CMD5_RG_ARPI_FB_CA		GENMASK(13, 8)
	#define SHU2_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY	GENMASK(18, 16)
	#define SHU2_CA_CMD5_DA_RX_ARCLK_DQSIEN_RB_DLY	BIT(19)
	#define SHU2_CA_CMD5_RG_RX_ARCLK_DVS_DLY	GENMASK(22, 20)
	#define SHU2_CA_CMD5_RG_ARPI_MCTL_CA		GENMASK(29, 24)
#define SHU2_CA_CMD6					0x00001218
	#define SHU2_CA_CMD6_RG_ARPI_OFFSET_CLKIEN	GENMASK(5, 0)
	#define SHU2_CA_CMD6_RG_ARPI_RESERVE_CA		GENMASK(21, 6)
	#define SHU2_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA	GENMASK(23, 22)
	#define SHU2_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA	GENMASK(25, 24)
	#define SHU2_CA_CMD6_RG_ARPI_MIDPI_EN_CA	BIT(26)
	#define SHU2_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA	BIT(27)
	#define SHU2_CA_CMD6_RG_ARPI_CAP_SEL_CA		GENMASK(29, 28)
	#define SHU2_CA_CMD6_RG_ARPI_MIDPI_BYPASS_EN_CA	BIT(31)
#define SHU2_CA_CMD7					0x0000121c
	#define SHU2_CA_CMD7_R_DMRANKRXDVS_CA		GENMASK(3, 0)
	#define SHU2_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA	BIT(12)
	#define SHU2_CA_CMD7_R_DMRODTEN_CA		BIT(15)
	#define SHU2_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA	BIT(16)
	#define SHU2_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW	BIT(17)
	#define SHU2_CA_CMD7_R_DMTX_ARPI_CG_CLK_NEW	BIT(18)
	#define SHU2_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW	BIT(19)
	#define SHU2_CA_CMD7_R_LP4Y_SDN_MODE_CLK	BIT(20)
	#define SHU2_CA_CMD7_R_DMRXRANK_CMD_EN		BIT(24)
	#define SHU2_CA_CMD7_R_DMRXRANK_CMD_LAT		GENMASK(27, 25)
	#define SHU2_CA_CMD7_R_DMRXRANK_CLK_EN		BIT(28)
	#define SHU2_CA_CMD7_R_DMRXRANK_CLK_LAT		GENMASK(31, 29)
#define SHU2_CA_CMD8					0x00001220
	#define SHU2_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA	GENMASK(14, 0)
	#define SHU2_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA	BIT(15)
	#define SHU2_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA	BIT(19)
	#define SHU2_CA_CMD8_R_RMRODTEN_CG_IG_CA	BIT(20)
	#define SHU2_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA	BIT(21)
	#define SHU2_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA	BIT(22)
	#define SHU2_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA	BIT(23)
	#define SHU2_CA_CMD8_R_DMRXDLY_CG_IG_CA		BIT(24)
	#define SHU2_CA_CMD8_R_DMSTBEN_SYNC_CG_IG_CA	BIT(25)
	#define SHU2_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA	BIT(26)
	#define SHU2_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA	BIT(27)
	#define SHU2_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA	BIT(28)
	#define SHU2_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA	BIT(29)
	#define SHU2_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA	BIT(30)
	#define SHU2_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA	BIT(31)
#define SHU2_CA_CMD9					0x00001224
	#define SHU2_CA_CMD9_RESERVED_0X1224		GENMASK(31, 0)
#define SHU2_CA_CMD10					0x00001228
	#define SHU2_CA_CMD10_RESERVED_0X1228		GENMASK(31, 0)
#define SHU2_CA_CMD11					0x0000122c
	#define SHU2_CA_CMD11_RG_RIMP_REV		GENMASK(7, 0)
	#define SHU2_CA_CMD11_RG_RIMP_VREF_SEL		GENMASK(13, 8)
	#define SHU2_CA_CMD11_RG_TX_ARCKE_DRVP		GENMASK(21, 17)
	#define SHU2_CA_CMD11_RG_TX_ARCKE_DRVN		GENMASK(26, 22)
#define SHU2_CA_CMD12					0x00001230
	#define SHU2_CA_CMD12_RESERVED_0X1230		GENMASK(31, 0)
#define SHU2_CA_DLL0					0x00001234
	#define SHU2_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU	BIT(0)
	#define SHU2_CA_DLL0_CA_DLL0_RFU		BIT(3)
	#define SHU2_CA_DLL0_RG_ARDLL_FAST_PSJP_CA	BIT(4)
	#define SHU2_CA_DLL0_RG_ARDLL_PHDIV_CA		BIT(9)
	#define SHU2_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA	BIT(10)
	#define SHU2_CA_DLL0_RG_ARDLL_P_GAIN_CA		GENMASK(15, 12)
	#define SHU2_CA_DLL0_RG_ARDLL_IDLECNT_CA	GENMASK(19, 16)
	#define SHU2_CA_DLL0_RG_ARDLL_GAIN_CA		GENMASK(23, 20)
	#define SHU2_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA	BIT(30)
	#define SHU2_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA	BIT(31)
#define SHU2_CA_DLL1					0x00001238
	#define SHU2_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA	BIT(0)
	#define SHU2_CA_DLL1_RG_ARDLL_PS_EN_CA		BIT(1)
	#define SHU2_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA	BIT(2)
	#define SHU2_CA_DLL1_RG_ARCMD_REV		GENMASK(31, 8)
#define SHU2_MISC0					0x000012f0
	#define SHU2_MISC0_R_RX_PIPE_BYPASS_EN		BIT(1)
	#define SHU2_MISC0_RG_CMD_TXPIPE_BYPASS_EN	BIT(2)
	#define SHU2_MISC0_RG_CK_TXPIPE_BYPASS_EN	BIT(3)
	#define SHU2_MISC0_RG_RVREF_SEL_DQ		GENMASK(21, 16)
	#define SHU2_MISC0_RG_RVREF_DDR4_SEL		BIT(22)
	#define SHU2_MISC0_RG_RVREF_DDR3_SEL		BIT(23)
	#define SHU2_MISC0_RG_RVREF_SEL_CMD		GENMASK(29, 24)
#define SHU2_R0_B0_DQ0					0x00001300
	#define SHU2_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0	GENMASK(3, 0)
	#define SHU2_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0	GENMASK(7, 4)
	#define SHU2_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0	GENMASK(11, 8)
	#define SHU2_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0	GENMASK(15, 12)
	#define SHU2_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0	GENMASK(19, 16)
	#define SHU2_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0	GENMASK(23, 20)
	#define SHU2_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0	GENMASK(27, 24)
	#define SHU2_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0	GENMASK(31, 28)
#define SHU2_R0_B0_DQ1					0x00001304
	#define SHU2_R0_B0_DQ1_RK0_TX_ARDQM0_DLY_B0	GENMASK(3, 0)
	#define SHU2_R0_B0_DQ1_RK0_TX_ARDQS0_DLYB_B0	GENMASK(19, 16)
	#define SHU2_R0_B0_DQ1_RK0_TX_ARDQS0B_DLYB_B0	GENMASK(23, 20)
	#define SHU2_R0_B0_DQ1_RK0_TX_ARDQS0_DLY_B0	GENMASK(27, 24)
	#define SHU2_R0_B0_DQ1_RK0_TX_ARDQS0B_DLY_B0	GENMASK(31, 28)
#define SHU2_R0_B0_DQ2					0x00001308
	#define SHU2_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R0_B0_DQ2_RK0_RX_ARDQ0_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0	GENMASK(21, 16)
	#define SHU2_R0_B0_DQ2_RK0_RX_ARDQ1_F_DLY_B0	GENMASK(29, 24)
#define SHU2_R0_B0_DQ3					0x0000130c
	#define SHU2_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R0_B0_DQ3_RK0_RX_ARDQ2_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0	GENMASK(21, 16)
	#define SHU2_R0_B0_DQ3_RK0_RX_ARDQ3_F_DLY_B0	GENMASK(29, 24)
#define SHU2_R0_B0_DQ4					0x00001310
	#define SHU2_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R0_B0_DQ4_RK0_RX_ARDQ4_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0	GENMASK(21, 16)
	#define SHU2_R0_B0_DQ4_RK0_RX_ARDQ5_F_DLY_B0	GENMASK(29, 24)
#define SHU2_R0_B0_DQ5					0x00001314
	#define SHU2_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R0_B0_DQ5_RK0_RX_ARDQ6_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0	GENMASK(21, 16)
	#define SHU2_R0_B0_DQ5_RK0_RX_ARDQ7_F_DLY_B0	GENMASK(29, 24)
#define SHU2_R0_B0_DQ6					0x00001318
	#define SHU2_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0	GENMASK(22, 16)
	#define SHU2_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0	GENMASK(30, 24)
#define SHU2_R0_B0_DQ7					0x0000131c
	#define SHU2_R0_B0_DQ7_RK0_ARPI_DQ_B0		GENMASK(13, 8)
	#define SHU2_R0_B0_DQ7_RK0_ARPI_DQM_B0		GENMASK(21, 16)
	#define SHU2_R0_B0_DQ7_RK0_ARPI_PBYTE_B0	GENMASK(29, 24)
#define RFU_0X1320					0x00001320
	#define RFU_0X1320_RESERVED_0X1320		GENMASK(31, 0)
#define RFU_0X1324					0x00001324
	#define RFU_0X1324_RESERVED_0X1324		GENMASK(31, 0)
#define RFU_0X1328					0x00001328
	#define RFU_0X1328_RESERVED_0X1328		GENMASK(31, 0)
#define RFU_0X132C					0x0000132c
	#define RFU_0X132C_RESERVED_0X132C		GENMASK(31, 0)
#define SHU2_R0_B1_DQ0					0x00001350
	#define SHU2_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1	GENMASK(3, 0)
	#define SHU2_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1	GENMASK(7, 4)
	#define SHU2_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1	GENMASK(11, 8)
	#define SHU2_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1	GENMASK(15, 12)
	#define SHU2_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1	GENMASK(19, 16)
	#define SHU2_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1	GENMASK(23, 20)
	#define SHU2_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1	GENMASK(27, 24)
	#define SHU2_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1	GENMASK(31, 28)
#define SHU2_R0_B1_DQ1					0x00001354
	#define SHU2_R0_B1_DQ1_RK0_TX_ARDQM0_DLY_B1	GENMASK(3, 0)
	#define SHU2_R0_B1_DQ1_RK0_TX_ARDQS0_DLYB_B1	GENMASK(19, 16)
	#define SHU2_R0_B1_DQ1_RK0_TX_ARDQS0B_DLYB_B1	GENMASK(23, 20)
	#define SHU2_R0_B1_DQ1_RK0_TX_ARDQS0_DLY_B1	GENMASK(27, 24)
	#define SHU2_R0_B1_DQ1_RK0_TX_ARDQS0B_DLY_B1	GENMASK(31, 28)
#define SHU2_R0_B1_DQ2					0x00001358
	#define SHU2_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R0_B1_DQ2_RK0_RX_ARDQ0_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1	GENMASK(21, 16)
	#define SHU2_R0_B1_DQ2_RK0_RX_ARDQ1_F_DLY_B1	GENMASK(29, 24)
#define SHU2_R0_B1_DQ3					0x0000135c
	#define SHU2_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R0_B1_DQ3_RK0_RX_ARDQ2_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1	GENMASK(21, 16)
	#define SHU2_R0_B1_DQ3_RK0_RX_ARDQ3_F_DLY_B1	GENMASK(29, 24)
#define SHU2_R0_B1_DQ4					0x00001360
	#define SHU2_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R0_B1_DQ4_RK0_RX_ARDQ4_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1	GENMASK(21, 16)
	#define SHU2_R0_B1_DQ4_RK0_RX_ARDQ5_F_DLY_B1	GENMASK(29, 24)
#define SHU2_R0_B1_DQ5					0x00001364
	#define SHU2_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R0_B1_DQ5_RK0_RX_ARDQ6_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1	GENMASK(21, 16)
	#define SHU2_R0_B1_DQ5_RK0_RX_ARDQ7_F_DLY_B1	GENMASK(29, 24)
#define SHU2_R0_B1_DQ6					0x00001368
	#define SHU2_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R0_B1_DQ6_RK0_RX_ARDQM0_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1	GENMASK(22, 16)
	#define SHU2_R0_B1_DQ6_RK0_RX_ARDQS0_F_DLY_B1	GENMASK(30, 24)
#define SHU2_R0_B1_DQ7					0x0000136c
	#define SHU2_R0_B1_DQ7_RK0_ARPI_DQ_B1		GENMASK(13, 8)
	#define SHU2_R0_B1_DQ7_RK0_ARPI_DQM_B1		GENMASK(21, 16)
	#define SHU2_R0_B1_DQ7_RK0_ARPI_PBYTE_B1	GENMASK(29, 24)
#define RFU_0X1370					0x00001370
	#define RFU_0X1370_RESERVED_0X1370		GENMASK(31, 0)
#define RFU_0X1374					0x00001374
	#define RFU_0X1374_RESERVED_0X1374		GENMASK(31, 0)
#define RFU_0X1378					0x00001378
	#define RFU_0X1378_RESERVED_0X1378		GENMASK(31, 0)
#define RFU_0X137C					0x0000137c
	#define RFU_0X137C_RESERVED_0X137C		GENMASK(31, 0)
#define SHU2_R0_CA_CMD0					0x000013a0
	#define SHU2_R0_CA_CMD0_RK0_TX_ARCA0_DLY	GENMASK(3, 0)
	#define SHU2_R0_CA_CMD0_RK0_TX_ARCA1_DLY	GENMASK(7, 4)
	#define SHU2_R0_CA_CMD0_RK0_TX_ARCA2_DLY	GENMASK(11, 8)
	#define SHU2_R0_CA_CMD0_RK0_TX_ARCA3_DLY	GENMASK(15, 12)
	#define SHU2_R0_CA_CMD0_RK0_TX_ARCA4_DLY	GENMASK(19, 16)
	#define SHU2_R0_CA_CMD0_RK0_TX_ARCA5_DLY	GENMASK(23, 20)
	#define SHU2_R0_CA_CMD0_RK0_TX_ARCLK_DLYB	GENMASK(27, 24)
	#define SHU2_R0_CA_CMD0_RK0_TX_ARCLKB_DLYB	GENMASK(31, 28)
#define SHU2_R0_CA_CMD1					0x000013a4
	#define SHU2_R0_CA_CMD1_RK0_TX_ARCKE0_DLY	GENMASK(3, 0)
	#define SHU2_R0_CA_CMD1_RK0_TX_ARCKE1_DLY	GENMASK(7, 4)
	#define SHU2_R0_CA_CMD1_RK0_TX_ARCKE2_DLY	GENMASK(11, 8)
	#define SHU2_R0_CA_CMD1_RK0_TX_ARCS0_DLY	GENMASK(15, 12)
	#define SHU2_R0_CA_CMD1_RK0_TX_ARCS1_DLY	GENMASK(19, 16)
	#define SHU2_R0_CA_CMD1_RK0_TX_ARCS2_DLY	GENMASK(23, 20)
	#define SHU2_R0_CA_CMD1_RK0_TX_ARCLK_DLY	GENMASK(27, 24)
	#define SHU2_R0_CA_CMD1_RK0_TX_ARCLKB_DLY	GENMASK(31, 28)
#define SHU2_R0_CA_CMD2					0x000013a8
	#define SHU2_R0_CA_CMD2_RG_RK0_RX_ARCA0_R_DLY	GENMASK(5, 0)
	#define SHU2_R0_CA_CMD2_RG_RK0_RX_ARCA0_F_DLY	GENMASK(13, 8)
	#define SHU2_R0_CA_CMD2_RG_RK0_RX_ARCA1_R_DLY	GENMASK(21, 16)
	#define SHU2_R0_CA_CMD2_RG_RK0_RX_ARCA1_F_DLY	GENMASK(29, 24)
#define SHU2_R0_CA_CMD3					0x000013ac
	#define SHU2_R0_CA_CMD3_RG_RK0_RX_ARCA2_R_DLY	GENMASK(5, 0)
	#define SHU2_R0_CA_CMD3_RG_RK0_RX_ARCA2_F_DLY	GENMASK(13, 8)
	#define SHU2_R0_CA_CMD3_RG_RK0_RX_ARCA3_R_DLY	GENMASK(21, 16)
	#define SHU2_R0_CA_CMD3_RG_RK0_RX_ARCA3_F_DLY	GENMASK(29, 24)
#define SHU2_R0_CA_CMD4					0x000013b0
	#define SHU2_R0_CA_CMD4_RG_RK0_RX_ARCA4_R_DLY	GENMASK(5, 0)
	#define SHU2_R0_CA_CMD4_RG_RK0_RX_ARCA4_F_DLY	GENMASK(13, 8)
	#define SHU2_R0_CA_CMD4_RG_RK0_RX_ARCA5_R_DLY	GENMASK(21, 16)
	#define SHU2_R0_CA_CMD4_RG_RK0_RX_ARCA5_F_DLY	GENMASK(29, 24)
#define SHU2_R0_CA_CMD5					0x000013b4
	#define SHU2_R0_CA_CMD5_RG_RK0_RX_ARCKE0_R_DLY	GENMASK(5, 0)
	#define SHU2_R0_CA_CMD5_RG_RK0_RX_ARCKE0_F_DLY	GENMASK(13, 8)
	#define SHU2_R0_CA_CMD5_RG_RK0_RX_ARCKE1_R_DLY	GENMASK(21, 16)
	#define SHU2_R0_CA_CMD5_RG_RK0_RX_ARCKE1_F_DLY	GENMASK(29, 24)
#define SHU2_R0_CA_CMD6					0x000013b8
	#define SHU2_R0_CA_CMD6_RG_RK0_RX_ARCKE2_R_DLY	GENMASK(5, 0)
	#define SHU2_R0_CA_CMD6_RG_RK0_RX_ARCKE2_F_DLY	GENMASK(13, 8)
	#define SHU2_R0_CA_CMD6_RG_RK0_RX_ARCS0_R_DLY	GENMASK(21, 16)
	#define SHU2_R0_CA_CMD6_RG_RK0_RX_ARCS0_F_DLY	GENMASK(29, 24)
#define SHU2_R0_CA_CMD7					0x000013bc
	#define SHU2_R0_CA_CMD7_RG_RK0_RX_ARCS1_R_DLY	GENMASK(5, 0)
	#define SHU2_R0_CA_CMD7_RG_RK0_RX_ARCS1_F_DLY	GENMASK(13, 8)
	#define SHU2_R0_CA_CMD7_RG_RK0_RX_ARCS2_R_DLY	GENMASK(21, 16)
	#define SHU2_R0_CA_CMD7_RG_RK0_RX_ARCS2_F_DLY	GENMASK(29, 24)
#define SHU2_R0_CA_CMD8					0x000013c0
	#define SHU2_R0_CA_CMD8_RG_RK0_RX_ARCLK_R_DLY	GENMASK(22, 16)
	#define SHU2_R0_CA_CMD8_RG_RK0_RX_ARCLK_F_DLY	GENMASK(30, 24)
#define SHU2_R0_CA_CMD9					0x000013c4
	#define SHU2_R0_CA_CMD9_RG_RK0_ARPI_CS		GENMASK(5, 0)
	#define SHU2_R0_CA_CMD9_RG_RK0_ARPI_CMD		GENMASK(13, 8)
	#define SHU2_R0_CA_CMD9_RG_RK0_ARPI_CLK		GENMASK(29, 24)
#define RFU_0X13C8					0x000013c8
	#define RFU_0X13C8_RESERVED_0X13C8		GENMASK(31, 0)
#define RFU_0X13CC					0x000013cc
	#define RFU_0X13CC_RESERVED_0X13CC		GENMASK(31, 0)
#define SHU2_R1_B0_DQ0					0x00001400
	#define SHU2_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0	GENMASK(3, 0)
	#define SHU2_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0	GENMASK(7, 4)
	#define SHU2_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0	GENMASK(11, 8)
	#define SHU2_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0	GENMASK(15, 12)
	#define SHU2_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0	GENMASK(19, 16)
	#define SHU2_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0	GENMASK(23, 20)
	#define SHU2_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0	GENMASK(27, 24)
	#define SHU2_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0	GENMASK(31, 28)
#define SHU2_R1_B0_DQ1					0x00001404
	#define SHU2_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0	GENMASK(3, 0)
	#define SHU2_R1_B0_DQ1_RK1_TX_ARDQS0_DLYB_B0	GENMASK(19, 16)
	#define SHU2_R1_B0_DQ1_RK1_TX_ARDQS0B_DLYB_B0	GENMASK(23, 20)
	#define SHU2_R1_B0_DQ1_RK1_TX_ARDQS0_DLY_B0	GENMASK(27, 24)
	#define SHU2_R1_B0_DQ1_RK1_TX_ARDQS0B_DLY_B0	GENMASK(31, 28)
#define SHU2_R1_B0_DQ2					0x00001408
	#define SHU2_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R1_B0_DQ2_RK1_RX_ARDQ0_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0	GENMASK(21, 16)
	#define SHU2_R1_B0_DQ2_RK1_RX_ARDQ1_F_DLY_B0	GENMASK(29, 24)
#define SHU2_R1_B0_DQ3					0x0000140c
	#define SHU2_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R1_B0_DQ3_RK1_RX_ARDQ2_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0	GENMASK(21, 16)
	#define SHU2_R1_B0_DQ3_RK1_RX_ARDQ3_F_DLY_B0	GENMASK(29, 24)
#define SHU2_R1_B0_DQ4					0x00001410
	#define SHU2_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R1_B0_DQ4_RK1_RX_ARDQ4_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0	GENMASK(21, 16)
	#define SHU2_R1_B0_DQ4_RK1_RX_ARDQ5_F_DLY_B0	GENMASK(29, 24)
#define SHU2_R1_B0_DQ5					0x00001414
	#define SHU2_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R1_B0_DQ5_RK1_RX_ARDQ6_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0	GENMASK(21, 16)
	#define SHU2_R1_B0_DQ5_RK1_RX_ARDQ7_F_DLY_B0	GENMASK(29, 24)
#define SHU2_R1_B0_DQ6					0x00001418
	#define SHU2_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R1_B0_DQ6_RK1_RX_ARDQM0_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0	GENMASK(22, 16)
	#define SHU2_R1_B0_DQ6_RK1_RX_ARDQS0_F_DLY_B0	GENMASK(30, 24)
#define SHU2_R1_B0_DQ7					0x0000141c
	#define SHU2_R1_B0_DQ7_RK1_ARPI_DQ_B0		GENMASK(13, 8)
	#define SHU2_R1_B0_DQ7_RK1_ARPI_DQM_B0		GENMASK(21, 16)
	#define SHU2_R1_B0_DQ7_RK1_ARPI_PBYTE_B0	GENMASK(29, 24)
#define RFU_0X1420					0x00001420
	#define RFU_0X1420_RESERVED_0X1420		GENMASK(31, 0)
#define RFU_0X1424					0x00001424
	#define RFU_0X1424_RESERVED_0X1424		GENMASK(31, 0)
#define RFU_0X1428					0x00001428
	#define RFU_0X1428_RESERVED_0X1428		GENMASK(31, 0)
#define RFU_0X142C					0x0000142c
	#define RFU_0X142C_RESERVED_0X142C		GENMASK(31, 0)
#define SHU2_R1_B1_DQ0					0x00001450
	#define SHU2_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1	GENMASK(3, 0)
	#define SHU2_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1	GENMASK(7, 4)
	#define SHU2_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1	GENMASK(11, 8)
	#define SHU2_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1	GENMASK(15, 12)
	#define SHU2_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1	GENMASK(19, 16)
	#define SHU2_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1	GENMASK(23, 20)
	#define SHU2_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1	GENMASK(27, 24)
	#define SHU2_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1	GENMASK(31, 28)
#define SHU2_R1_B1_DQ1					0x00001454
	#define SHU2_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1	GENMASK(3, 0)
	#define SHU2_R1_B1_DQ1_RK1_TX_ARDQS0_DLYB_B1	GENMASK(19, 16)
	#define SHU2_R1_B1_DQ1_RK1_TX_ARDQS0B_DLYB_B1	GENMASK(23, 20)
	#define SHU2_R1_B1_DQ1_RK1_TX_ARDQS0_DLY_B1	GENMASK(27, 24)
	#define SHU2_R1_B1_DQ1_RK1_TX_ARDQS0B_DLY_B1	GENMASK(31, 28)
#define SHU2_R1_B1_DQ2					0x00001458
	#define SHU2_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R1_B1_DQ2_RK1_RX_ARDQ0_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1	GENMASK(21, 16)
	#define SHU2_R1_B1_DQ2_RK1_RX_ARDQ1_F_DLY_B1	GENMASK(29, 24)
#define SHU2_R1_B1_DQ3					0x0000145c
	#define SHU2_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R1_B1_DQ3_RK1_RX_ARDQ2_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1	GENMASK(21, 16)
	#define SHU2_R1_B1_DQ3_RK1_RX_ARDQ3_F_DLY_B1	GENMASK(29, 24)
#define SHU2_R1_B1_DQ4					0x00001460
	#define SHU2_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R1_B1_DQ4_RK1_RX_ARDQ4_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1	GENMASK(21, 16)
	#define SHU2_R1_B1_DQ4_RK1_RX_ARDQ5_F_DLY_B1	GENMASK(29, 24)
#define SHU2_R1_B1_DQ5					0x00001464
	#define SHU2_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R1_B1_DQ5_RK1_RX_ARDQ6_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1	GENMASK(21, 16)
	#define SHU2_R1_B1_DQ5_RK1_RX_ARDQ7_F_DLY_B1	GENMASK(29, 24)
#define SHU2_R1_B1_DQ6					0x00001468
	#define SHU2_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R1_B1_DQ6_RK1_RX_ARDQM0_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1	GENMASK(22, 16)
	#define SHU2_R1_B1_DQ6_RK1_RX_ARDQS0_F_DLY_B1	GENMASK(30, 24)
#define SHU2_R1_B1_DQ7					0x0000146c
	#define SHU2_R1_B1_DQ7_RK1_ARPI_DQ_B1		GENMASK(13, 8)
	#define SHU2_R1_B1_DQ7_RK1_ARPI_DQM_B1		GENMASK(21, 16)
	#define SHU2_R1_B1_DQ7_RK1_ARPI_PBYTE_B1	GENMASK(29, 24)
#define RFU_0X1470					0x00001470
	#define RFU_0X1470_RESERVED_0X1470		GENMASK(31, 0)
#define RFU_0X1474					0x00001474
	#define RFU_0X1474_RESERVED_0X1474		GENMASK(31, 0)
#define RFU_0X1478					0x00001478
	#define RFU_0X1478_RESERVED_0X1478		GENMASK(31, 0)
#define RFU_0X147C					0x0000147c
	#define RFU_0X147C_RESERVED_0X147C		GENMASK(31, 0)
#define SHU2_R1_CA_CMD0					0x000014a0
	#define SHU2_R1_CA_CMD0_RK1_TX_ARCA0_DLY	GENMASK(3, 0)
	#define SHU2_R1_CA_CMD0_RK1_TX_ARCA1_DLY	GENMASK(7, 4)
	#define SHU2_R1_CA_CMD0_RK1_TX_ARCA2_DLY	GENMASK(11, 8)
	#define SHU2_R1_CA_CMD0_RK1_TX_ARCA3_DLY	GENMASK(15, 12)
	#define SHU2_R1_CA_CMD0_RK1_TX_ARCA4_DLY	GENMASK(19, 16)
	#define SHU2_R1_CA_CMD0_RK1_TX_ARCA5_DLY	GENMASK(23, 20)
	#define SHU2_R1_CA_CMD0_RK1_TX_ARCLK_DLYB	GENMASK(27, 24)
	#define SHU2_R1_CA_CMD0_RK1_TX_ARCLKB_DLYB	GENMASK(31, 28)
#define SHU2_R1_CA_CMD1					0x000014a4
	#define SHU2_R1_CA_CMD1_RK1_TX_ARCKE0_DLY	GENMASK(3, 0)
	#define SHU2_R1_CA_CMD1_RK1_TX_ARCKE1_DLY	GENMASK(7, 4)
	#define SHU2_R1_CA_CMD1_RK1_TX_ARCKE2_DLY	GENMASK(11, 8)
	#define SHU2_R1_CA_CMD1_RK1_TX_ARCS0_DLY	GENMASK(15, 12)
	#define SHU2_R1_CA_CMD1_RK1_TX_ARCS1_DLY	GENMASK(19, 16)
	#define SHU2_R1_CA_CMD1_RK1_TX_ARCS2_DLY	GENMASK(23, 20)
	#define SHU2_R1_CA_CMD1_RK1_TX_ARCLK_DLY	GENMASK(27, 24)
	#define SHU2_R1_CA_CMD1_RK1_TX_ARCLKB_DLY	GENMASK(31, 28)
#define SHU2_R1_CA_CMD2					0x000014a8
	#define SHU2_R1_CA_CMD2_RG_RK1_RX_ARCA0_R_DLY	GENMASK(5, 0)
	#define SHU2_R1_CA_CMD2_RG_RK1_RX_ARCA0_F_DLY	GENMASK(13, 8)
	#define SHU2_R1_CA_CMD2_RG_RK1_RX_ARCA1_R_DLY	GENMASK(21, 16)
	#define SHU2_R1_CA_CMD2_RG_RK1_RX_ARCA1_F_DLY	GENMASK(29, 24)
#define SHU2_R1_CA_CMD3					0x000014ac
	#define SHU2_R1_CA_CMD3_RG_RK1_RX_ARCA2_R_DLY	GENMASK(5, 0)
	#define SHU2_R1_CA_CMD3_RG_RK1_RX_ARCA2_F_DLY	GENMASK(13, 8)
	#define SHU2_R1_CA_CMD3_RG_RK1_RX_ARCA3_R_DLY	GENMASK(21, 16)
	#define SHU2_R1_CA_CMD3_RG_RK1_RX_ARCA3_F_DLY	GENMASK(29, 24)
#define SHU2_R1_CA_CMD4					0x000014b0
	#define SHU2_R1_CA_CMD4_RG_RK1_RX_ARCA4_R_DLY	GENMASK(5, 0)
	#define SHU2_R1_CA_CMD4_RG_RK1_RX_ARCA4_F_DLY	GENMASK(13, 8)
	#define SHU2_R1_CA_CMD4_RG_RK1_RX_ARCA5_R_DLY	GENMASK(21, 16)
	#define SHU2_R1_CA_CMD4_RG_RK1_RX_ARCA5_F_DLY	GENMASK(29, 24)
#define SHU2_R1_CA_CMD5					0x000014b4
	#define SHU2_R1_CA_CMD5_RG_RK1_RX_ARCKE0_R_DLY	GENMASK(5, 0)
	#define SHU2_R1_CA_CMD5_RG_RK1_RX_ARCKE0_F_DLY	GENMASK(13, 8)
	#define SHU2_R1_CA_CMD5_RG_RK1_RX_ARCKE1_R_DLY	GENMASK(21, 16)
	#define SHU2_R1_CA_CMD5_RG_RK1_RX_ARCKE1_F_DLY	GENMASK(29, 24)
#define SHU2_R1_CA_CMD6					0x000014b8
	#define SHU2_R1_CA_CMD6_RG_RK1_RX_ARCKE2_R_DLY	GENMASK(5, 0)
	#define SHU2_R1_CA_CMD6_RG_RK1_RX_ARCKE2_F_DLY	GENMASK(13, 8)
	#define SHU2_R1_CA_CMD6_RG_RK1_RX_ARCS0_R_DLY	GENMASK(21, 16)
	#define SHU2_R1_CA_CMD6_RG_RK1_RX_ARCS0_F_DLY	GENMASK(29, 24)
#define SHU2_R1_CA_CMD7					0x000014bc
	#define SHU2_R1_CA_CMD7_RG_RK1_RX_ARCS1_R_DLY	GENMASK(5, 0)
	#define SHU2_R1_CA_CMD7_RG_RK1_RX_ARCS1_F_DLY	GENMASK(13, 8)
	#define SHU2_R1_CA_CMD7_RG_RK1_RX_ARCS2_R_DLY	GENMASK(21, 16)
	#define SHU2_R1_CA_CMD7_RG_RK1_RX_ARCS2_F_DLY	GENMASK(29, 24)
#define SHU2_R1_CA_CMD8					0x000014c0
	#define SHU2_R1_CA_CMD8_RG_RK1_RX_ARCLK_R_DLY	GENMASK(22, 16)
	#define SHU2_R1_CA_CMD8_RG_RK1_RX_ARCLK_F_DLY	GENMASK(30, 24)
#define SHU2_R1_CA_CMD9					0x000014c4
	#define SHU2_R1_CA_CMD9_RG_RK1_ARPI_CS		GENMASK(5, 0)
	#define SHU2_R1_CA_CMD9_RG_RK1_ARPI_CMD		GENMASK(13, 8)
	#define SHU2_R1_CA_CMD9_RG_RK1_ARPI_CLK		GENMASK(29, 24)
#define RFU_0X14C8					0x000014c8
	#define RFU_0X14C8_RESERVED_0X14C8		GENMASK(31, 0)
#define RFU_0X14CC					0x000014cc
	#define RFU_0X14CC_RESERVED_0X14CC		GENMASK(31, 0)
#define SHU2_R2_B0_DQ0					0x00001500
	#define SHU2_R2_B0_DQ0_RK2_TX_ARDQ0_DLY_B0	GENMASK(3, 0)
	#define SHU2_R2_B0_DQ0_RK2_TX_ARDQ1_DLY_B0	GENMASK(7, 4)
	#define SHU2_R2_B0_DQ0_RK2_TX_ARDQ2_DLY_B0	GENMASK(11, 8)
	#define SHU2_R2_B0_DQ0_RK2_TX_ARDQ3_DLY_B0	GENMASK(15, 12)
	#define SHU2_R2_B0_DQ0_RK2_TX_ARDQ4_DLY_B0	GENMASK(19, 16)
	#define SHU2_R2_B0_DQ0_RK2_TX_ARDQ5_DLY_B0	GENMASK(23, 20)
	#define SHU2_R2_B0_DQ0_RK2_TX_ARDQ6_DLY_B0	GENMASK(27, 24)
	#define SHU2_R2_B0_DQ0_RK2_TX_ARDQ7_DLY_B0	GENMASK(31, 28)
#define SHU2_R2_B0_DQ1					0x00001504
	#define SHU2_R2_B0_DQ1_RK2_TX_ARDQM0_DLY_B0	GENMASK(3, 0)
	#define SHU2_R2_B0_DQ1_RK2_TX_ARDQS0_DLYB_B0	GENMASK(19, 16)
	#define SHU2_R2_B0_DQ1_RK2_TX_ARDQS0B_DLYB_B0	GENMASK(23, 20)
	#define SHU2_R2_B0_DQ1_RK2_TX_ARDQS0_DLY_B0	GENMASK(27, 24)
	#define SHU2_R2_B0_DQ1_RK2_TX_ARDQS0B_DLY_B0	GENMASK(31, 28)
#define SHU2_R2_B0_DQ2					0x00001508
	#define SHU2_R2_B0_DQ2_RK2_RX_ARDQ0_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R2_B0_DQ2_RK2_RX_ARDQ0_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R2_B0_DQ2_RK2_RX_ARDQ1_R_DLY_B0	GENMASK(21, 16)
	#define SHU2_R2_B0_DQ2_RK2_RX_ARDQ1_F_DLY_B0	GENMASK(29, 24)
#define SHU2_R2_B0_DQ3					0x0000150c
	#define SHU2_R2_B0_DQ3_RK2_RX_ARDQ2_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R2_B0_DQ3_RK2_RX_ARDQ2_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R2_B0_DQ3_RK2_RX_ARDQ3_R_DLY_B0	GENMASK(21, 16)
	#define SHU2_R2_B0_DQ3_RK2_RX_ARDQ3_F_DLY_B0	GENMASK(29, 24)
#define SHU2_R2_B0_DQ4					0x00001510
	#define SHU2_R2_B0_DQ4_RK2_RX_ARDQ4_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R2_B0_DQ4_RK2_RX_ARDQ4_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R2_B0_DQ4_RK2_RX_ARDQ5_R_DLY_B0	GENMASK(21, 16)
	#define SHU2_R2_B0_DQ4_RK2_RX_ARDQ5_F_DLY_B0	GENMASK(29, 24)
#define SHU2_R2_B0_DQ5					0x00001514
	#define SHU2_R2_B0_DQ5_RK2_RX_ARDQ6_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R2_B0_DQ5_RK2_RX_ARDQ6_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R2_B0_DQ5_RK2_RX_ARDQ7_R_DLY_B0	GENMASK(21, 16)
	#define SHU2_R2_B0_DQ5_RK2_RX_ARDQ7_F_DLY_B0	GENMASK(29, 24)
#define SHU2_R2_B0_DQ6					0x00001518
	#define SHU2_R2_B0_DQ6_RK2_RX_ARDQM0_R_DLY_B0	GENMASK(5, 0)
	#define SHU2_R2_B0_DQ6_RK2_RX_ARDQM0_F_DLY_B0	GENMASK(13, 8)
	#define SHU2_R2_B0_DQ6_RK2_RX_ARDQS0_R_DLY_B0	GENMASK(22, 16)
	#define SHU2_R2_B0_DQ6_RK2_RX_ARDQS0_F_DLY_B0	GENMASK(30, 24)
#define SHU2_R2_B0_DQ7					0x0000151c
	#define SHU2_R2_B0_DQ7_RK2_ARPI_DQ_B0		GENMASK(13, 8)
	#define SHU2_R2_B0_DQ7_RK2_ARPI_DQM_B0		GENMASK(21, 16)
	#define SHU2_R2_B0_DQ7_RK2_ARPI_PBYTE_B0	GENMASK(29, 24)
#define RFU_0X1520					0x00001520
	#define RFU_0X1520_RESERVED_0X1520		GENMASK(31, 0)
#define RFU_0X1524					0x00001524
	#define RFU_0X1524_RESERVED_0X1524		GENMASK(31, 0)
#define RFU_0X1528					0x00001528
	#define RFU_0X1528_RESERVED_0X1528		GENMASK(31, 0)
#define RFU_0X152C					0x0000152c
	#define RFU_0X152C_RESERVED_0X152C		GENMASK(31, 0)
#define SHU2_R2_B1_DQ0					0x00001550
	#define SHU2_R2_B1_DQ0_RK2_TX_ARDQ0_DLY_B1	GENMASK(3, 0)
	#define SHU2_R2_B1_DQ0_RK2_TX_ARDQ1_DLY_B1	GENMASK(7, 4)
	#define SHU2_R2_B1_DQ0_RK2_TX_ARDQ2_DLY_B1	GENMASK(11, 8)
	#define SHU2_R2_B1_DQ0_RK2_TX_ARDQ3_DLY_B1	GENMASK(15, 12)
	#define SHU2_R2_B1_DQ0_RK2_TX_ARDQ4_DLY_B1	GENMASK(19, 16)
	#define SHU2_R2_B1_DQ0_RK2_TX_ARDQ5_DLY_B1	GENMASK(23, 20)
	#define SHU2_R2_B1_DQ0_RK2_TX_ARDQ6_DLY_B1	GENMASK(27, 24)
	#define SHU2_R2_B1_DQ0_RK2_TX_ARDQ7_DLY_B1	GENMASK(31, 28)
#define SHU2_R2_B1_DQ1					0x00001554
	#define SHU2_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1	GENMASK(3, 0)
	#define SHU2_R2_B1_DQ1_RK2_TX_ARDQS0_DLYB_B1	GENMASK(19, 16)
	#define SHU2_R2_B1_DQ1_RK2_TX_ARDQS0B_DLYB_B1	GENMASK(23, 20)
	#define SHU2_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1	GENMASK(27, 24)
	#define SHU2_R2_B1_DQ1_RK2_TX_ARDQS0B_DLY_B1	GENMASK(31, 28)
#define SHU2_R2_B1_DQ2					0x00001558
	#define SHU2_R2_B1_DQ2_RK2_RX_ARDQ0_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R2_B1_DQ2_RK2_RX_ARDQ0_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R2_B1_DQ2_RK2_RX_ARDQ1_R_DLY_B1	GENMASK(21, 16)
	#define SHU2_R2_B1_DQ2_RK2_RX_ARDQ1_F_DLY_B1	GENMASK(29, 24)
#define SHU2_R2_B1_DQ3					0x0000155c
	#define SHU2_R2_B1_DQ3_RK2_RX_ARDQ2_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R2_B1_DQ3_RK2_RX_ARDQ2_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R2_B1_DQ3_RK2_RX_ARDQ3_R_DLY_B1	GENMASK(21, 16)
	#define SHU2_R2_B1_DQ3_RK2_RX_ARDQ3_F_DLY_B1	GENMASK(29, 24)
#define SHU2_R2_B1_DQ4					0x00001560
	#define SHU2_R2_B1_DQ4_RK2_RX_ARDQ4_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R2_B1_DQ4_RK2_RX_ARDQ4_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R2_B1_DQ4_RK2_RX_ARDQ5_R_DLY_B1	GENMASK(21, 16)
	#define SHU2_R2_B1_DQ4_RK2_RX_ARDQ5_F_DLY_B1	GENMASK(29, 24)
#define SHU2_R2_B1_DQ5					0x00001564
	#define SHU2_R2_B1_DQ5_RK2_RX_ARDQ6_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R2_B1_DQ5_RK2_RX_ARDQ6_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R2_B1_DQ5_RK2_RX_ARDQ7_R_DLY_B1	GENMASK(21, 16)
	#define SHU2_R2_B1_DQ5_RK2_RX_ARDQ7_F_DLY_B1	GENMASK(29, 24)
#define SHU2_R2_B1_DQ6					0x00001568
	#define SHU2_R2_B1_DQ6_RK2_RX_ARDQM0_R_DLY_B1	GENMASK(5, 0)
	#define SHU2_R2_B1_DQ6_RK2_RX_ARDQM0_F_DLY_B1	GENMASK(13, 8)
	#define SHU2_R2_B1_DQ6_RK2_RX_ARDQS0_R_DLY_B1	GENMASK(22, 16)
	#define SHU2_R2_B1_DQ6_RK2_RX_ARDQS0_F_DLY_B1	GENMASK(30, 24)
#define SHU2_R2_B1_DQ7					0x0000156c
	#define SHU2_R2_B1_DQ7_RK2_ARPI_DQ_B1		GENMASK(13, 8)
	#define SHU2_R2_B1_DQ7_RK2_ARPI_DQM_B1		GENMASK(21, 16)
	#define SHU2_R2_B1_DQ7_RK2_ARPI_PBYTE_B1	GENMASK(29, 24)
#define RFU_0X1570					0x00001570
	#define RFU_0X1570_RESERVED_0X1570		GENMASK(31, 0)
#define RFU_0X1574					0x00001574
	#define RFU_0X1574_RESERVED_0X1574		GENMASK(31, 0)
#define RFU_0X1578					0x00001578
	#define RFU_0X1578_RESERVED_0X1578		GENMASK(31, 0)
#define RFU_0X157C					0x0000157c
	#define RFU_0X157C_RESERVED_0X157C		GENMASK(31, 0)
#define SHU2_R2_CA_CMD0					0x000015a0
	#define SHU2_R2_CA_CMD0_RK2_TX_ARCA0_DLY	GENMASK(3, 0)
	#define SHU2_R2_CA_CMD0_RK2_TX_ARCA1_DLY	GENMASK(7, 4)
	#define SHU2_R2_CA_CMD0_RK2_TX_ARCA2_DLY	GENMASK(11, 8)
	#define SHU2_R2_CA_CMD0_RK2_TX_ARCA3_DLY	GENMASK(15, 12)
	#define SHU2_R2_CA_CMD0_RK2_TX_ARCA4_DLY	GENMASK(19, 16)
	#define SHU2_R2_CA_CMD0_RK2_TX_ARCA5_DLY	GENMASK(23, 20)
	#define SHU2_R2_CA_CMD0_RK2_TX_ARCLK_DLYB	GENMASK(27, 24)
	#define SHU2_R2_CA_CMD0_RK2_TX_ARCLKB_DLYB	GENMASK(31, 28)
#define SHU2_R2_CA_CMD1					0x000015a4
	#define SHU2_R2_CA_CMD1_RK2_TX_ARCKE0_DLY	GENMASK(3, 0)
	#define SHU2_R2_CA_CMD1_RK2_TX_ARCKE1_DLY	GENMASK(7, 4)
	#define SHU2_R2_CA_CMD1_RK2_TX_ARCKE2_DLY	GENMASK(11, 8)
	#define SHU2_R2_CA_CMD1_RK2_TX_ARCS0_DLY	GENMASK(15, 12)
	#define SHU2_R2_CA_CMD1_RK2_TX_ARCS1_DLY	GENMASK(19, 16)
	#define SHU2_R2_CA_CMD1_RK2_TX_ARCS2_DLY	GENMASK(23, 20)
	#define SHU2_R2_CA_CMD1_RK2_TX_ARCLK_DLY	GENMASK(27, 24)
	#define SHU2_R2_CA_CMD1_RK2_TX_ARCLKB_DLY	GENMASK(31, 28)
#define SHU2_R2_CA_CMD2					0x000015a8
	#define SHU2_R2_CA_CMD2_RG_RK2_RX_ARCA0_R_DLY	GENMASK(5, 0)
	#define SHU2_R2_CA_CMD2_RG_RK2_RX_ARCA0_F_DLY	GENMASK(13, 8)
	#define SHU2_R2_CA_CMD2_RG_RK2_RX_ARCA1_R_DLY	GENMASK(21, 16)
	#define SHU2_R2_CA_CMD2_RG_RK2_RX_ARCA1_F_DLY	GENMASK(29, 24)
#define SHU2_R2_CA_CMD3					0x000015ac
	#define SHU2_R2_CA_CMD3_RG_RK2_RX_ARCA2_R_DLY	GENMASK(5, 0)
	#define SHU2_R2_CA_CMD3_RG_RK2_RX_ARCA2_F_DLY	GENMASK(13, 8)
	#define SHU2_R2_CA_CMD3_RG_RK2_RX_ARCA3_R_DLY	GENMASK(21, 16)
	#define SHU2_R2_CA_CMD3_RG_RK2_RX_ARCA3_F_DLY	GENMASK(29, 24)
#define SHU2_R2_CA_CMD4					0x000015b0
	#define SHU2_R2_CA_CMD4_RG_RK2_RX_ARCA4_R_DLY	GENMASK(5, 0)
	#define SHU2_R2_CA_CMD4_RG_RK2_RX_ARCA4_F_DLY	GENMASK(13, 8)
	#define SHU2_R2_CA_CMD4_RG_RK2_RX_ARCA5_R_DLY	GENMASK(21, 16)
	#define SHU2_R2_CA_CMD4_RG_RK2_RX_ARCA5_F_DLY	GENMASK(29, 24)
#define SHU2_R2_CA_CMD5					0x000015b4
	#define SHU2_R2_CA_CMD5_RG_RK2_RX_ARCKE0_R_DLY	GENMASK(5, 0)
	#define SHU2_R2_CA_CMD5_RG_RK2_RX_ARCKE0_F_DLY	GENMASK(13, 8)
	#define SHU2_R2_CA_CMD5_RG_RK2_RX_ARCKE1_R_DLY	GENMASK(21, 16)
	#define SHU2_R2_CA_CMD5_RG_RK2_RX_ARCKE1_F_DLY	GENMASK(29, 24)
#define SHU2_R2_CA_CMD6					0x000015b8
	#define SHU2_R2_CA_CMD6_RG_RK2_RX_ARCKE2_R_DLY	GENMASK(5, 0)
	#define SHU2_R2_CA_CMD6_RG_RK2_RX_ARCKE2_F_DLY	GENMASK(13, 8)
	#define SHU2_R2_CA_CMD6_RG_RK2_RX_ARCS0_R_DLY	GENMASK(21, 16)
	#define SHU2_R2_CA_CMD6_RG_RK2_RX_ARCS0_F_DLY	GENMASK(29, 24)
#define SHU2_R2_CA_CMD7					0x000015bc
	#define SHU2_R2_CA_CMD7_RG_RK2_RX_ARCS1_R_DLY	GENMASK(5, 0)
	#define SHU2_R2_CA_CMD7_RG_RK2_RX_ARCS1_F_DLY	GENMASK(13, 8)
	#define SHU2_R2_CA_CMD7_RG_RK2_RX_ARCS2_R_DLY	GENMASK(21, 16)
	#define SHU2_R2_CA_CMD7_RG_RK2_RX_ARCS2_F_DLY	GENMASK(29, 24)
#define SHU2_R2_CA_CMD8					0x000015c0
	#define SHU2_R2_CA_CMD8_RG_RK2_RX_ARCLK_R_DLY	GENMASK(22, 16)
	#define SHU2_R2_CA_CMD8_RG_RK2_RX_ARCLK_F_DLY	GENMASK(30, 24)
#define SHU2_R2_CA_CMD9					0x000015c4
	#define SHU2_R2_CA_CMD9_RG_RK2_ARPI_CS		GENMASK(5, 0)
	#define SHU2_R2_CA_CMD9_RG_RK2_ARPI_CMD		GENMASK(13, 8)
	#define SHU2_R2_CA_CMD9_RG_RK2_ARPI_CLK		GENMASK(29, 24)
#define RFU_0X15C8					0x000015c8
	#define RFU_0X15C8_RESERVED_0X15C8		GENMASK(31, 0)
#define RFU_0X15CC					0x000015cc
	#define RFU_0X15CC_RESERVED_0X15CC		GENMASK(31, 0)
#define SHU3_B0_DQ0					0x00001600
	#define SHU3_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0	BIT(4)
	#define SHU3_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0	GENMASK(10, 8)
	#define SHU3_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0	GENMASK(14, 12)
	#define SHU3_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0	BIT(20)
	#define SHU3_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0	GENMASK(26, 24)
	#define SHU3_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0	GENMASK(30, 28)
	#define SHU3_B0_DQ0_R_LP4Y_WDN_MODE_DQS0	BIT(31)
#define SHU3_B0_DQ1					0x00001604
	#define SHU3_B0_DQ1_RG_TX_ARDQ_DRVP_B0		GENMASK(4, 0)
	#define SHU3_B0_DQ1_RG_TX_ARDQ_DRVN_B0		GENMASK(12, 8)
	#define SHU3_B0_DQ1_RG_TX_ARDQ_ODTP_B0		GENMASK(20, 16)
	#define SHU3_B0_DQ1_RG_TX_ARDQ_ODTN_B0		GENMASK(28, 24)
#define SHU3_B0_DQ2					0x00001608
	#define SHU3_B0_DQ2_RG_TX_ARDQS0_DRVP_B0	GENMASK(4, 0)
	#define SHU3_B0_DQ2_RG_TX_ARDQS0_DRVN_B0	GENMASK(12, 8)
	#define SHU3_B0_DQ2_RG_TX_ARDQS0_ODTP_B0	GENMASK(20, 16)
	#define SHU3_B0_DQ2_RG_TX_ARDQS0_ODTN_B0	GENMASK(28, 24)
#define SHU3_B0_DQ3					0x0000160c
	#define SHU3_B0_DQ3_RG_TX_ARDQS0_PU_B0		GENMASK(1, 0)
	#define SHU3_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0	GENMASK(3, 2)
	#define SHU3_B0_DQ3_RG_TX_ARDQS0_PDB_B0		GENMASK(5, 4)
	#define SHU3_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0	GENMASK(7, 6)
	#define SHU3_B0_DQ3_RG_TX_ARDQ_PU_B0		GENMASK(9, 8)
	#define SHU3_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0	GENMASK(11, 10)
	#define SHU3_B0_DQ3_RG_TX_ARDQ_PDB_B0		GENMASK(13, 12)
	#define SHU3_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0	GENMASK(15, 14)
#define SHU3_B0_DQ4					0x00001610
	#define SHU3_B0_DQ4_RG_ARPI_AA_MCK_DL_B0	GENMASK(5, 0)
	#define SHU3_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0	GENMASK(13, 8)
	#define SHU3_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0	GENMASK(21, 16)
#define SHU3_B0_DQ5					0x00001614
	#define SHU3_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0	GENMASK(5, 0)
	#define SHU3_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0	BIT(6)
	#define SHU3_B0_DQ5_RG_ARPI_FB_B0		GENMASK(13, 8)
	#define SHU3_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0	GENMASK(18, 16)
	#define SHU3_B0_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B0	BIT(19)
	#define SHU3_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0	GENMASK(22, 20)
	#define SHU3_B0_DQ5_RG_ARPI_MCTL_B0		GENMASK(29, 24)
#define SHU3_B0_DQ6					0x00001618
	#define SHU3_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0	GENMASK(5, 0)
	#define SHU3_B0_DQ6_RG_ARPI_RESERVE_B0		GENMASK(21, 6)
	#define SHU3_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0	GENMASK(23, 22)
	#define SHU3_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0	GENMASK(25, 24)
	#define SHU3_B0_DQ6_RG_ARPI_MIDPI_EN_B0		BIT(26)
	#define SHU3_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0	BIT(27)
	#define SHU3_B0_DQ6_RG_ARPI_CAP_SEL_B0		GENMASK(29, 28)
	#define SHU3_B0_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B0	BIT(31)
#define SHU3_B0_DQ7					0x0000161c
	#define SHU3_B0_DQ7_R_DMRANKRXDVS_B0		GENMASK(3, 0)
	#define SHU3_B0_DQ7_MIDPI_ENABLE		BIT(4)
	#define SHU3_B0_DQ7_MIDPI_DIV4_ENABLE		BIT(5)
	#define SHU3_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0	BIT(6)
	#define SHU3_B0_DQ7_R_DMDQMDBI_SHU_B0		BIT(7)
	#define SHU3_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0	GENMASK(11, 8)
	#define SHU3_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0	BIT(12)
	#define SHU3_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0	BIT(13)
	#define SHU3_B0_DQ7_R_DMRXTRACK_DQM_EN_B0	BIT(14)
	#define SHU3_B0_DQ7_R_DMRODTEN_B0		BIT(15)
	#define SHU3_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0	BIT(16)
	#define SHU3_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0	BIT(17)
	#define SHU3_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0	BIT(18)
	#define SHU3_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0	BIT(19)
	#define SHU3_B0_DQ7_R_LP4Y_SDN_MODE_DQS0	BIT(20)
	#define SHU3_B0_DQ7_R_DMRXRANK_DQ_EN_B0		BIT(24)
	#define SHU3_B0_DQ7_R_DMRXRANK_DQ_LAT_B0	GENMASK(27, 25)
	#define SHU3_B0_DQ7_R_DMRXRANK_DQS_EN_B0	BIT(28)
	#define SHU3_B0_DQ7_R_DMRXRANK_DQS_LAT_B0	GENMASK(31, 29)
#define SHU3_B0_DQ8					0x00001620
	#define SHU3_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0	GENMASK(14, 0)
	#define SHU3_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0	BIT(15)
	#define SHU3_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0	BIT(19)
	#define SHU3_B0_DQ8_R_RMRODTEN_CG_IG_B0		BIT(20)
	#define SHU3_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0	BIT(21)
	#define SHU3_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0	BIT(22)
	#define SHU3_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0	BIT(23)
	#define SHU3_B0_DQ8_R_DMRXDLY_CG_IG_B0		BIT(24)
	#define SHU3_B0_DQ8_R_DMSTBEN_SYNC_CG_IG_B0	BIT(25)
	#define SHU3_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0	BIT(26)
	#define SHU3_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0	BIT(27)
	#define SHU3_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0	BIT(28)
	#define SHU3_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0	BIT(29)
	#define SHU3_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0	BIT(30)
	#define SHU3_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0	BIT(31)
#define SHU3_B0_DQ9					0x00001624
	#define SHU3_B0_DQ9_RESERVED_0X1624		GENMASK(31, 0)
#define SHU3_B0_DQ10					0x00001628
	#define SHU3_B0_DQ10_RESERVED_0X1628		GENMASK(31, 0)
#define SHU3_B0_DQ11					0x0000162c
	#define SHU3_B0_DQ11_RESERVED_0X162C		GENMASK(31, 0)
#define SHU3_B0_DQ12					0x00001630
	#define SHU3_B0_DQ12_RESERVED_0X1630		GENMASK(31, 0)
#define SHU3_B0_DLL0					0x00001634
	#define SHU3_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU	BIT(0)
	#define SHU3_B0_DLL0_B0_DLL0_RFU		BIT(3)
	#define SHU3_B0_DLL0_RG_ARDLL_FAST_PSJP_B0	BIT(4)
	#define SHU3_B0_DLL0_RG_ARDLL_PHDIV_B0		BIT(9)
	#define SHU3_B0_DLL0_RG_ARDLL_PHJUMP_EN_B0	BIT(10)
	#define SHU3_B0_DLL0_RG_ARDLL_P_GAIN_B0		GENMASK(15, 12)
	#define SHU3_B0_DLL0_RG_ARDLL_IDLECNT_B0	GENMASK(19, 16)
	#define SHU3_B0_DLL0_RG_ARDLL_GAIN_B0		GENMASK(23, 20)
	#define SHU3_B0_DLL0_RG_ARDLL_PHDET_IN_SWAP_B0	BIT(30)
	#define SHU3_B0_DLL0_RG_ARDLL_PHDET_OUT_SEL_B0	BIT(31)
#define SHU3_B0_DLL1					0x00001638
	#define SHU3_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0	BIT(0)
	#define SHU3_B0_DLL1_RG_ARDLL_PS_EN_B0		BIT(1)
	#define SHU3_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0	BIT(2)
	#define SHU3_B0_DLL1_RG_ARDQ_REV_B0		GENMASK(31, 8)
#define SHU3_B1_DQ0					0x00001680
	#define SHU3_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1	BIT(4)
	#define SHU3_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1	GENMASK(10, 8)
	#define SHU3_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1	GENMASK(14, 12)
	#define SHU3_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1	BIT(20)
	#define SHU3_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1	GENMASK(26, 24)
	#define SHU3_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1	GENMASK(30, 28)
	#define SHU3_B1_DQ0_R_LP4Y_WDN_MODE_DQS1	BIT(31)
#define SHU3_B1_DQ1					0x00001684
	#define SHU3_B1_DQ1_RG_TX_ARDQ_DRVP_B1		GENMASK(4, 0)
	#define SHU3_B1_DQ1_RG_TX_ARDQ_DRVN_B1		GENMASK(12, 8)
	#define SHU3_B1_DQ1_RG_TX_ARDQ_ODTP_B1		GENMASK(20, 16)
	#define SHU3_B1_DQ1_RG_TX_ARDQ_ODTN_B1		GENMASK(28, 24)
#define SHU3_B1_DQ2					0x00001688
	#define SHU3_B1_DQ2_RG_TX_ARDQS0_DRVP_B1	GENMASK(4, 0)
	#define SHU3_B1_DQ2_RG_TX_ARDQS0_DRVN_B1	GENMASK(12, 8)
	#define SHU3_B1_DQ2_RG_TX_ARDQS0_ODTP_B1	GENMASK(20, 16)
	#define SHU3_B1_DQ2_RG_TX_ARDQS0_ODTN_B1	GENMASK(28, 24)
#define SHU3_B1_DQ3					0x0000168c
	#define SHU3_B1_DQ3_RG_TX_ARDQS0_PU_B1		GENMASK(1, 0)
	#define SHU3_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1	GENMASK(3, 2)
	#define SHU3_B1_DQ3_RG_TX_ARDQS0_PDB_B1		GENMASK(5, 4)
	#define SHU3_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1	GENMASK(7, 6)
	#define SHU3_B1_DQ3_RG_TX_ARDQ_PU_B1		GENMASK(9, 8)
	#define SHU3_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1	GENMASK(11, 10)
	#define SHU3_B1_DQ3_RG_TX_ARDQ_PDB_B1		GENMASK(13, 12)
	#define SHU3_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1	GENMASK(15, 14)
#define SHU3_B1_DQ4					0x00001690
	#define SHU3_B1_DQ4_RG_ARPI_AA_MCK_DL_B1	GENMASK(5, 0)
	#define SHU3_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1	GENMASK(13, 8)
	#define SHU3_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1	GENMASK(21, 16)
#define SHU3_B1_DQ5					0x00001694
	#define SHU3_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1	GENMASK(5, 0)
	#define SHU3_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1	BIT(6)
	#define SHU3_B1_DQ5_RG_ARPI_FB_B1		GENMASK(13, 8)
	#define SHU3_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1	GENMASK(18, 16)
	#define SHU3_B1_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B1	BIT(19)
	#define SHU3_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1	GENMASK(22, 20)
	#define SHU3_B1_DQ5_RG_ARPI_MCTL_B1		GENMASK(29, 24)
#define SHU3_B1_DQ6					0x00001698
	#define SHU3_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1	GENMASK(5, 0)
	#define SHU3_B1_DQ6_RG_ARPI_RESERVE_B1		GENMASK(21, 6)
	#define SHU3_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1	GENMASK(23, 22)
	#define SHU3_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1	GENMASK(25, 24)
	#define SHU3_B1_DQ6_RG_ARPI_MIDPI_EN_B1		BIT(26)
	#define SHU3_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1	BIT(27)
	#define SHU3_B1_DQ6_RG_ARPI_CAP_SEL_B1		GENMASK(29, 28)
	#define SHU3_B1_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B1	BIT(31)
#define SHU3_B1_DQ7					0x0000169c
	#define SHU3_B1_DQ7_R_DMRANKRXDVS_B1		GENMASK(3, 0)
	#define SHU3_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1	BIT(6)
	#define SHU3_B1_DQ7_R_DMDQMDBI_SHU_B1		BIT(7)
	#define SHU3_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1	GENMASK(11, 8)
	#define SHU3_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1	BIT(12)
	#define SHU3_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1	BIT(13)
	#define SHU3_B1_DQ7_R_DMRXTRACK_DQM_EN_B1	BIT(14)
	#define SHU3_B1_DQ7_R_DMRODTEN_B1		BIT(15)
	#define SHU3_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1	BIT(16)
	#define SHU3_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1	BIT(17)
	#define SHU3_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1	BIT(18)
	#define SHU3_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1	BIT(19)
	#define SHU3_B1_DQ7_R_LP4Y_SDN_MODE_DQS1	BIT(20)
	#define SHU3_B1_DQ7_R_DMRXRANK_DQ_EN_B1		BIT(24)
	#define SHU3_B1_DQ7_R_DMRXRANK_DQ_LAT_B1	GENMASK(27, 25)
	#define SHU3_B1_DQ7_R_DMRXRANK_DQS_EN_B1	BIT(28)
	#define SHU3_B1_DQ7_R_DMRXRANK_DQS_LAT_B1	GENMASK(31, 29)
#define SHU3_B1_DQ8					0x000016a0
	#define SHU3_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1	GENMASK(14, 0)
	#define SHU3_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1	BIT(15)
	#define SHU3_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1	BIT(19)
	#define SHU3_B1_DQ8_R_RMRODTEN_CG_IG_B1		BIT(20)
	#define SHU3_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1	BIT(21)
	#define SHU3_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1	BIT(22)
	#define SHU3_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1	BIT(23)
	#define SHU3_B1_DQ8_R_DMRXDLY_CG_IG_B1		BIT(24)
	#define SHU3_B1_DQ8_R_DMSTBEN_SYNC_CG_IG_B1	BIT(25)
	#define SHU3_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1	BIT(26)
	#define SHU3_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1	BIT(27)
	#define SHU3_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1	BIT(28)
	#define SHU3_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1	BIT(29)
	#define SHU3_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1	BIT(30)
	#define SHU3_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1	BIT(31)
#define SHU3_B1_DQ9					0x000016a4
	#define SHU3_B1_DQ9_RESERVED_0X16A4		GENMASK(31, 0)
#define SHU3_B1_DQ10					0x000016a8
	#define SHU3_B1_DQ10_RESERVED_0X16A8		GENMASK(31, 0)
#define SHU3_B1_DQ11					0x000016ac
	#define SHU3_B1_DQ11_RESERVED_0X16AC		GENMASK(31, 0)
#define SHU3_B1_DQ12					0x000016b0
	#define SHU3_B1_DQ12_RESERVED_0X16B0		GENMASK(31, 0)
#define SHU3_B1_DLL0					0x000016b4
	#define SHU3_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU	BIT(0)
	#define SHU3_B1_DLL0_B1_DLL0_RFU		BIT(3)
	#define SHU3_B1_DLL0_RG_ARDLL_FAST_PSJP_B1	BIT(4)
	#define SHU3_B1_DLL0_RG_ARDLL_PHDIV_B1		BIT(9)
	#define SHU3_B1_DLL0_RG_ARDLL_PHJUMP_EN_B1	BIT(10)
	#define SHU3_B1_DLL0_RG_ARDLL_P_GAIN_B1		GENMASK(15, 12)
	#define SHU3_B1_DLL0_RG_ARDLL_IDLECNT_B1	GENMASK(19, 16)
	#define SHU3_B1_DLL0_RG_ARDLL_GAIN_B1		GENMASK(23, 20)
	#define SHU3_B1_DLL0_RG_ARDLL_PHDET_IN_SWAP_B1	BIT(30)
	#define SHU3_B1_DLL0_RG_ARDLL_PHDET_OUT_SEL_B1	BIT(31)
#define SHU3_B1_DLL1					0x000016b8
	#define SHU3_B1_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B1	BIT(0)
	#define SHU3_B1_DLL1_RG_ARDLL_PS_EN_B1		BIT(1)
	#define SHU3_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1	BIT(2)
	#define SHU3_B1_DLL1_RG_ARDQ_REV_B1		GENMASK(31, 8)
#define SHU3_CA_CMD0					0x00001700
	#define SHU3_CA_CMD0_RG_TX_ARCLK_PRE_EN		BIT(4)
	#define SHU3_CA_CMD0_RG_TX_ARCLK_DRVP_PRE	GENMASK(10, 8)
	#define SHU3_CA_CMD0_RG_TX_ARCLK_DRVN_PRE	GENMASK(14, 12)
	#define SHU3_CA_CMD0_RG_CGEN_FMEM_CK_CG_DLL	BIT(17)
	#define SHU3_CA_CMD0_RG_FB_CK_MUX		GENMASK(19, 18)
	#define SHU3_CA_CMD0_RG_TX_ARCMD_PRE_EN		BIT(20)
	#define SHU3_CA_CMD0_RG_TX_ARCMD_DRVP_PRE	GENMASK(26, 24)
	#define SHU3_CA_CMD0_RG_TX_ARCMD_DRVN_PRE	GENMASK(30, 28)
	#define SHU3_CA_CMD0_R_LP4Y_WDN_MODE_CLK	BIT(31)
#define SHU3_CA_CMD1					0x00001704
	#define SHU3_CA_CMD1_RG_TX_ARCMD_DRVP		GENMASK(4, 0)
	#define SHU3_CA_CMD1_RG_TX_ARCMD_DRVN		GENMASK(12, 8)
	#define SHU3_CA_CMD1_RG_TX_ARCMD_ODTP		GENMASK(20, 16)
	#define SHU3_CA_CMD1_RG_TX_ARCMD_ODTN		GENMASK(28, 24)
#define SHU3_CA_CMD2					0x00001708
	#define SHU3_CA_CMD2_RG_TX_ARCLK_DRVP		GENMASK(4, 0)
	#define SHU3_CA_CMD2_RG_TX_ARCLK_DRVN		GENMASK(12, 8)
	#define SHU3_CA_CMD2_RG_TX_ARCLK_ODTP		GENMASK(20, 16)
	#define SHU3_CA_CMD2_RG_TX_ARCLK_ODTN		GENMASK(28, 24)
#define SHU3_CA_CMD3					0x0000170c
	#define SHU3_CA_CMD3_RG_TX_ARCLK_PU		GENMASK(1, 0)
	#define SHU3_CA_CMD3_RG_TX_ARCLK_PU_PRE		GENMASK(3, 2)
	#define SHU3_CA_CMD3_RG_TX_ARCLK_PDB		GENMASK(5, 4)
	#define SHU3_CA_CMD3_RG_TX_ARCLK_PDB_PRE	GENMASK(7, 6)
	#define SHU3_CA_CMD3_RG_TX_ARCMD_PU		GENMASK(9, 8)
	#define SHU3_CA_CMD3_RG_TX_ARCMD_PU_PRE		GENMASK(11, 10)
	#define SHU3_CA_CMD3_RG_TX_ARCMD_PDB		GENMASK(13, 12)
	#define SHU3_CA_CMD3_RG_TX_ARCMD_PDB_PRE	GENMASK(15, 14)
#define SHU3_CA_CMD4					0x00001710
	#define SHU3_CA_CMD4_RG_ARPI_AA_MCK_DL_CA	GENMASK(5, 0)
	#define SHU3_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA	GENMASK(13, 8)
	#define SHU3_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA	GENMASK(21, 16)
#define SHU3_CA_CMD5					0x00001714
	#define SHU3_CA_CMD5_RG_RX_ARCMD_VREF_SEL	GENMASK(5, 0)
	#define SHU3_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS	BIT(6)
	#define SHU3_CA_CMD5_RG_ARPI_FB_CA		GENMASK(13, 8)
	#define SHU3_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY	GENMASK(18, 16)
	#define SHU3_CA_CMD5_DA_RX_ARCLK_DQSIEN_RB_DLY	BIT(19)
	#define SHU3_CA_CMD5_RG_RX_ARCLK_DVS_DLY	GENMASK(22, 20)
	#define SHU3_CA_CMD5_RG_ARPI_MCTL_CA		GENMASK(29, 24)
#define SHU3_CA_CMD6					0x00001718
	#define SHU3_CA_CMD6_RG_ARPI_OFFSET_CLKIEN	GENMASK(5, 0)
	#define SHU3_CA_CMD6_RG_ARPI_RESERVE_CA		GENMASK(21, 6)
	#define SHU3_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA	GENMASK(23, 22)
	#define SHU3_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA	GENMASK(25, 24)
	#define SHU3_CA_CMD6_RG_ARPI_MIDPI_EN_CA	BIT(26)
	#define SHU3_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA	BIT(27)
	#define SHU3_CA_CMD6_RG_ARPI_CAP_SEL_CA		GENMASK(29, 28)
	#define SHU3_CA_CMD6_RG_ARPI_MIDPI_BYPASS_EN_CA	BIT(31)
#define SHU3_CA_CMD7					0x0000171c
	#define SHU3_CA_CMD7_R_DMRANKRXDVS_CA		GENMASK(3, 0)
	#define SHU3_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA	BIT(12)
	#define SHU3_CA_CMD7_R_DMRODTEN_CA		BIT(15)
	#define SHU3_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA	BIT(16)
	#define SHU3_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW	BIT(17)
	#define SHU3_CA_CMD7_R_DMTX_ARPI_CG_CLK_NEW	BIT(18)
	#define SHU3_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW	BIT(19)
	#define SHU3_CA_CMD7_R_LP4Y_SDN_MODE_CLK	BIT(20)
	#define SHU3_CA_CMD7_R_DMRXRANK_CMD_EN		BIT(24)
	#define SHU3_CA_CMD7_R_DMRXRANK_CMD_LAT		GENMASK(27, 25)
	#define SHU3_CA_CMD7_R_DMRXRANK_CLK_EN		BIT(28)
	#define SHU3_CA_CMD7_R_DMRXRANK_CLK_LAT		GENMASK(31, 29)
#define SHU3_CA_CMD8					0x00001720
	#define SHU3_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA	GENMASK(14, 0)
	#define SHU3_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA	BIT(15)
	#define SHU3_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA	BIT(19)
	#define SHU3_CA_CMD8_R_RMRODTEN_CG_IG_CA	BIT(20)
	#define SHU3_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA	BIT(21)
	#define SHU3_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA	BIT(22)
	#define SHU3_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA	BIT(23)
	#define SHU3_CA_CMD8_R_DMRXDLY_CG_IG_CA		BIT(24)
	#define SHU3_CA_CMD8_R_DMSTBEN_SYNC_CG_IG_CA	BIT(25)
	#define SHU3_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA	BIT(26)
	#define SHU3_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA	BIT(27)
	#define SHU3_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA	BIT(28)
	#define SHU3_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA	BIT(29)
	#define SHU3_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA	BIT(30)
	#define SHU3_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA	BIT(31)
#define SHU3_CA_CMD9					0x00001724
	#define SHU3_CA_CMD9_RESERVED_0X1724		GENMASK(31, 0)
#define SHU3_CA_CMD10					0x00001728
	#define SHU3_CA_CMD10_RESERVED_0X1728		GENMASK(31, 0)
#define SHU3_CA_CMD11					0x0000172c
	#define SHU3_CA_CMD11_RG_RIMP_REV		GENMASK(7, 0)
	#define SHU3_CA_CMD11_RG_RIMP_VREF_SEL		GENMASK(13, 8)
	#define SHU3_CA_CMD11_RG_TX_ARCKE_DRVP		GENMASK(21, 17)
	#define SHU3_CA_CMD11_RG_TX_ARCKE_DRVN		GENMASK(26, 22)
#define SHU3_CA_CMD12					0x00001730
	#define SHU3_CA_CMD12_RESERVED_0X1730		GENMASK(31, 0)
#define SHU3_CA_DLL0					0x00001734
	#define SHU3_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU	BIT(0)
	#define SHU3_CA_DLL0_CA_DLL0_RFU		BIT(3)
	#define SHU3_CA_DLL0_RG_ARDLL_FAST_PSJP_CA	BIT(4)
	#define SHU3_CA_DLL0_RG_ARDLL_PHDIV_CA		BIT(9)
	#define SHU3_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA	BIT(10)
	#define SHU3_CA_DLL0_RG_ARDLL_P_GAIN_CA		GENMASK(15, 12)
	#define SHU3_CA_DLL0_RG_ARDLL_IDLECNT_CA	GENMASK(19, 16)
	#define SHU3_CA_DLL0_RG_ARDLL_GAIN_CA		GENMASK(23, 20)
	#define SHU3_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA	BIT(30)
	#define SHU3_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA	BIT(31)
#define SHU3_CA_DLL1					0x00001738
	#define SHU3_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA	BIT(0)
	#define SHU3_CA_DLL1_RG_ARDLL_PS_EN_CA		BIT(1)
	#define SHU3_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA	BIT(2)
	#define SHU3_CA_DLL1_RG_ARCMD_REV		GENMASK(31, 8)
#define SHU3_MISC0					0x000017f0
	#define SHU3_MISC0_R_RX_PIPE_BYPASS_EN		BIT(1)
	#define SHU3_MISC0_RG_CMD_TXPIPE_BYPASS_EN	BIT(2)
	#define SHU3_MISC0_RG_CK_TXPIPE_BYPASS_EN	BIT(3)
	#define SHU3_MISC0_RG_RVREF_SEL_DQ		GENMASK(21, 16)
	#define SHU3_MISC0_RG_RVREF_DDR4_SEL		BIT(22)
	#define SHU3_MISC0_RG_RVREF_DDR3_SEL		BIT(23)
	#define SHU3_MISC0_RG_RVREF_SEL_CMD		GENMASK(29, 24)
#define SHU3_R0_B0_DQ0					0x00001800
	#define SHU3_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0	GENMASK(3, 0)
	#define SHU3_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0	GENMASK(7, 4)
	#define SHU3_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0	GENMASK(11, 8)
	#define SHU3_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0	GENMASK(15, 12)
	#define SHU3_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0	GENMASK(19, 16)
	#define SHU3_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0	GENMASK(23, 20)
	#define SHU3_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0	GENMASK(27, 24)
	#define SHU3_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0	GENMASK(31, 28)
#define SHU3_R0_B0_DQ1					0x00001804
	#define SHU3_R0_B0_DQ1_RK0_TX_ARDQM0_DLY_B0	GENMASK(3, 0)
	#define SHU3_R0_B0_DQ1_RK0_TX_ARDQS0_DLYB_B0	GENMASK(19, 16)
	#define SHU3_R0_B0_DQ1_RK0_TX_ARDQS0B_DLYB_B0	GENMASK(23, 20)
	#define SHU3_R0_B0_DQ1_RK0_TX_ARDQS0_DLY_B0	GENMASK(27, 24)
	#define SHU3_R0_B0_DQ1_RK0_TX_ARDQS0B_DLY_B0	GENMASK(31, 28)
#define SHU3_R0_B0_DQ2					0x00001808
	#define SHU3_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R0_B0_DQ2_RK0_RX_ARDQ0_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0	GENMASK(21, 16)
	#define SHU3_R0_B0_DQ2_RK0_RX_ARDQ1_F_DLY_B0	GENMASK(29, 24)
#define SHU3_R0_B0_DQ3					0x0000180c
	#define SHU3_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R0_B0_DQ3_RK0_RX_ARDQ2_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0	GENMASK(21, 16)
	#define SHU3_R0_B0_DQ3_RK0_RX_ARDQ3_F_DLY_B0	GENMASK(29, 24)
#define SHU3_R0_B0_DQ4					0x00001810
	#define SHU3_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R0_B0_DQ4_RK0_RX_ARDQ4_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0	GENMASK(21, 16)
	#define SHU3_R0_B0_DQ4_RK0_RX_ARDQ5_F_DLY_B0	GENMASK(29, 24)
#define SHU3_R0_B0_DQ5					0x00001814
	#define SHU3_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R0_B0_DQ5_RK0_RX_ARDQ6_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0	GENMASK(21, 16)
	#define SHU3_R0_B0_DQ5_RK0_RX_ARDQ7_F_DLY_B0	GENMASK(29, 24)
#define SHU3_R0_B0_DQ6					0x00001818
	#define SHU3_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0	GENMASK(22, 16)
	#define SHU3_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0	GENMASK(30, 24)
#define SHU3_R0_B0_DQ7					0x0000181c
	#define SHU3_R0_B0_DQ7_RK0_ARPI_DQ_B0		GENMASK(13, 8)
	#define SHU3_R0_B0_DQ7_RK0_ARPI_DQM_B0		GENMASK(21, 16)
	#define SHU3_R0_B0_DQ7_RK0_ARPI_PBYTE_B0	GENMASK(29, 24)
#define RFU_0X1820					0x00001820
	#define RFU_0X1820_RESERVED_0X1820		GENMASK(31, 0)
#define RFU_0X1824					0x00001824
	#define RFU_0X1824_RESERVED_0X1824		GENMASK(31, 0)
#define RFU_0X1828					0x00001828
	#define RFU_0X1828_RESERVED_0X1828		GENMASK(31, 0)
#define RFU_0X182C					0x0000182c
	#define RFU_0X182C_RESERVED_0X182C		GENMASK(31, 0)
#define SHU3_R0_B1_DQ0					0x00001850
	#define SHU3_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1	GENMASK(3, 0)
	#define SHU3_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1	GENMASK(7, 4)
	#define SHU3_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1	GENMASK(11, 8)
	#define SHU3_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1	GENMASK(15, 12)
	#define SHU3_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1	GENMASK(19, 16)
	#define SHU3_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1	GENMASK(23, 20)
	#define SHU3_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1	GENMASK(27, 24)
	#define SHU3_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1	GENMASK(31, 28)
#define SHU3_R0_B1_DQ1					0x00001854
	#define SHU3_R0_B1_DQ1_RK0_TX_ARDQM0_DLY_B1	GENMASK(3, 0)
	#define SHU3_R0_B1_DQ1_RK0_TX_ARDQS0_DLYB_B1	GENMASK(19, 16)
	#define SHU3_R0_B1_DQ1_RK0_TX_ARDQS0B_DLYB_B1	GENMASK(23, 20)
	#define SHU3_R0_B1_DQ1_RK0_TX_ARDQS0_DLY_B1	GENMASK(27, 24)
	#define SHU3_R0_B1_DQ1_RK0_TX_ARDQS0B_DLY_B1	GENMASK(31, 28)
#define SHU3_R0_B1_DQ2					0x00001858
	#define SHU3_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R0_B1_DQ2_RK0_RX_ARDQ0_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1	GENMASK(21, 16)
	#define SHU3_R0_B1_DQ2_RK0_RX_ARDQ1_F_DLY_B1	GENMASK(29, 24)
#define SHU3_R0_B1_DQ3					0x0000185c
	#define SHU3_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R0_B1_DQ3_RK0_RX_ARDQ2_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1	GENMASK(21, 16)
	#define SHU3_R0_B1_DQ3_RK0_RX_ARDQ3_F_DLY_B1	GENMASK(29, 24)
#define SHU3_R0_B1_DQ4					0x00001860
	#define SHU3_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R0_B1_DQ4_RK0_RX_ARDQ4_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1	GENMASK(21, 16)
	#define SHU3_R0_B1_DQ4_RK0_RX_ARDQ5_F_DLY_B1	GENMASK(29, 24)
#define SHU3_R0_B1_DQ5					0x00001864
	#define SHU3_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R0_B1_DQ5_RK0_RX_ARDQ6_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1	GENMASK(21, 16)
	#define SHU3_R0_B1_DQ5_RK0_RX_ARDQ7_F_DLY_B1	GENMASK(29, 24)
#define SHU3_R0_B1_DQ6					0x00001868
	#define SHU3_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R0_B1_DQ6_RK0_RX_ARDQM0_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1	GENMASK(22, 16)
	#define SHU3_R0_B1_DQ6_RK0_RX_ARDQS0_F_DLY_B1	GENMASK(30, 24)
#define SHU3_R0_B1_DQ7					0x0000186c
	#define SHU3_R0_B1_DQ7_RK0_ARPI_DQ_B1		GENMASK(13, 8)
	#define SHU3_R0_B1_DQ7_RK0_ARPI_DQM_B1		GENMASK(21, 16)
	#define SHU3_R0_B1_DQ7_RK0_ARPI_PBYTE_B1	GENMASK(29, 24)
#define RFU_0X1870					0x00001870
	#define RFU_0X1870_RESERVED_0X1870		GENMASK(31, 0)
#define RFU_0X1874					0x00001874
	#define RFU_0X1874_RESERVED_0X1874		GENMASK(31, 0)
#define RFU_0X1878					0x00001878
	#define RFU_0X1878_RESERVED_0X1878		GENMASK(31, 0)
#define RFU_0X187C					0x0000187c
	#define RFU_0X187C_RESERVED_0X187C		GENMASK(31, 0)
#define SHU3_R0_CA_CMD0					0x000018a0
	#define SHU3_R0_CA_CMD0_RK0_TX_ARCA0_DLY	GENMASK(3, 0)
	#define SHU3_R0_CA_CMD0_RK0_TX_ARCA1_DLY	GENMASK(7, 4)
	#define SHU3_R0_CA_CMD0_RK0_TX_ARCA2_DLY	GENMASK(11, 8)
	#define SHU3_R0_CA_CMD0_RK0_TX_ARCA3_DLY	GENMASK(15, 12)
	#define SHU3_R0_CA_CMD0_RK0_TX_ARCA4_DLY	GENMASK(19, 16)
	#define SHU3_R0_CA_CMD0_RK0_TX_ARCA5_DLY	GENMASK(23, 20)
	#define SHU3_R0_CA_CMD0_RK0_TX_ARCLK_DLYB	GENMASK(27, 24)
	#define SHU3_R0_CA_CMD0_RK0_TX_ARCLKB_DLYB	GENMASK(31, 28)
#define SHU3_R0_CA_CMD1					0x000018a4
	#define SHU3_R0_CA_CMD1_RK0_TX_ARCKE0_DLY	GENMASK(3, 0)
	#define SHU3_R0_CA_CMD1_RK0_TX_ARCKE1_DLY	GENMASK(7, 4)
	#define SHU3_R0_CA_CMD1_RK0_TX_ARCKE2_DLY	GENMASK(11, 8)
	#define SHU3_R0_CA_CMD1_RK0_TX_ARCS0_DLY	GENMASK(15, 12)
	#define SHU3_R0_CA_CMD1_RK0_TX_ARCS1_DLY	GENMASK(19, 16)
	#define SHU3_R0_CA_CMD1_RK0_TX_ARCS2_DLY	GENMASK(23, 20)
	#define SHU3_R0_CA_CMD1_RK0_TX_ARCLK_DLY	GENMASK(27, 24)
	#define SHU3_R0_CA_CMD1_RK0_TX_ARCLKB_DLY	GENMASK(31, 28)
#define SHU3_R0_CA_CMD2					0x000018a8
	#define SHU3_R0_CA_CMD2_RG_RK0_RX_ARCA0_R_DLY	GENMASK(5, 0)
	#define SHU3_R0_CA_CMD2_RG_RK0_RX_ARCA0_F_DLY	GENMASK(13, 8)
	#define SHU3_R0_CA_CMD2_RG_RK0_RX_ARCA1_R_DLY	GENMASK(21, 16)
	#define SHU3_R0_CA_CMD2_RG_RK0_RX_ARCA1_F_DLY	GENMASK(29, 24)
#define SHU3_R0_CA_CMD3					0x000018ac
	#define SHU3_R0_CA_CMD3_RG_RK0_RX_ARCA2_R_DLY	GENMASK(5, 0)
	#define SHU3_R0_CA_CMD3_RG_RK0_RX_ARCA2_F_DLY	GENMASK(13, 8)
	#define SHU3_R0_CA_CMD3_RG_RK0_RX_ARCA3_R_DLY	GENMASK(21, 16)
	#define SHU3_R0_CA_CMD3_RG_RK0_RX_ARCA3_F_DLY	GENMASK(29, 24)
#define SHU3_R0_CA_CMD4					0x000018b0
	#define SHU3_R0_CA_CMD4_RG_RK0_RX_ARCA4_R_DLY	GENMASK(5, 0)
	#define SHU3_R0_CA_CMD4_RG_RK0_RX_ARCA4_F_DLY	GENMASK(13, 8)
	#define SHU3_R0_CA_CMD4_RG_RK0_RX_ARCA5_R_DLY	GENMASK(21, 16)
	#define SHU3_R0_CA_CMD4_RG_RK0_RX_ARCA5_F_DLY	GENMASK(29, 24)
#define SHU3_R0_CA_CMD5					0x000018b4
	#define SHU3_R0_CA_CMD5_RG_RK0_RX_ARCKE0_R_DLY	GENMASK(5, 0)
	#define SHU3_R0_CA_CMD5_RG_RK0_RX_ARCKE0_F_DLY	GENMASK(13, 8)
	#define SHU3_R0_CA_CMD5_RG_RK0_RX_ARCKE1_R_DLY	GENMASK(21, 16)
	#define SHU3_R0_CA_CMD5_RG_RK0_RX_ARCKE1_F_DLY	GENMASK(29, 24)
#define SHU3_R0_CA_CMD6					0x000018b8
	#define SHU3_R0_CA_CMD6_RG_RK0_RX_ARCKE2_R_DLY	GENMASK(5, 0)
	#define SHU3_R0_CA_CMD6_RG_RK0_RX_ARCKE2_F_DLY	GENMASK(13, 8)
	#define SHU3_R0_CA_CMD6_RG_RK0_RX_ARCS0_R_DLY	GENMASK(21, 16)
	#define SHU3_R0_CA_CMD6_RG_RK0_RX_ARCS0_F_DLY	GENMASK(29, 24)
#define SHU3_R0_CA_CMD7					0x000018bc
	#define SHU3_R0_CA_CMD7_RG_RK0_RX_ARCS1_R_DLY	GENMASK(5, 0)
	#define SHU3_R0_CA_CMD7_RG_RK0_RX_ARCS1_F_DLY	GENMASK(13, 8)
	#define SHU3_R0_CA_CMD7_RG_RK0_RX_ARCS2_R_DLY	GENMASK(21, 16)
	#define SHU3_R0_CA_CMD7_RG_RK0_RX_ARCS2_F_DLY	GENMASK(29, 24)
#define SHU3_R0_CA_CMD8					0x000018c0
	#define SHU3_R0_CA_CMD8_RG_RK0_RX_ARCLK_R_DLY	GENMASK(22, 16)
	#define SHU3_R0_CA_CMD8_RG_RK0_RX_ARCLK_F_DLY	GENMASK(30, 24)
#define SHU3_R0_CA_CMD9					0x000018c4
	#define SHU3_R0_CA_CMD9_RG_RK0_ARPI_CS		GENMASK(5, 0)
	#define SHU3_R0_CA_CMD9_RG_RK0_ARPI_CMD		GENMASK(13, 8)
	#define SHU3_R0_CA_CMD9_RG_RK0_ARPI_CLK		GENMASK(29, 24)
#define RFU_0X18C8					0x000018c8
	#define RFU_0X18C8_RESERVED_0X18C8		GENMASK(31, 0)
#define RFU_0X18CC					0x000018cc
	#define RFU_0X18CC_RESERVED_0X18CC		GENMASK(31, 0)
#define SHU3_R1_B0_DQ0					0x00001900
	#define SHU3_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0	GENMASK(3, 0)
	#define SHU3_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0	GENMASK(7, 4)
	#define SHU3_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0	GENMASK(11, 8)
	#define SHU3_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0	GENMASK(15, 12)
	#define SHU3_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0	GENMASK(19, 16)
	#define SHU3_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0	GENMASK(23, 20)
	#define SHU3_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0	GENMASK(27, 24)
	#define SHU3_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0	GENMASK(31, 28)
#define SHU3_R1_B0_DQ1					0x00001904
	#define SHU3_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0	GENMASK(3, 0)
	#define SHU3_R1_B0_DQ1_RK1_TX_ARDQS0_DLYB_B0	GENMASK(19, 16)
	#define SHU3_R1_B0_DQ1_RK1_TX_ARDQS0B_DLYB_B0	GENMASK(23, 20)
	#define SHU3_R1_B0_DQ1_RK1_TX_ARDQS0_DLY_B0	GENMASK(27, 24)
	#define SHU3_R1_B0_DQ1_RK1_TX_ARDQS0B_DLY_B0	GENMASK(31, 28)
#define SHU3_R1_B0_DQ2					0x00001908
	#define SHU3_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R1_B0_DQ2_RK1_RX_ARDQ0_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0	GENMASK(21, 16)
	#define SHU3_R1_B0_DQ2_RK1_RX_ARDQ1_F_DLY_B0	GENMASK(29, 24)
#define SHU3_R1_B0_DQ3					0x0000190c
	#define SHU3_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R1_B0_DQ3_RK1_RX_ARDQ2_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0	GENMASK(21, 16)
	#define SHU3_R1_B0_DQ3_RK1_RX_ARDQ3_F_DLY_B0	GENMASK(29, 24)
#define SHU3_R1_B0_DQ4					0x00001910
	#define SHU3_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R1_B0_DQ4_RK1_RX_ARDQ4_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0	GENMASK(21, 16)
	#define SHU3_R1_B0_DQ4_RK1_RX_ARDQ5_F_DLY_B0	GENMASK(29, 24)
#define SHU3_R1_B0_DQ5					0x00001914
	#define SHU3_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R1_B0_DQ5_RK1_RX_ARDQ6_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0	GENMASK(21, 16)
	#define SHU3_R1_B0_DQ5_RK1_RX_ARDQ7_F_DLY_B0	GENMASK(29, 24)
#define SHU3_R1_B0_DQ6					0x00001918
	#define SHU3_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R1_B0_DQ6_RK1_RX_ARDQM0_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0	GENMASK(22, 16)
	#define SHU3_R1_B0_DQ6_RK1_RX_ARDQS0_F_DLY_B0	GENMASK(30, 24)
#define SHU3_R1_B0_DQ7					0x0000191c
	#define SHU3_R1_B0_DQ7_RK1_ARPI_DQ_B0		GENMASK(13, 8)
	#define SHU3_R1_B0_DQ7_RK1_ARPI_DQM_B0		GENMASK(21, 16)
	#define SHU3_R1_B0_DQ7_RK1_ARPI_PBYTE_B0	GENMASK(29, 24)
#define RFU_0X1920					0x00001920
	#define RFU_0X1920_RESERVED_0X1920		GENMASK(31, 0)
#define RFU_0X1924					0x00001924
	#define RFU_0X1924_RESERVED_0X1924		GENMASK(31, 0)
#define RFU_0X1928					0x00001928
	#define RFU_0X1928_RESERVED_0X1928		GENMASK(31, 0)
#define RFU_0X192C					0x0000192c
	#define RFU_0X192C_RESERVED_0X192C		GENMASK(31, 0)
#define SHU3_R1_B1_DQ0					0x00001950
	#define SHU3_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1	GENMASK(3, 0)
	#define SHU3_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1	GENMASK(7, 4)
	#define SHU3_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1	GENMASK(11, 8)
	#define SHU3_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1	GENMASK(15, 12)
	#define SHU3_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1	GENMASK(19, 16)
	#define SHU3_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1	GENMASK(23, 20)
	#define SHU3_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1	GENMASK(27, 24)
	#define SHU3_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1	GENMASK(31, 28)
#define SHU3_R1_B1_DQ1					0x00001954
	#define SHU3_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1	GENMASK(3, 0)
	#define SHU3_R1_B1_DQ1_RK1_TX_ARDQS0_DLYB_B1	GENMASK(19, 16)
	#define SHU3_R1_B1_DQ1_RK1_TX_ARDQS0B_DLYB_B1	GENMASK(23, 20)
	#define SHU3_R1_B1_DQ1_RK1_TX_ARDQS0_DLY_B1	GENMASK(27, 24)
	#define SHU3_R1_B1_DQ1_RK1_TX_ARDQS0B_DLY_B1	GENMASK(31, 28)
#define SHU3_R1_B1_DQ2					0x00001958
	#define SHU3_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R1_B1_DQ2_RK1_RX_ARDQ0_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1	GENMASK(21, 16)
	#define SHU3_R1_B1_DQ2_RK1_RX_ARDQ1_F_DLY_B1	GENMASK(29, 24)
#define SHU3_R1_B1_DQ3					0x0000195c
	#define SHU3_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R1_B1_DQ3_RK1_RX_ARDQ2_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1	GENMASK(21, 16)
	#define SHU3_R1_B1_DQ3_RK1_RX_ARDQ3_F_DLY_B1	GENMASK(29, 24)
#define SHU3_R1_B1_DQ4					0x00001960
	#define SHU3_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R1_B1_DQ4_RK1_RX_ARDQ4_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1	GENMASK(21, 16)
	#define SHU3_R1_B1_DQ4_RK1_RX_ARDQ5_F_DLY_B1	GENMASK(29, 24)
#define SHU3_R1_B1_DQ5					0x00001964
	#define SHU3_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R1_B1_DQ5_RK1_RX_ARDQ6_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1	GENMASK(21, 16)
	#define SHU3_R1_B1_DQ5_RK1_RX_ARDQ7_F_DLY_B1	GENMASK(29, 24)
#define SHU3_R1_B1_DQ6					0x00001968
	#define SHU3_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R1_B1_DQ6_RK1_RX_ARDQM0_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1	GENMASK(22, 16)
	#define SHU3_R1_B1_DQ6_RK1_RX_ARDQS0_F_DLY_B1	GENMASK(30, 24)
#define SHU3_R1_B1_DQ7					0x0000196c
	#define SHU3_R1_B1_DQ7_RK1_ARPI_DQ_B1		GENMASK(13, 8)
	#define SHU3_R1_B1_DQ7_RK1_ARPI_DQM_B1		GENMASK(21, 16)
	#define SHU3_R1_B1_DQ7_RK1_ARPI_PBYTE_B1	GENMASK(29, 24)
#define RFU_0X1970					0x00001970
	#define RFU_0X1970_RESERVED_0X1970		GENMASK(31, 0)
#define RFU_0X1974					0x00001974
	#define RFU_0X1974_RESERVED_0X1974		GENMASK(31, 0)
#define RFU_0X1978					0x00001978
	#define RFU_0X1978_RESERVED_0X1978		GENMASK(31, 0)
#define RFU_0X197C					0x0000197c
	#define RFU_0X197C_RESERVED_0X197C		GENMASK(31, 0)
#define SHU3_R1_CA_CMD0					0x000019a0
	#define SHU3_R1_CA_CMD0_RK1_TX_ARCA0_DLY	GENMASK(3, 0)
	#define SHU3_R1_CA_CMD0_RK1_TX_ARCA1_DLY	GENMASK(7, 4)
	#define SHU3_R1_CA_CMD0_RK1_TX_ARCA2_DLY	GENMASK(11, 8)
	#define SHU3_R1_CA_CMD0_RK1_TX_ARCA3_DLY	GENMASK(15, 12)
	#define SHU3_R1_CA_CMD0_RK1_TX_ARCA4_DLY	GENMASK(19, 16)
	#define SHU3_R1_CA_CMD0_RK1_TX_ARCA5_DLY	GENMASK(23, 20)
	#define SHU3_R1_CA_CMD0_RK1_TX_ARCLK_DLYB	GENMASK(27, 24)
	#define SHU3_R1_CA_CMD0_RK1_TX_ARCLKB_DLYB	GENMASK(31, 28)
#define SHU3_R1_CA_CMD1					0x000019a4
	#define SHU3_R1_CA_CMD1_RK1_TX_ARCKE0_DLY	GENMASK(3, 0)
	#define SHU3_R1_CA_CMD1_RK1_TX_ARCKE1_DLY	GENMASK(7, 4)
	#define SHU3_R1_CA_CMD1_RK1_TX_ARCKE2_DLY	GENMASK(11, 8)
	#define SHU3_R1_CA_CMD1_RK1_TX_ARCS0_DLY	GENMASK(15, 12)
	#define SHU3_R1_CA_CMD1_RK1_TX_ARCS1_DLY	GENMASK(19, 16)
	#define SHU3_R1_CA_CMD1_RK1_TX_ARCS2_DLY	GENMASK(23, 20)
	#define SHU3_R1_CA_CMD1_RK1_TX_ARCLK_DLY	GENMASK(27, 24)
	#define SHU3_R1_CA_CMD1_RK1_TX_ARCLKB_DLY	GENMASK(31, 28)
#define SHU3_R1_CA_CMD2					0x000019a8
	#define SHU3_R1_CA_CMD2_RG_RK1_RX_ARCA0_R_DLY	GENMASK(5, 0)
	#define SHU3_R1_CA_CMD2_RG_RK1_RX_ARCA0_F_DLY	GENMASK(13, 8)
	#define SHU3_R1_CA_CMD2_RG_RK1_RX_ARCA1_R_DLY	GENMASK(21, 16)
	#define SHU3_R1_CA_CMD2_RG_RK1_RX_ARCA1_F_DLY	GENMASK(29, 24)
#define SHU3_R1_CA_CMD3					0x000019ac
	#define SHU3_R1_CA_CMD3_RG_RK1_RX_ARCA2_R_DLY	GENMASK(5, 0)
	#define SHU3_R1_CA_CMD3_RG_RK1_RX_ARCA2_F_DLY	GENMASK(13, 8)
	#define SHU3_R1_CA_CMD3_RG_RK1_RX_ARCA3_R_DLY	GENMASK(21, 16)
	#define SHU3_R1_CA_CMD3_RG_RK1_RX_ARCA3_F_DLY	GENMASK(29, 24)
#define SHU3_R1_CA_CMD4					0x000019b0
	#define SHU3_R1_CA_CMD4_RG_RK1_RX_ARCA4_R_DLY	GENMASK(5, 0)
	#define SHU3_R1_CA_CMD4_RG_RK1_RX_ARCA4_F_DLY	GENMASK(13, 8)
	#define SHU3_R1_CA_CMD4_RG_RK1_RX_ARCA5_R_DLY	GENMASK(21, 16)
	#define SHU3_R1_CA_CMD4_RG_RK1_RX_ARCA5_F_DLY	GENMASK(29, 24)
#define SHU3_R1_CA_CMD5					0x000019b4
	#define SHU3_R1_CA_CMD5_RG_RK1_RX_ARCKE0_R_DLY	GENMASK(5, 0)
	#define SHU3_R1_CA_CMD5_RG_RK1_RX_ARCKE0_F_DLY	GENMASK(13, 8)
	#define SHU3_R1_CA_CMD5_RG_RK1_RX_ARCKE1_R_DLY	GENMASK(21, 16)
	#define SHU3_R1_CA_CMD5_RG_RK1_RX_ARCKE1_F_DLY	GENMASK(29, 24)
#define SHU3_R1_CA_CMD6					0x000019b8
	#define SHU3_R1_CA_CMD6_RG_RK1_RX_ARCKE2_R_DLY	GENMASK(5, 0)
	#define SHU3_R1_CA_CMD6_RG_RK1_RX_ARCKE2_F_DLY	GENMASK(13, 8)
	#define SHU3_R1_CA_CMD6_RG_RK1_RX_ARCS0_R_DLY	GENMASK(21, 16)
	#define SHU3_R1_CA_CMD6_RG_RK1_RX_ARCS0_F_DLY	GENMASK(29, 24)
#define SHU3_R1_CA_CMD7					0x000019bc
	#define SHU3_R1_CA_CMD7_RG_RK1_RX_ARCS1_R_DLY	GENMASK(5, 0)
	#define SHU3_R1_CA_CMD7_RG_RK1_RX_ARCS1_F_DLY	GENMASK(13, 8)
	#define SHU3_R1_CA_CMD7_RG_RK1_RX_ARCS2_R_DLY	GENMASK(21, 16)
	#define SHU3_R1_CA_CMD7_RG_RK1_RX_ARCS2_F_DLY	GENMASK(29, 24)
#define SHU3_R1_CA_CMD8					0x000019c0
	#define SHU3_R1_CA_CMD8_RG_RK1_RX_ARCLK_R_DLY	GENMASK(22, 16)
	#define SHU3_R1_CA_CMD8_RG_RK1_RX_ARCLK_F_DLY	GENMASK(30, 24)
#define SHU3_R1_CA_CMD9					0x000019c4
	#define SHU3_R1_CA_CMD9_RG_RK1_ARPI_CS		GENMASK(5, 0)
	#define SHU3_R1_CA_CMD9_RG_RK1_ARPI_CMD		GENMASK(13, 8)
	#define SHU3_R1_CA_CMD9_RG_RK1_ARPI_CLK		GENMASK(29, 24)
#define RFU_0X19C8					0x000019c8
	#define RFU_0X19C8_RESERVED_0X19C8		GENMASK(31, 0)
#define RFU_0X19CC					0x000019cc
	#define RFU_0X19CC_RESERVED_0X19CC		GENMASK(31, 0)
#define SHU3_R2_B0_DQ0					0x00001a00
	#define SHU3_R2_B0_DQ0_RK2_TX_ARDQ0_DLY_B0	GENMASK(3, 0)
	#define SHU3_R2_B0_DQ0_RK2_TX_ARDQ1_DLY_B0	GENMASK(7, 4)
	#define SHU3_R2_B0_DQ0_RK2_TX_ARDQ2_DLY_B0	GENMASK(11, 8)
	#define SHU3_R2_B0_DQ0_RK2_TX_ARDQ3_DLY_B0	GENMASK(15, 12)
	#define SHU3_R2_B0_DQ0_RK2_TX_ARDQ4_DLY_B0	GENMASK(19, 16)
	#define SHU3_R2_B0_DQ0_RK2_TX_ARDQ5_DLY_B0	GENMASK(23, 20)
	#define SHU3_R2_B0_DQ0_RK2_TX_ARDQ6_DLY_B0	GENMASK(27, 24)
	#define SHU3_R2_B0_DQ0_RK2_TX_ARDQ7_DLY_B0	GENMASK(31, 28)
#define SHU3_R2_B0_DQ1					0x00001a04
	#define SHU3_R2_B0_DQ1_RK2_TX_ARDQM0_DLY_B0	GENMASK(3, 0)
	#define SHU3_R2_B0_DQ1_RK2_TX_ARDQS0_DLYB_B0	GENMASK(19, 16)
	#define SHU3_R2_B0_DQ1_RK2_TX_ARDQS0B_DLYB_B0	GENMASK(23, 20)
	#define SHU3_R2_B0_DQ1_RK2_TX_ARDQS0_DLY_B0	GENMASK(27, 24)
	#define SHU3_R2_B0_DQ1_RK2_TX_ARDQS0B_DLY_B0	GENMASK(31, 28)
#define SHU3_R2_B0_DQ2					0x00001a08
	#define SHU3_R2_B0_DQ2_RK2_RX_ARDQ0_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R2_B0_DQ2_RK2_RX_ARDQ0_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R2_B0_DQ2_RK2_RX_ARDQ1_R_DLY_B0	GENMASK(21, 16)
	#define SHU3_R2_B0_DQ2_RK2_RX_ARDQ1_F_DLY_B0	GENMASK(29, 24)
#define SHU3_R2_B0_DQ3					0x00001a0c
	#define SHU3_R2_B0_DQ3_RK2_RX_ARDQ2_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R2_B0_DQ3_RK2_RX_ARDQ2_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R2_B0_DQ3_RK2_RX_ARDQ3_R_DLY_B0	GENMASK(21, 16)
	#define SHU3_R2_B0_DQ3_RK2_RX_ARDQ3_F_DLY_B0	GENMASK(29, 24)
#define SHU3_R2_B0_DQ4					0x00001a10
	#define SHU3_R2_B0_DQ4_RK2_RX_ARDQ4_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R2_B0_DQ4_RK2_RX_ARDQ4_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R2_B0_DQ4_RK2_RX_ARDQ5_R_DLY_B0	GENMASK(21, 16)
	#define SHU3_R2_B0_DQ4_RK2_RX_ARDQ5_F_DLY_B0	GENMASK(29, 24)
#define SHU3_R2_B0_DQ5					0x00001a14
	#define SHU3_R2_B0_DQ5_RK2_RX_ARDQ6_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R2_B0_DQ5_RK2_RX_ARDQ6_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R2_B0_DQ5_RK2_RX_ARDQ7_R_DLY_B0	GENMASK(21, 16)
	#define SHU3_R2_B0_DQ5_RK2_RX_ARDQ7_F_DLY_B0	GENMASK(29, 24)
#define SHU3_R2_B0_DQ6					0x00001a18
	#define SHU3_R2_B0_DQ6_RK2_RX_ARDQM0_R_DLY_B0	GENMASK(5, 0)
	#define SHU3_R2_B0_DQ6_RK2_RX_ARDQM0_F_DLY_B0	GENMASK(13, 8)
	#define SHU3_R2_B0_DQ6_RK2_RX_ARDQS0_R_DLY_B0	GENMASK(22, 16)
	#define SHU3_R2_B0_DQ6_RK2_RX_ARDQS0_F_DLY_B0	GENMASK(30, 24)
#define SHU3_R2_B0_DQ7					0x00001a1c
	#define SHU3_R2_B0_DQ7_RK2_ARPI_DQ_B0		GENMASK(13, 8)
	#define SHU3_R2_B0_DQ7_RK2_ARPI_DQM_B0		GENMASK(21, 16)
	#define SHU3_R2_B0_DQ7_RK2_ARPI_PBYTE_B0	GENMASK(29, 24)
#define RFU_0X1A20					0x00001a20
	#define RFU_0X1A20_RESERVED_0X1A20		GENMASK(31, 0)
#define RFU_0X1A24					0x00001a24
	#define RFU_0X1A24_RESERVED_0X1A24		GENMASK(31, 0)
#define RFU_0X1A28					0x00001a28
	#define RFU_0X1A28_RESERVED_0X1A28		GENMASK(31, 0)
#define RFU_0X1A2C					0x00001a2c
	#define RFU_0X1A2C_RESERVED_0X1A2C		GENMASK(31, 0)
#define SHU3_R2_B1_DQ0					0x00001a50
	#define SHU3_R2_B1_DQ0_RK2_TX_ARDQ0_DLY_B1	GENMASK(3, 0)
	#define SHU3_R2_B1_DQ0_RK2_TX_ARDQ1_DLY_B1	GENMASK(7, 4)
	#define SHU3_R2_B1_DQ0_RK2_TX_ARDQ2_DLY_B1	GENMASK(11, 8)
	#define SHU3_R2_B1_DQ0_RK2_TX_ARDQ3_DLY_B1	GENMASK(15, 12)
	#define SHU3_R2_B1_DQ0_RK2_TX_ARDQ4_DLY_B1	GENMASK(19, 16)
	#define SHU3_R2_B1_DQ0_RK2_TX_ARDQ5_DLY_B1	GENMASK(23, 20)
	#define SHU3_R2_B1_DQ0_RK2_TX_ARDQ6_DLY_B1	GENMASK(27, 24)
	#define SHU3_R2_B1_DQ0_RK2_TX_ARDQ7_DLY_B1	GENMASK(31, 28)
#define SHU3_R2_B1_DQ1					0x00001a54
	#define SHU3_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1	GENMASK(3, 0)
	#define SHU3_R2_B1_DQ1_RK2_TX_ARDQS0_DLYB_B1	GENMASK(19, 16)
	#define SHU3_R2_B1_DQ1_RK2_TX_ARDQS0B_DLYB_B1	GENMASK(23, 20)
	#define SHU3_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1	GENMASK(27, 24)
	#define SHU3_R2_B1_DQ1_RK2_TX_ARDQS0B_DLY_B1	GENMASK(31, 28)
#define SHU3_R2_B1_DQ2					0x00001a58
	#define SHU3_R2_B1_DQ2_RK2_RX_ARDQ0_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R2_B1_DQ2_RK2_RX_ARDQ0_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R2_B1_DQ2_RK2_RX_ARDQ1_R_DLY_B1	GENMASK(21, 16)
	#define SHU3_R2_B1_DQ2_RK2_RX_ARDQ1_F_DLY_B1	GENMASK(29, 24)
#define SHU3_R2_B1_DQ3					0x00001a5c
	#define SHU3_R2_B1_DQ3_RK2_RX_ARDQ2_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R2_B1_DQ3_RK2_RX_ARDQ2_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R2_B1_DQ3_RK2_RX_ARDQ3_R_DLY_B1	GENMASK(21, 16)
	#define SHU3_R2_B1_DQ3_RK2_RX_ARDQ3_F_DLY_B1	GENMASK(29, 24)
#define SHU3_R2_B1_DQ4					0x00001a60
	#define SHU3_R2_B1_DQ4_RK2_RX_ARDQ4_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R2_B1_DQ4_RK2_RX_ARDQ4_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R2_B1_DQ4_RK2_RX_ARDQ5_R_DLY_B1	GENMASK(21, 16)
	#define SHU3_R2_B1_DQ4_RK2_RX_ARDQ5_F_DLY_B1	GENMASK(29, 24)
#define SHU3_R2_B1_DQ5					0x00001a64
	#define SHU3_R2_B1_DQ5_RK2_RX_ARDQ6_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R2_B1_DQ5_RK2_RX_ARDQ6_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R2_B1_DQ5_RK2_RX_ARDQ7_R_DLY_B1	GENMASK(21, 16)
	#define SHU3_R2_B1_DQ5_RK2_RX_ARDQ7_F_DLY_B1	GENMASK(29, 24)
#define SHU3_R2_B1_DQ6					0x00001a68
	#define SHU3_R2_B1_DQ6_RK2_RX_ARDQM0_R_DLY_B1	GENMASK(5, 0)
	#define SHU3_R2_B1_DQ6_RK2_RX_ARDQM0_F_DLY_B1	GENMASK(13, 8)
	#define SHU3_R2_B1_DQ6_RK2_RX_ARDQS0_R_DLY_B1	GENMASK(22, 16)
	#define SHU3_R2_B1_DQ6_RK2_RX_ARDQS0_F_DLY_B1	GENMASK(30, 24)
#define SHU3_R2_B1_DQ7					0x00001a6c
	#define SHU3_R2_B1_DQ7_RK2_ARPI_DQ_B1		GENMASK(13, 8)
	#define SHU3_R2_B1_DQ7_RK2_ARPI_DQM_B1		GENMASK(21, 16)
	#define SHU3_R2_B1_DQ7_RK2_ARPI_PBYTE_B1	GENMASK(29, 24)
#define RFU_0X1A70					0x00001a70
	#define RFU_0X1A70_RESERVED_0X1A70		GENMASK(31, 0)
#define RFU_0X1A74					0x00001a74
	#define RFU_0X1A74_RESERVED_0X1A74		GENMASK(31, 0)
#define RFU_0X1A78					0x00001a78
	#define RFU_0X1A78_RESERVED_0X1A78		GENMASK(31, 0)
#define RFU_0X1A7C					0x00001a7c
	#define RFU_0X1A7C_RESERVED_0X1A7C		GENMASK(31, 0)
#define SHU3_R2_CA_CMD0					0x00001aa0
	#define SHU3_R2_CA_CMD0_RK2_TX_ARCA0_DLY	GENMASK(3, 0)
	#define SHU3_R2_CA_CMD0_RK2_TX_ARCA1_DLY	GENMASK(7, 4)
	#define SHU3_R2_CA_CMD0_RK2_TX_ARCA2_DLY	GENMASK(11, 8)
	#define SHU3_R2_CA_CMD0_RK2_TX_ARCA3_DLY	GENMASK(15, 12)
	#define SHU3_R2_CA_CMD0_RK2_TX_ARCA4_DLY	GENMASK(19, 16)
	#define SHU3_R2_CA_CMD0_RK2_TX_ARCA5_DLY	GENMASK(23, 20)
	#define SHU3_R2_CA_CMD0_RK2_TX_ARCLK_DLYB	GENMASK(27, 24)
	#define SHU3_R2_CA_CMD0_RK2_TX_ARCLKB_DLYB	GENMASK(31, 28)
#define SHU3_R2_CA_CMD1					0x00001aa4
	#define SHU3_R2_CA_CMD1_RK2_TX_ARCKE0_DLY	GENMASK(3, 0)
	#define SHU3_R2_CA_CMD1_RK2_TX_ARCKE1_DLY	GENMASK(7, 4)
	#define SHU3_R2_CA_CMD1_RK2_TX_ARCKE2_DLY	GENMASK(11, 8)
	#define SHU3_R2_CA_CMD1_RK2_TX_ARCS0_DLY	GENMASK(15, 12)
	#define SHU3_R2_CA_CMD1_RK2_TX_ARCS1_DLY	GENMASK(19, 16)
	#define SHU3_R2_CA_CMD1_RK2_TX_ARCS2_DLY	GENMASK(23, 20)
	#define SHU3_R2_CA_CMD1_RK2_TX_ARCLK_DLY	GENMASK(27, 24)
	#define SHU3_R2_CA_CMD1_RK2_TX_ARCLKB_DLY	GENMASK(31, 28)
#define SHU3_R2_CA_CMD2					0x00001aa8
	#define SHU3_R2_CA_CMD2_RG_RK2_RX_ARCA0_R_DLY	GENMASK(5, 0)
	#define SHU3_R2_CA_CMD2_RG_RK2_RX_ARCA0_F_DLY	GENMASK(13, 8)
	#define SHU3_R2_CA_CMD2_RG_RK2_RX_ARCA1_R_DLY	GENMASK(21, 16)
	#define SHU3_R2_CA_CMD2_RG_RK2_RX_ARCA1_F_DLY	GENMASK(29, 24)
#define SHU3_R2_CA_CMD3					0x00001aac
	#define SHU3_R2_CA_CMD3_RG_RK2_RX_ARCA2_R_DLY	GENMASK(5, 0)
	#define SHU3_R2_CA_CMD3_RG_RK2_RX_ARCA2_F_DLY	GENMASK(13, 8)
	#define SHU3_R2_CA_CMD3_RG_RK2_RX_ARCA3_R_DLY	GENMASK(21, 16)
	#define SHU3_R2_CA_CMD3_RG_RK2_RX_ARCA3_F_DLY	GENMASK(29, 24)
#define SHU3_R2_CA_CMD4					0x00001ab0
	#define SHU3_R2_CA_CMD4_RG_RK2_RX_ARCA4_R_DLY	GENMASK(5, 0)
	#define SHU3_R2_CA_CMD4_RG_RK2_RX_ARCA4_F_DLY	GENMASK(13, 8)
	#define SHU3_R2_CA_CMD4_RG_RK2_RX_ARCA5_R_DLY	GENMASK(21, 16)
	#define SHU3_R2_CA_CMD4_RG_RK2_RX_ARCA5_F_DLY	GENMASK(29, 24)
#define SHU3_R2_CA_CMD5					0x00001ab4
	#define SHU3_R2_CA_CMD5_RG_RK2_RX_ARCKE0_R_DLY	GENMASK(5, 0)
	#define SHU3_R2_CA_CMD5_RG_RK2_RX_ARCKE0_F_DLY	GENMASK(13, 8)
	#define SHU3_R2_CA_CMD5_RG_RK2_RX_ARCKE1_R_DLY	GENMASK(21, 16)
	#define SHU3_R2_CA_CMD5_RG_RK2_RX_ARCKE1_F_DLY	GENMASK(29, 24)
#define SHU3_R2_CA_CMD6					0x00001ab8
	#define SHU3_R2_CA_CMD6_RG_RK2_RX_ARCKE2_R_DLY	GENMASK(5, 0)
	#define SHU3_R2_CA_CMD6_RG_RK2_RX_ARCKE2_F_DLY	GENMASK(13, 8)
	#define SHU3_R2_CA_CMD6_RG_RK2_RX_ARCS0_R_DLY	GENMASK(21, 16)
	#define SHU3_R2_CA_CMD6_RG_RK2_RX_ARCS0_F_DLY	GENMASK(29, 24)
#define SHU3_R2_CA_CMD7					0x00001abc
	#define SHU3_R2_CA_CMD7_RG_RK2_RX_ARCS1_R_DLY	GENMASK(5, 0)
	#define SHU3_R2_CA_CMD7_RG_RK2_RX_ARCS1_F_DLY	GENMASK(13, 8)
	#define SHU3_R2_CA_CMD7_RG_RK2_RX_ARCS2_R_DLY	GENMASK(21, 16)
	#define SHU3_R2_CA_CMD7_RG_RK2_RX_ARCS2_F_DLY	GENMASK(29, 24)
#define SHU3_R2_CA_CMD8					0x00001ac0
	#define SHU3_R2_CA_CMD8_RG_RK2_RX_ARCLK_R_DLY	GENMASK(22, 16)
	#define SHU3_R2_CA_CMD8_RG_RK2_RX_ARCLK_F_DLY	GENMASK(30, 24)
#define SHU3_R2_CA_CMD9					0x00001ac4
	#define SHU3_R2_CA_CMD9_RG_RK2_ARPI_CS		GENMASK(5, 0)
	#define SHU3_R2_CA_CMD9_RG_RK2_ARPI_CMD		GENMASK(13, 8)
	#define SHU3_R2_CA_CMD9_RG_RK2_ARPI_CLK		GENMASK(29, 24)
#define RFU_0X1AC8					0x00001ac8
	#define RFU_0X1AC8_RESERVED_0X1AC8		GENMASK(31, 0)
#define RFU_0X1ACC					0x00001acc
	#define RFU_0X1ACC_RESERVED_0X1ACC		GENMASK(31, 0)
#define SHU4_B0_DQ0					0x00001b00
	#define SHU4_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0	BIT(4)
	#define SHU4_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0	GENMASK(10, 8)
	#define SHU4_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0	GENMASK(14, 12)
	#define SHU4_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0	BIT(20)
	#define SHU4_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0	GENMASK(26, 24)
	#define SHU4_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0	GENMASK(30, 28)
	#define SHU4_B0_DQ0_R_LP4Y_WDN_MODE_DQS0	BIT(31)
#define SHU4_B0_DQ1					0x00001b04
	#define SHU4_B0_DQ1_RG_TX_ARDQ_DRVP_B0		GENMASK(4, 0)
	#define SHU4_B0_DQ1_RG_TX_ARDQ_DRVN_B0		GENMASK(12, 8)
	#define SHU4_B0_DQ1_RG_TX_ARDQ_ODTP_B0		GENMASK(20, 16)
	#define SHU4_B0_DQ1_RG_TX_ARDQ_ODTN_B0		GENMASK(28, 24)
#define SHU4_B0_DQ2					0x00001b08
	#define SHU4_B0_DQ2_RG_TX_ARDQS0_DRVP_B0	GENMASK(4, 0)
	#define SHU4_B0_DQ2_RG_TX_ARDQS0_DRVN_B0	GENMASK(12, 8)
	#define SHU4_B0_DQ2_RG_TX_ARDQS0_ODTP_B0	GENMASK(20, 16)
	#define SHU4_B0_DQ2_RG_TX_ARDQS0_ODTN_B0	GENMASK(28, 24)
#define SHU4_B0_DQ3					0x00001b0c
	#define SHU4_B0_DQ3_RG_TX_ARDQS0_PU_B0		GENMASK(1, 0)
	#define SHU4_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0	GENMASK(3, 2)
	#define SHU4_B0_DQ3_RG_TX_ARDQS0_PDB_B0		GENMASK(5, 4)
	#define SHU4_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0	GENMASK(7, 6)
	#define SHU4_B0_DQ3_RG_TX_ARDQ_PU_B0		GENMASK(9, 8)
	#define SHU4_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0	GENMASK(11, 10)
	#define SHU4_B0_DQ3_RG_TX_ARDQ_PDB_B0		GENMASK(13, 12)
	#define SHU4_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0	GENMASK(15, 14)
#define SHU4_B0_DQ4					0x00001b10
	#define SHU4_B0_DQ4_RG_ARPI_AA_MCK_DL_B0	GENMASK(5, 0)
	#define SHU4_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0	GENMASK(13, 8)
	#define SHU4_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0	GENMASK(21, 16)
#define SHU4_B0_DQ5					0x00001b14
	#define SHU4_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0	GENMASK(5, 0)
	#define SHU4_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0	BIT(6)
	#define SHU4_B0_DQ5_RG_ARPI_FB_B0		GENMASK(13, 8)
	#define SHU4_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0	GENMASK(18, 16)
	#define SHU4_B0_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B0	BIT(19)
	#define SHU4_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0	GENMASK(22, 20)
	#define SHU4_B0_DQ5_RG_ARPI_MCTL_B0		GENMASK(29, 24)
#define SHU4_B0_DQ6					0x00001b18
	#define SHU4_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0	GENMASK(5, 0)
	#define SHU4_B0_DQ6_RG_ARPI_RESERVE_B0		GENMASK(21, 6)
	#define SHU4_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0	GENMASK(23, 22)
	#define SHU4_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0	GENMASK(25, 24)
	#define SHU4_B0_DQ6_RG_ARPI_MIDPI_EN_B0		BIT(26)
	#define SHU4_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0	BIT(27)
	#define SHU4_B0_DQ6_RG_ARPI_CAP_SEL_B0		GENMASK(29, 28)
	#define SHU4_B0_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B0	BIT(31)
#define SHU4_B0_DQ7					0x00001b1c
	#define SHU4_B0_DQ7_R_DMRANKRXDVS_B0		GENMASK(3, 0)
	#define SHU4_B0_DQ7_MIDPI_ENABLE		BIT(4)
	#define SHU4_B0_DQ7_MIDPI_DIV4_ENABLE		BIT(5)
	#define SHU4_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0	BIT(6)
	#define SHU4_B0_DQ7_R_DMDQMDBI_SHU_B0		BIT(7)
	#define SHU4_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0	GENMASK(11, 8)
	#define SHU4_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0	BIT(12)
	#define SHU4_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0	BIT(13)
	#define SHU4_B0_DQ7_R_DMRXTRACK_DQM_EN_B0	BIT(14)
	#define SHU4_B0_DQ7_R_DMRODTEN_B0		BIT(15)
	#define SHU4_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0	BIT(16)
	#define SHU4_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0	BIT(17)
	#define SHU4_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0	BIT(18)
	#define SHU4_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0	BIT(19)
	#define SHU4_B0_DQ7_R_LP4Y_SDN_MODE_DQS0	BIT(20)
	#define SHU4_B0_DQ7_R_DMRXRANK_DQ_EN_B0		BIT(24)
	#define SHU4_B0_DQ7_R_DMRXRANK_DQ_LAT_B0	GENMASK(27, 25)
	#define SHU4_B0_DQ7_R_DMRXRANK_DQS_EN_B0	BIT(28)
	#define SHU4_B0_DQ7_R_DMRXRANK_DQS_LAT_B0	GENMASK(31, 29)
#define SHU4_B0_DQ8					0x00001b20
	#define SHU4_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0	GENMASK(14, 0)
	#define SHU4_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0	BIT(15)
	#define SHU4_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0	BIT(19)
	#define SHU4_B0_DQ8_R_RMRODTEN_CG_IG_B0		BIT(20)
	#define SHU4_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0	BIT(21)
	#define SHU4_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0	BIT(22)
	#define SHU4_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0	BIT(23)
	#define SHU4_B0_DQ8_R_DMRXDLY_CG_IG_B0		BIT(24)
	#define SHU4_B0_DQ8_R_DMSTBEN_SYNC_CG_IG_B0	BIT(25)
	#define SHU4_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0	BIT(26)
	#define SHU4_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0	BIT(27)
	#define SHU4_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0	BIT(28)
	#define SHU4_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0	BIT(29)
	#define SHU4_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0	BIT(30)
	#define SHU4_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0	BIT(31)
#define SHU4_B0_DQ9					0x00001b24
	#define SHU4_B0_DQ9_RESERVED_0X1B24		GENMASK(31, 0)
#define SHU4_B0_DQ10					0x00001b28
	#define SHU4_B0_DQ10_RESERVED_0X1B28		GENMASK(31, 0)
#define SHU4_B0_DQ11					0x00001b2c
	#define SHU4_B0_DQ11_RESERVED_0X1B2C		GENMASK(31, 0)
#define SHU4_B0_DQ12					0x00001b30
	#define SHU4_B0_DQ12_RESERVED_0X1B30		GENMASK(31, 0)
#define SHU4_B0_DLL0					0x00001b34
	#define SHU4_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU	BIT(0)
	#define SHU4_B0_DLL0_B0_DLL0_RFU		BIT(3)
	#define SHU4_B0_DLL0_RG_ARDLL_FAST_PSJP_B0	BIT(4)
	#define SHU4_B0_DLL0_RG_ARDLL_PHDIV_B0		BIT(9)
	#define SHU4_B0_DLL0_RG_ARDLL_PHJUMP_EN_B0	BIT(10)
	#define SHU4_B0_DLL0_RG_ARDLL_P_GAIN_B0		GENMASK(15, 12)
	#define SHU4_B0_DLL0_RG_ARDLL_IDLECNT_B0	GENMASK(19, 16)
	#define SHU4_B0_DLL0_RG_ARDLL_GAIN_B0		GENMASK(23, 20)
	#define SHU4_B0_DLL0_RG_ARDLL_PHDET_IN_SWAP_B0	BIT(30)
	#define SHU4_B0_DLL0_RG_ARDLL_PHDET_OUT_SEL_B0	BIT(31)
#define SHU4_B0_DLL1					0x00001b38
	#define SHU4_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0	BIT(0)
	#define SHU4_B0_DLL1_RG_ARDLL_PS_EN_B0		BIT(1)
	#define SHU4_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0	BIT(2)
	#define SHU4_B0_DLL1_RG_ARDQ_REV_B0		GENMASK(31, 8)
#define SHU4_B1_DQ0					0x00001b80
	#define SHU4_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1	BIT(4)
	#define SHU4_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1	GENMASK(10, 8)
	#define SHU4_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1	GENMASK(14, 12)
	#define SHU4_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1	BIT(20)
	#define SHU4_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1	GENMASK(26, 24)
	#define SHU4_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1	GENMASK(30, 28)
	#define SHU4_B1_DQ0_R_LP4Y_WDN_MODE_DQS1	BIT(31)
#define SHU4_B1_DQ1					0x00001b84
	#define SHU4_B1_DQ1_RG_TX_ARDQ_DRVP_B1		GENMASK(4, 0)
	#define SHU4_B1_DQ1_RG_TX_ARDQ_DRVN_B1		GENMASK(12, 8)
	#define SHU4_B1_DQ1_RG_TX_ARDQ_ODTP_B1		GENMASK(20, 16)
	#define SHU4_B1_DQ1_RG_TX_ARDQ_ODTN_B1		GENMASK(28, 24)
#define SHU4_B1_DQ2					0x00001b88
	#define SHU4_B1_DQ2_RG_TX_ARDQS0_DRVP_B1	GENMASK(4, 0)
	#define SHU4_B1_DQ2_RG_TX_ARDQS0_DRVN_B1	GENMASK(12, 8)
	#define SHU4_B1_DQ2_RG_TX_ARDQS0_ODTP_B1	GENMASK(20, 16)
	#define SHU4_B1_DQ2_RG_TX_ARDQS0_ODTN_B1	GENMASK(28, 24)
#define SHU4_B1_DQ3					0x00001b8c
	#define SHU4_B1_DQ3_RG_TX_ARDQS0_PU_B1		GENMASK(1, 0)
	#define SHU4_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1	GENMASK(3, 2)
	#define SHU4_B1_DQ3_RG_TX_ARDQS0_PDB_B1		GENMASK(5, 4)
	#define SHU4_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1	GENMASK(7, 6)
	#define SHU4_B1_DQ3_RG_TX_ARDQ_PU_B1		GENMASK(9, 8)
	#define SHU4_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1	GENMASK(11, 10)
	#define SHU4_B1_DQ3_RG_TX_ARDQ_PDB_B1		GENMASK(13, 12)
	#define SHU4_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1	GENMASK(15, 14)
#define SHU4_B1_DQ4					0x00001b90
	#define SHU4_B1_DQ4_RG_ARPI_AA_MCK_DL_B1	GENMASK(5, 0)
	#define SHU4_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1	GENMASK(13, 8)
	#define SHU4_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1	GENMASK(21, 16)
#define SHU4_B1_DQ5					0x00001b94
	#define SHU4_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1	GENMASK(5, 0)
	#define SHU4_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1	BIT(6)
	#define SHU4_B1_DQ5_RG_ARPI_FB_B1		GENMASK(13, 8)
	#define SHU4_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1	GENMASK(18, 16)
	#define SHU4_B1_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B1	BIT(19)
	#define SHU4_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1	GENMASK(22, 20)
	#define SHU4_B1_DQ5_RG_ARPI_MCTL_B1		GENMASK(29, 24)
#define SHU4_B1_DQ6					0x00001b98
	#define SHU4_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1	GENMASK(5, 0)
	#define SHU4_B1_DQ6_RG_ARPI_RESERVE_B1		GENMASK(21, 6)
	#define SHU4_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1	GENMASK(23, 22)
	#define SHU4_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1	GENMASK(25, 24)
	#define SHU4_B1_DQ6_RG_ARPI_MIDPI_EN_B1		BIT(26)
	#define SHU4_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1	BIT(27)
	#define SHU4_B1_DQ6_RG_ARPI_CAP_SEL_B1		GENMASK(29, 28)
	#define SHU4_B1_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B1	BIT(31)
#define SHU4_B1_DQ7					0x00001b9c
	#define SHU4_B1_DQ7_R_DMRANKRXDVS_B1		GENMASK(3, 0)
	#define SHU4_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1	BIT(6)
	#define SHU4_B1_DQ7_R_DMDQMDBI_SHU_B1		BIT(7)
	#define SHU4_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1	GENMASK(11, 8)
	#define SHU4_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1	BIT(12)
	#define SHU4_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1	BIT(13)
	#define SHU4_B1_DQ7_R_DMRXTRACK_DQM_EN_B1	BIT(14)
	#define SHU4_B1_DQ7_R_DMRODTEN_B1		BIT(15)
	#define SHU4_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1	BIT(16)
	#define SHU4_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1	BIT(17)
	#define SHU4_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1	BIT(18)
	#define SHU4_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1	BIT(19)
	#define SHU4_B1_DQ7_R_LP4Y_SDN_MODE_DQS1	BIT(20)
	#define SHU4_B1_DQ7_R_DMRXRANK_DQ_EN_B1		BIT(24)
	#define SHU4_B1_DQ7_R_DMRXRANK_DQ_LAT_B1	GENMASK(27, 25)
	#define SHU4_B1_DQ7_R_DMRXRANK_DQS_EN_B1	BIT(28)
	#define SHU4_B1_DQ7_R_DMRXRANK_DQS_LAT_B1	GENMASK(31, 29)
#define SHU4_B1_DQ8					0x00001ba0
	#define SHU4_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1	GENMASK(14, 0)
	#define SHU4_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1	BIT(15)
	#define SHU4_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1	BIT(19)
	#define SHU4_B1_DQ8_R_RMRODTEN_CG_IG_B1		BIT(20)
	#define SHU4_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1	BIT(21)
	#define SHU4_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1	BIT(22)
	#define SHU4_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1	BIT(23)
	#define SHU4_B1_DQ8_R_DMRXDLY_CG_IG_B1		BIT(24)
	#define SHU4_B1_DQ8_R_DMSTBEN_SYNC_CG_IG_B1	BIT(25)
	#define SHU4_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1	BIT(26)
	#define SHU4_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1	BIT(27)
	#define SHU4_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1	BIT(28)
	#define SHU4_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1	BIT(29)
	#define SHU4_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1	BIT(30)
	#define SHU4_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1	BIT(31)
#define SHU4_B1_DQ9					0x00001ba4
	#define SHU4_B1_DQ9_RESERVED_0X1BA4		GENMASK(31, 0)
#define SHU4_B1_DQ10					0x00001ba8
	#define SHU4_B1_DQ10_RESERVED_0X1BA8		GENMASK(31, 0)
#define SHU4_B1_DQ11					0x00001bac
	#define SHU4_B1_DQ11_RESERVED_0X1BAC		GENMASK(31, 0)
#define SHU4_B1_DQ12					0x00001bb0
	#define SHU4_B1_DQ12_RESERVED_0X1BB0		GENMASK(31, 0)
#define SHU4_B1_DLL0					0x00001bb4
	#define SHU4_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU	BIT(0)
	#define SHU4_B1_DLL0_B1_DLL0_RFU		BIT(3)
	#define SHU4_B1_DLL0_RG_ARDLL_FAST_PSJP_B1	BIT(4)
	#define SHU4_B1_DLL0_RG_ARDLL_PHDIV_B1		BIT(9)
	#define SHU4_B1_DLL0_RG_ARDLL_PHJUMP_EN_B1	BIT(10)
	#define SHU4_B1_DLL0_RG_ARDLL_P_GAIN_B1		GENMASK(15, 12)
	#define SHU4_B1_DLL0_RG_ARDLL_IDLECNT_B1	GENMASK(19, 16)
	#define SHU4_B1_DLL0_RG_ARDLL_GAIN_B1		GENMASK(23, 20)
	#define SHU4_B1_DLL0_RG_ARDLL_PHDET_IN_SWAP_B1	BIT(30)
	#define SHU4_B1_DLL0_RG_ARDLL_PHDET_OUT_SEL_B1	BIT(31)
#define SHU4_B1_DLL1					0x00001bb8
	#define SHU4_B1_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B1	BIT(0)
	#define SHU4_B1_DLL1_RG_ARDLL_PS_EN_B1		BIT(1)
	#define SHU4_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1	BIT(2)
	#define SHU4_B1_DLL1_RG_ARDQ_REV_B1		GENMASK(31, 8)
#define SHU4_CA_CMD0					0x00001c00
	#define SHU4_CA_CMD0_RG_TX_ARCLK_PRE_EN		BIT(4)
	#define SHU4_CA_CMD0_RG_TX_ARCLK_DRVP_PRE	GENMASK(10, 8)
	#define SHU4_CA_CMD0_RG_TX_ARCLK_DRVN_PRE	GENMASK(14, 12)
	#define SHU4_CA_CMD0_RG_CGEN_FMEM_CK_CG_DLL	BIT(17)
	#define SHU4_CA_CMD0_RG_FB_CK_MUX		GENMASK(19, 18)
	#define SHU4_CA_CMD0_RG_TX_ARCMD_PRE_EN		BIT(20)
	#define SHU4_CA_CMD0_RG_TX_ARCMD_DRVP_PRE	GENMASK(26, 24)
	#define SHU4_CA_CMD0_RG_TX_ARCMD_DRVN_PRE	GENMASK(30, 28)
	#define SHU4_CA_CMD0_R_LP4Y_WDN_MODE_CLK	BIT(31)
#define SHU4_CA_CMD1					0x00001c04
	#define SHU4_CA_CMD1_RG_TX_ARCMD_DRVP		GENMASK(4, 0)
	#define SHU4_CA_CMD1_RG_TX_ARCMD_DRVN		GENMASK(12, 8)
	#define SHU4_CA_CMD1_RG_TX_ARCMD_ODTP		GENMASK(20, 16)
	#define SHU4_CA_CMD1_RG_TX_ARCMD_ODTN		GENMASK(28, 24)
#define SHU4_CA_CMD2					0x00001c08
	#define SHU4_CA_CMD2_RG_TX_ARCLK_DRVP		GENMASK(4, 0)
	#define SHU4_CA_CMD2_RG_TX_ARCLK_DRVN		GENMASK(12, 8)
	#define SHU4_CA_CMD2_RG_TX_ARCLK_ODTP		GENMASK(20, 16)
	#define SHU4_CA_CMD2_RG_TX_ARCLK_ODTN		GENMASK(28, 24)
#define SHU4_CA_CMD3					0x00001c0c
	#define SHU4_CA_CMD3_RG_TX_ARCLK_PU		GENMASK(1, 0)
	#define SHU4_CA_CMD3_RG_TX_ARCLK_PU_PRE		GENMASK(3, 2)
	#define SHU4_CA_CMD3_RG_TX_ARCLK_PDB		GENMASK(5, 4)
	#define SHU4_CA_CMD3_RG_TX_ARCLK_PDB_PRE	GENMASK(7, 6)
	#define SHU4_CA_CMD3_RG_TX_ARCMD_PU		GENMASK(9, 8)
	#define SHU4_CA_CMD3_RG_TX_ARCMD_PU_PRE		GENMASK(11, 10)
	#define SHU4_CA_CMD3_RG_TX_ARCMD_PDB		GENMASK(13, 12)
	#define SHU4_CA_CMD3_RG_TX_ARCMD_PDB_PRE	GENMASK(15, 14)
#define SHU4_CA_CMD4					0x00001c10
	#define SHU4_CA_CMD4_RG_ARPI_AA_MCK_DL_CA	GENMASK(5, 0)
	#define SHU4_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA	GENMASK(13, 8)
	#define SHU4_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA	GENMASK(21, 16)
#define SHU4_CA_CMD5					0x00001c14
	#define SHU4_CA_CMD5_RG_RX_ARCMD_VREF_SEL	GENMASK(5, 0)
	#define SHU4_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS	BIT(6)
	#define SHU4_CA_CMD5_RG_ARPI_FB_CA		GENMASK(13, 8)
	#define SHU4_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY	GENMASK(18, 16)
	#define SHU4_CA_CMD5_DA_RX_ARCLK_DQSIEN_RB_DLY	BIT(19)
	#define SHU4_CA_CMD5_RG_RX_ARCLK_DVS_DLY	GENMASK(22, 20)
	#define SHU4_CA_CMD5_RG_ARPI_MCTL_CA		GENMASK(29, 24)
#define SHU4_CA_CMD6					0x00001c18
	#define SHU4_CA_CMD6_RG_ARPI_OFFSET_CLKIEN	GENMASK(5, 0)
	#define SHU4_CA_CMD6_RG_ARPI_RESERVE_CA		GENMASK(21, 6)
	#define SHU4_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA	GENMASK(23, 22)
	#define SHU4_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA	GENMASK(25, 24)
	#define SHU4_CA_CMD6_RG_ARPI_MIDPI_EN_CA	BIT(26)
	#define SHU4_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA	BIT(27)
	#define SHU4_CA_CMD6_RG_ARPI_CAP_SEL_CA		GENMASK(29, 28)
	#define SHU4_CA_CMD6_RG_ARPI_MIDPI_BYPASS_EN_CA	BIT(31)
#define SHU4_CA_CMD7					0x00001c1c
	#define SHU4_CA_CMD7_R_DMRANKRXDVS_CA		GENMASK(3, 0)
	#define SHU4_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA	BIT(12)
	#define SHU4_CA_CMD7_R_DMRODTEN_CA		BIT(15)
	#define SHU4_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA	BIT(16)
	#define SHU4_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW	BIT(17)
	#define SHU4_CA_CMD7_R_DMTX_ARPI_CG_CLK_NEW	BIT(18)
	#define SHU4_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW	BIT(19)
	#define SHU4_CA_CMD7_R_LP4Y_SDN_MODE_CLK	BIT(20)
	#define SHU4_CA_CMD7_R_DMRXRANK_CMD_EN		BIT(24)
	#define SHU4_CA_CMD7_R_DMRXRANK_CMD_LAT		GENMASK(27, 25)
	#define SHU4_CA_CMD7_R_DMRXRANK_CLK_EN		BIT(28)
	#define SHU4_CA_CMD7_R_DMRXRANK_CLK_LAT		GENMASK(31, 29)
#define SHU4_CA_CMD8					0x00001c20
	#define SHU4_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA	GENMASK(14, 0)
	#define SHU4_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA	BIT(15)
	#define SHU4_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA	BIT(19)
	#define SHU4_CA_CMD8_R_RMRODTEN_CG_IG_CA	BIT(20)
	#define SHU4_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA	BIT(21)
	#define SHU4_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA	BIT(22)
	#define SHU4_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA	BIT(23)
	#define SHU4_CA_CMD8_R_DMRXDLY_CG_IG_CA		BIT(24)
	#define SHU4_CA_CMD8_R_DMSTBEN_SYNC_CG_IG_CA	BIT(25)
	#define SHU4_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA	BIT(26)
	#define SHU4_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA	BIT(27)
	#define SHU4_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA	BIT(28)
	#define SHU4_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA	BIT(29)
	#define SHU4_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA	BIT(30)
	#define SHU4_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA	BIT(31)
#define SHU4_CA_CMD9					0x00001c24
	#define SHU4_CA_CMD9_RESERVED_0X1C24		GENMASK(31, 0)
#define SHU4_CA_CMD10					0x00001c28
	#define SHU4_CA_CMD10_RESERVED_0X1C28		GENMASK(31, 0)
#define SHU4_CA_CMD11					0x00001c2c
	#define SHU4_CA_CMD11_RG_RIMP_REV		GENMASK(7, 0)
	#define SHU4_CA_CMD11_RG_RIMP_VREF_SEL		GENMASK(13, 8)
	#define SHU4_CA_CMD11_RG_TX_ARCKE_DRVP		GENMASK(21, 17)
	#define SHU4_CA_CMD11_RG_TX_ARCKE_DRVN		GENMASK(26, 22)
#define SHU4_CA_CMD12					0x00001c30
	#define SHU4_CA_CMD12_RESERVED_0X1C30		GENMASK(31, 0)
#define SHU4_CA_DLL0					0x00001c34
	#define SHU4_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU	BIT(0)
	#define SHU4_CA_DLL0_CA_DLL0_RFU		BIT(3)
	#define SHU4_CA_DLL0_RG_ARDLL_FAST_PSJP_CA	BIT(4)
	#define SHU4_CA_DLL0_RG_ARDLL_PHDIV_CA		BIT(9)
	#define SHU4_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA	BIT(10)
	#define SHU4_CA_DLL0_RG_ARDLL_P_GAIN_CA		GENMASK(15, 12)
	#define SHU4_CA_DLL0_RG_ARDLL_IDLECNT_CA	GENMASK(19, 16)
	#define SHU4_CA_DLL0_RG_ARDLL_GAIN_CA		GENMASK(23, 20)
	#define SHU4_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA	BIT(30)
	#define SHU4_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA	BIT(31)
#define SHU4_CA_DLL1					0x00001c38
	#define SHU4_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA	BIT(0)
	#define SHU4_CA_DLL1_RG_ARDLL_PS_EN_CA		BIT(1)
	#define SHU4_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA	BIT(2)
	#define SHU4_CA_DLL1_RG_ARCMD_REV		GENMASK(31, 8)
#define SHU4_MISC0					0x00001cf0
	#define SHU4_MISC0_R_RX_PIPE_BYPASS_EN		BIT(1)
	#define SHU4_MISC0_RG_CMD_TXPIPE_BYPASS_EN	BIT(2)
	#define SHU4_MISC0_RG_CK_TXPIPE_BYPASS_EN	BIT(3)
	#define SHU4_MISC0_RG_RVREF_SEL_DQ		GENMASK(21, 16)
	#define SHU4_MISC0_RG_RVREF_DDR4_SEL		BIT(22)
	#define SHU4_MISC0_RG_RVREF_DDR3_SEL		BIT(23)
	#define SHU4_MISC0_RG_RVREF_SEL_CMD		GENMASK(29, 24)
#define SHU4_R0_B0_DQ0					0x00001d00
	#define SHU4_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0	GENMASK(3, 0)
	#define SHU4_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0	GENMASK(7, 4)
	#define SHU4_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0	GENMASK(11, 8)
	#define SHU4_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0	GENMASK(15, 12)
	#define SHU4_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0	GENMASK(19, 16)
	#define SHU4_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0	GENMASK(23, 20)
	#define SHU4_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0	GENMASK(27, 24)
	#define SHU4_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0	GENMASK(31, 28)
#define SHU4_R0_B0_DQ1					0x00001d04
	#define SHU4_R0_B0_DQ1_RK0_TX_ARDQM0_DLY_B0	GENMASK(3, 0)
	#define SHU4_R0_B0_DQ1_RK0_TX_ARDQS0_DLYB_B0	GENMASK(19, 16)
	#define SHU4_R0_B0_DQ1_RK0_TX_ARDQS0B_DLYB_B0	GENMASK(23, 20)
	#define SHU4_R0_B0_DQ1_RK0_TX_ARDQS0_DLY_B0	GENMASK(27, 24)
	#define SHU4_R0_B0_DQ1_RK0_TX_ARDQS0B_DLY_B0	GENMASK(31, 28)
#define SHU4_R0_B0_DQ2					0x00001d08
	#define SHU4_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R0_B0_DQ2_RK0_RX_ARDQ0_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0	GENMASK(21, 16)
	#define SHU4_R0_B0_DQ2_RK0_RX_ARDQ1_F_DLY_B0	GENMASK(29, 24)
#define SHU4_R0_B0_DQ3					0x00001d0c
	#define SHU4_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R0_B0_DQ3_RK0_RX_ARDQ2_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0	GENMASK(21, 16)
	#define SHU4_R0_B0_DQ3_RK0_RX_ARDQ3_F_DLY_B0	GENMASK(29, 24)
#define SHU4_R0_B0_DQ4					0x00001d10
	#define SHU4_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R0_B0_DQ4_RK0_RX_ARDQ4_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0	GENMASK(21, 16)
	#define SHU4_R0_B0_DQ4_RK0_RX_ARDQ5_F_DLY_B0	GENMASK(29, 24)
#define SHU4_R0_B0_DQ5					0x00001d14
	#define SHU4_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R0_B0_DQ5_RK0_RX_ARDQ6_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0	GENMASK(21, 16)
	#define SHU4_R0_B0_DQ5_RK0_RX_ARDQ7_F_DLY_B0	GENMASK(29, 24)
#define SHU4_R0_B0_DQ6					0x00001d18
	#define SHU4_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0	GENMASK(22, 16)
	#define SHU4_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0	GENMASK(30, 24)
#define SHU4_R0_B0_DQ7					0x00001d1c
	#define SHU4_R0_B0_DQ7_RK0_ARPI_DQ_B0		GENMASK(13, 8)
	#define SHU4_R0_B0_DQ7_RK0_ARPI_DQM_B0		GENMASK(21, 16)
	#define SHU4_R0_B0_DQ7_RK0_ARPI_PBYTE_B0	GENMASK(29, 24)
#define RFU_0X1D20					0x00001d20
	#define RFU_0X1D20_RESERVED_0X1D20		GENMASK(31, 0)
#define RFU_0X1D24					0x00001d24
	#define RFU_0X1D24_RESERVED_0X1D24		GENMASK(31, 0)
#define RFU_0X1D28					0x00001d28
	#define RFU_0X1D28_RESERVED_0X1D28		GENMASK(31, 0)
#define RFU_0X1D2C					0x00001d2c
	#define RFU_0X1D2C_RESERVED_0X1D2C		GENMASK(31, 0)
#define SHU4_R0_B1_DQ0					0x00001d50
	#define SHU4_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1	GENMASK(3, 0)
	#define SHU4_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1	GENMASK(7, 4)
	#define SHU4_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1	GENMASK(11, 8)
	#define SHU4_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1	GENMASK(15, 12)
	#define SHU4_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1	GENMASK(19, 16)
	#define SHU4_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1	GENMASK(23, 20)
	#define SHU4_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1	GENMASK(27, 24)
	#define SHU4_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1	GENMASK(31, 28)
#define SHU4_R0_B1_DQ1					0x00001d54
	#define SHU4_R0_B1_DQ1_RK0_TX_ARDQM0_DLY_B1	GENMASK(3, 0)
	#define SHU4_R0_B1_DQ1_RK0_TX_ARDQS0_DLYB_B1	GENMASK(19, 16)
	#define SHU4_R0_B1_DQ1_RK0_TX_ARDQS0B_DLYB_B1	GENMASK(23, 20)
	#define SHU4_R0_B1_DQ1_RK0_TX_ARDQS0_DLY_B1	GENMASK(27, 24)
	#define SHU4_R0_B1_DQ1_RK0_TX_ARDQS0B_DLY_B1	GENMASK(31, 28)
#define SHU4_R0_B1_DQ2					0x00001d58
	#define SHU4_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R0_B1_DQ2_RK0_RX_ARDQ0_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1	GENMASK(21, 16)
	#define SHU4_R0_B1_DQ2_RK0_RX_ARDQ1_F_DLY_B1	GENMASK(29, 24)
#define SHU4_R0_B1_DQ3					0x00001d5c
	#define SHU4_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R0_B1_DQ3_RK0_RX_ARDQ2_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1	GENMASK(21, 16)
	#define SHU4_R0_B1_DQ3_RK0_RX_ARDQ3_F_DLY_B1	GENMASK(29, 24)
#define SHU4_R0_B1_DQ4					0x00001d60
	#define SHU4_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R0_B1_DQ4_RK0_RX_ARDQ4_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1	GENMASK(21, 16)
	#define SHU4_R0_B1_DQ4_RK0_RX_ARDQ5_F_DLY_B1	GENMASK(29, 24)
#define SHU4_R0_B1_DQ5					0x00001d64
	#define SHU4_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R0_B1_DQ5_RK0_RX_ARDQ6_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1	GENMASK(21, 16)
	#define SHU4_R0_B1_DQ5_RK0_RX_ARDQ7_F_DLY_B1	GENMASK(29, 24)
#define SHU4_R0_B1_DQ6					0x00001d68
	#define SHU4_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R0_B1_DQ6_RK0_RX_ARDQM0_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1	GENMASK(22, 16)
	#define SHU4_R0_B1_DQ6_RK0_RX_ARDQS0_F_DLY_B1	GENMASK(30, 24)
#define SHU4_R0_B1_DQ7					0x00001d6c
	#define SHU4_R0_B1_DQ7_RK0_ARPI_DQ_B1		GENMASK(13, 8)
	#define SHU4_R0_B1_DQ7_RK0_ARPI_DQM_B1		GENMASK(21, 16)
	#define SHU4_R0_B1_DQ7_RK0_ARPI_PBYTE_B1	GENMASK(29, 24)
#define RFU_0X1D70					0x00001d70
	#define RFU_0X1D70_RESERVED_0X1D70		GENMASK(31, 0)
#define RFU_0X1D74					0x00001d74
	#define RFU_0X1D74_RESERVED_0X1D74		GENMASK(31, 0)
#define RFU_0X1D78					0x00001d78
	#define RFU_0X1D78_RESERVED_0X1D78		GENMASK(31, 0)
#define RFU_0X1D7C					0x00001d7c
	#define RFU_0X1D7C_RESERVED_0X1D7C		GENMASK(31, 0)
#define SHU4_R0_CA_CMD0					0x00001da0
	#define SHU4_R0_CA_CMD0_RK0_TX_ARCA0_DLY	GENMASK(3, 0)
	#define SHU4_R0_CA_CMD0_RK0_TX_ARCA1_DLY	GENMASK(7, 4)
	#define SHU4_R0_CA_CMD0_RK0_TX_ARCA2_DLY	GENMASK(11, 8)
	#define SHU4_R0_CA_CMD0_RK0_TX_ARCA3_DLY	GENMASK(15, 12)
	#define SHU4_R0_CA_CMD0_RK0_TX_ARCA4_DLY	GENMASK(19, 16)
	#define SHU4_R0_CA_CMD0_RK0_TX_ARCA5_DLY	GENMASK(23, 20)
	#define SHU4_R0_CA_CMD0_RK0_TX_ARCLK_DLYB	GENMASK(27, 24)
	#define SHU4_R0_CA_CMD0_RK0_TX_ARCLKB_DLYB	GENMASK(31, 28)
#define SHU4_R0_CA_CMD1					0x00001da4
	#define SHU4_R0_CA_CMD1_RK0_TX_ARCKE0_DLY	GENMASK(3, 0)
	#define SHU4_R0_CA_CMD1_RK0_TX_ARCKE1_DLY	GENMASK(7, 4)
	#define SHU4_R0_CA_CMD1_RK0_TX_ARCKE2_DLY	GENMASK(11, 8)
	#define SHU4_R0_CA_CMD1_RK0_TX_ARCS0_DLY	GENMASK(15, 12)
	#define SHU4_R0_CA_CMD1_RK0_TX_ARCS1_DLY	GENMASK(19, 16)
	#define SHU4_R0_CA_CMD1_RK0_TX_ARCS2_DLY	GENMASK(23, 20)
	#define SHU4_R0_CA_CMD1_RK0_TX_ARCLK_DLY	GENMASK(27, 24)
	#define SHU4_R0_CA_CMD1_RK0_TX_ARCLKB_DLY	GENMASK(31, 28)
#define SHU4_R0_CA_CMD2					0x00001da8
	#define SHU4_R0_CA_CMD2_RG_RK0_RX_ARCA0_R_DLY	GENMASK(5, 0)
	#define SHU4_R0_CA_CMD2_RG_RK0_RX_ARCA0_F_DLY	GENMASK(13, 8)
	#define SHU4_R0_CA_CMD2_RG_RK0_RX_ARCA1_R_DLY	GENMASK(21, 16)
	#define SHU4_R0_CA_CMD2_RG_RK0_RX_ARCA1_F_DLY	GENMASK(29, 24)
#define SHU4_R0_CA_CMD3					0x00001dac
	#define SHU4_R0_CA_CMD3_RG_RK0_RX_ARCA2_R_DLY	GENMASK(5, 0)
	#define SHU4_R0_CA_CMD3_RG_RK0_RX_ARCA2_F_DLY	GENMASK(13, 8)
	#define SHU4_R0_CA_CMD3_RG_RK0_RX_ARCA3_R_DLY	GENMASK(21, 16)
	#define SHU4_R0_CA_CMD3_RG_RK0_RX_ARCA3_F_DLY	GENMASK(29, 24)
#define SHU4_R0_CA_CMD4					0x00001db0
	#define SHU4_R0_CA_CMD4_RG_RK0_RX_ARCA4_R_DLY	GENMASK(5, 0)
	#define SHU4_R0_CA_CMD4_RG_RK0_RX_ARCA4_F_DLY	GENMASK(13, 8)
	#define SHU4_R0_CA_CMD4_RG_RK0_RX_ARCA5_R_DLY	GENMASK(21, 16)
	#define SHU4_R0_CA_CMD4_RG_RK0_RX_ARCA5_F_DLY	GENMASK(29, 24)
#define SHU4_R0_CA_CMD5					0x00001db4
	#define SHU4_R0_CA_CMD5_RG_RK0_RX_ARCKE0_R_DLY	GENMASK(5, 0)
	#define SHU4_R0_CA_CMD5_RG_RK0_RX_ARCKE0_F_DLY	GENMASK(13, 8)
	#define SHU4_R0_CA_CMD5_RG_RK0_RX_ARCKE1_R_DLY	GENMASK(21, 16)
	#define SHU4_R0_CA_CMD5_RG_RK0_RX_ARCKE1_F_DLY	GENMASK(29, 24)
#define SHU4_R0_CA_CMD6					0x00001db8
	#define SHU4_R0_CA_CMD6_RG_RK0_RX_ARCKE2_R_DLY	GENMASK(5, 0)
	#define SHU4_R0_CA_CMD6_RG_RK0_RX_ARCKE2_F_DLY	GENMASK(13, 8)
	#define SHU4_R0_CA_CMD6_RG_RK0_RX_ARCS0_R_DLY	GENMASK(21, 16)
	#define SHU4_R0_CA_CMD6_RG_RK0_RX_ARCS0_F_DLY	GENMASK(29, 24)
#define SHU4_R0_CA_CMD7					0x00001dbc
	#define SHU4_R0_CA_CMD7_RG_RK0_RX_ARCS1_R_DLY	GENMASK(5, 0)
	#define SHU4_R0_CA_CMD7_RG_RK0_RX_ARCS1_F_DLY	GENMASK(13, 8)
	#define SHU4_R0_CA_CMD7_RG_RK0_RX_ARCS2_R_DLY	GENMASK(21, 16)
	#define SHU4_R0_CA_CMD7_RG_RK0_RX_ARCS2_F_DLY	GENMASK(29, 24)
#define SHU4_R0_CA_CMD8					0x00001dc0
	#define SHU4_R0_CA_CMD8_RG_RK0_RX_ARCLK_R_DLY	GENMASK(22, 16)
	#define SHU4_R0_CA_CMD8_RG_RK0_RX_ARCLK_F_DLY	GENMASK(30, 24)
#define SHU4_R0_CA_CMD9					0x00001dc4
	#define SHU4_R0_CA_CMD9_RG_RK0_ARPI_CS		GENMASK(5, 0)
	#define SHU4_R0_CA_CMD9_RG_RK0_ARPI_CMD		GENMASK(13, 8)
	#define SHU4_R0_CA_CMD9_RG_RK0_ARPI_CLK		GENMASK(29, 24)
#define RFU_0X1DC8					0x00001dc8
	#define RFU_0X1DC8_RESERVED_0X1DC8		GENMASK(31, 0)
#define RFU_0X1DCC					0x00001dcc
	#define RFU_0X1DCC_RESERVED_0X1DCC		GENMASK(31, 0)
#define SHU4_R1_B0_DQ0					0x00001e00
	#define SHU4_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0	GENMASK(3, 0)
	#define SHU4_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0	GENMASK(7, 4)
	#define SHU4_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0	GENMASK(11, 8)
	#define SHU4_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0	GENMASK(15, 12)
	#define SHU4_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0	GENMASK(19, 16)
	#define SHU4_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0	GENMASK(23, 20)
	#define SHU4_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0	GENMASK(27, 24)
	#define SHU4_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0	GENMASK(31, 28)
#define SHU4_R1_B0_DQ1					0x00001e04
	#define SHU4_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0	GENMASK(3, 0)
	#define SHU4_R1_B0_DQ1_RK1_TX_ARDQS0_DLYB_B0	GENMASK(19, 16)
	#define SHU4_R1_B0_DQ1_RK1_TX_ARDQS0B_DLYB_B0	GENMASK(23, 20)
	#define SHU4_R1_B0_DQ1_RK1_TX_ARDQS0_DLY_B0	GENMASK(27, 24)
	#define SHU4_R1_B0_DQ1_RK1_TX_ARDQS0B_DLY_B0	GENMASK(31, 28)
#define SHU4_R1_B0_DQ2					0x00001e08
	#define SHU4_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R1_B0_DQ2_RK1_RX_ARDQ0_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0	GENMASK(21, 16)
	#define SHU4_R1_B0_DQ2_RK1_RX_ARDQ1_F_DLY_B0	GENMASK(29, 24)
#define SHU4_R1_B0_DQ3					0x00001e0c
	#define SHU4_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R1_B0_DQ3_RK1_RX_ARDQ2_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0	GENMASK(21, 16)
	#define SHU4_R1_B0_DQ3_RK1_RX_ARDQ3_F_DLY_B0	GENMASK(29, 24)
#define SHU4_R1_B0_DQ4					0x00001e10
	#define SHU4_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R1_B0_DQ4_RK1_RX_ARDQ4_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0	GENMASK(21, 16)
	#define SHU4_R1_B0_DQ4_RK1_RX_ARDQ5_F_DLY_B0	GENMASK(29, 24)
#define SHU4_R1_B0_DQ5					0x00001e14
	#define SHU4_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R1_B0_DQ5_RK1_RX_ARDQ6_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0	GENMASK(21, 16)
	#define SHU4_R1_B0_DQ5_RK1_RX_ARDQ7_F_DLY_B0	GENMASK(29, 24)
#define SHU4_R1_B0_DQ6					0x00001e18
	#define SHU4_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R1_B0_DQ6_RK1_RX_ARDQM0_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0	GENMASK(22, 16)
	#define SHU4_R1_B0_DQ6_RK1_RX_ARDQS0_F_DLY_B0	GENMASK(30, 24)
#define SHU4_R1_B0_DQ7					0x00001e1c
	#define SHU4_R1_B0_DQ7_RK1_ARPI_DQ_B0		GENMASK(13, 8)
	#define SHU4_R1_B0_DQ7_RK1_ARPI_DQM_B0		GENMASK(21, 16)
	#define SHU4_R1_B0_DQ7_RK1_ARPI_PBYTE_B0	GENMASK(29, 24)
#define RFU_0X1E20					0x00001e20
	#define RFU_0X1E20_RESERVED_0X1E20		GENMASK(31, 0)
#define RFU_0X1E24					0x00001e24
	#define RFU_0X1E24_RESERVED_0X1E24		GENMASK(31, 0)
#define RFU_0X1E28					0x00001e28
	#define RFU_0X1E28_RESERVED_0X1E28		GENMASK(31, 0)
#define RFU_0X1E2C					0x00001e2c
	#define RFU_0X1E2C_RESERVED_0X1E2C		GENMASK(31, 0)
#define SHU4_R1_B1_DQ0					0x00001e50
	#define SHU4_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1	GENMASK(3, 0)
	#define SHU4_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1	GENMASK(7, 4)
	#define SHU4_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1	GENMASK(11, 8)
	#define SHU4_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1	GENMASK(15, 12)
	#define SHU4_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1	GENMASK(19, 16)
	#define SHU4_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1	GENMASK(23, 20)
	#define SHU4_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1	GENMASK(27, 24)
	#define SHU4_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1	GENMASK(31, 28)
#define SHU4_R1_B1_DQ1					0x00001e54
	#define SHU4_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1	GENMASK(3, 0)
	#define SHU4_R1_B1_DQ1_RK1_TX_ARDQS0_DLYB_B1	GENMASK(19, 16)
	#define SHU4_R1_B1_DQ1_RK1_TX_ARDQS0B_DLYB_B1	GENMASK(23, 20)
	#define SHU4_R1_B1_DQ1_RK1_TX_ARDQS0_DLY_B1	GENMASK(27, 24)
	#define SHU4_R1_B1_DQ1_RK1_TX_ARDQS0B_DLY_B1	GENMASK(31, 28)
#define SHU4_R1_B1_DQ2					0x00001e58
	#define SHU4_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R1_B1_DQ2_RK1_RX_ARDQ0_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1	GENMASK(21, 16)
	#define SHU4_R1_B1_DQ2_RK1_RX_ARDQ1_F_DLY_B1	GENMASK(29, 24)
#define SHU4_R1_B1_DQ3					0x00001e5c
	#define SHU4_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R1_B1_DQ3_RK1_RX_ARDQ2_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1	GENMASK(21, 16)
	#define SHU4_R1_B1_DQ3_RK1_RX_ARDQ3_F_DLY_B1	GENMASK(29, 24)
#define SHU4_R1_B1_DQ4					0x00001e60
	#define SHU4_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R1_B1_DQ4_RK1_RX_ARDQ4_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1	GENMASK(21, 16)
	#define SHU4_R1_B1_DQ4_RK1_RX_ARDQ5_F_DLY_B1	GENMASK(29, 24)
#define SHU4_R1_B1_DQ5					0x00001e64
	#define SHU4_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R1_B1_DQ5_RK1_RX_ARDQ6_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1	GENMASK(21, 16)
	#define SHU4_R1_B1_DQ5_RK1_RX_ARDQ7_F_DLY_B1	GENMASK(29, 24)
#define SHU4_R1_B1_DQ6					0x00001e68
	#define SHU4_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R1_B1_DQ6_RK1_RX_ARDQM0_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1	GENMASK(22, 16)
	#define SHU4_R1_B1_DQ6_RK1_RX_ARDQS0_F_DLY_B1	GENMASK(30, 24)
#define SHU4_R1_B1_DQ7					0x00001e6c
	#define SHU4_R1_B1_DQ7_RK1_ARPI_DQ_B1		GENMASK(13, 8)
	#define SHU4_R1_B1_DQ7_RK1_ARPI_DQM_B1		GENMASK(21, 16)
	#define SHU4_R1_B1_DQ7_RK1_ARPI_PBYTE_B1	GENMASK(29, 24)
#define RFU_0X1E70					0x00001e70
	#define RFU_0X1E70_RESERVED_0X1E70		GENMASK(31, 0)
#define RFU_0X1E74					0x00001e74
	#define RFU_0X1E74_RESERVED_0X1E74		GENMASK(31, 0)
#define RFU_0X1E78					0x00001e78
	#define RFU_0X1E78_RESERVED_0X1E78		GENMASK(31, 0)
#define RFU_0X1E7C					0x00001e7c
	#define RFU_0X1E7C_RESERVED_0X1E7C		GENMASK(31, 0)
#define SHU4_R1_CA_CMD0					0x00001ea0
	#define SHU4_R1_CA_CMD0_RK1_TX_ARCA0_DLY	GENMASK(3, 0)
	#define SHU4_R1_CA_CMD0_RK1_TX_ARCA1_DLY	GENMASK(7, 4)
	#define SHU4_R1_CA_CMD0_RK1_TX_ARCA2_DLY	GENMASK(11, 8)
	#define SHU4_R1_CA_CMD0_RK1_TX_ARCA3_DLY	GENMASK(15, 12)
	#define SHU4_R1_CA_CMD0_RK1_TX_ARCA4_DLY	GENMASK(19, 16)
	#define SHU4_R1_CA_CMD0_RK1_TX_ARCA5_DLY	GENMASK(23, 20)
	#define SHU4_R1_CA_CMD0_RK1_TX_ARCLK_DLYB	GENMASK(27, 24)
	#define SHU4_R1_CA_CMD0_RK1_TX_ARCLKB_DLYB	GENMASK(31, 28)
#define SHU4_R1_CA_CMD1					0x00001ea4
	#define SHU4_R1_CA_CMD1_RK1_TX_ARCKE0_DLY	GENMASK(3, 0)
	#define SHU4_R1_CA_CMD1_RK1_TX_ARCKE1_DLY	GENMASK(7, 4)
	#define SHU4_R1_CA_CMD1_RK1_TX_ARCKE2_DLY	GENMASK(11, 8)
	#define SHU4_R1_CA_CMD1_RK1_TX_ARCS0_DLY	GENMASK(15, 12)
	#define SHU4_R1_CA_CMD1_RK1_TX_ARCS1_DLY	GENMASK(19, 16)
	#define SHU4_R1_CA_CMD1_RK1_TX_ARCS2_DLY	GENMASK(23, 20)
	#define SHU4_R1_CA_CMD1_RK1_TX_ARCLK_DLY	GENMASK(27, 24)
	#define SHU4_R1_CA_CMD1_RK1_TX_ARCLKB_DLY	GENMASK(31, 28)
#define SHU4_R1_CA_CMD2					0x00001ea8
	#define SHU4_R1_CA_CMD2_RG_RK1_RX_ARCA0_R_DLY	GENMASK(5, 0)
	#define SHU4_R1_CA_CMD2_RG_RK1_RX_ARCA0_F_DLY	GENMASK(13, 8)
	#define SHU4_R1_CA_CMD2_RG_RK1_RX_ARCA1_R_DLY	GENMASK(21, 16)
	#define SHU4_R1_CA_CMD2_RG_RK1_RX_ARCA1_F_DLY	GENMASK(29, 24)
#define SHU4_R1_CA_CMD3					0x00001eac
	#define SHU4_R1_CA_CMD3_RG_RK1_RX_ARCA2_R_DLY	GENMASK(5, 0)
	#define SHU4_R1_CA_CMD3_RG_RK1_RX_ARCA2_F_DLY	GENMASK(13, 8)
	#define SHU4_R1_CA_CMD3_RG_RK1_RX_ARCA3_R_DLY	GENMASK(21, 16)
	#define SHU4_R1_CA_CMD3_RG_RK1_RX_ARCA3_F_DLY	GENMASK(29, 24)
#define SHU4_R1_CA_CMD4					0x00001eb0
	#define SHU4_R1_CA_CMD4_RG_RK1_RX_ARCA4_R_DLY	GENMASK(5, 0)
	#define SHU4_R1_CA_CMD4_RG_RK1_RX_ARCA4_F_DLY	GENMASK(13, 8)
	#define SHU4_R1_CA_CMD4_RG_RK1_RX_ARCA5_R_DLY	GENMASK(21, 16)
	#define SHU4_R1_CA_CMD4_RG_RK1_RX_ARCA5_F_DLY	GENMASK(29, 24)
#define SHU4_R1_CA_CMD5					0x00001eb4
	#define SHU4_R1_CA_CMD5_RG_RK1_RX_ARCKE0_R_DLY	GENMASK(5, 0)
	#define SHU4_R1_CA_CMD5_RG_RK1_RX_ARCKE0_F_DLY	GENMASK(13, 8)
	#define SHU4_R1_CA_CMD5_RG_RK1_RX_ARCKE1_R_DLY	GENMASK(21, 16)
	#define SHU4_R1_CA_CMD5_RG_RK1_RX_ARCKE1_F_DLY	GENMASK(29, 24)
#define SHU4_R1_CA_CMD6					0x00001eb8
	#define SHU4_R1_CA_CMD6_RG_RK1_RX_ARCKE2_R_DLY	GENMASK(5, 0)
	#define SHU4_R1_CA_CMD6_RG_RK1_RX_ARCKE2_F_DLY	GENMASK(13, 8)
	#define SHU4_R1_CA_CMD6_RG_RK1_RX_ARCS0_R_DLY	GENMASK(21, 16)
	#define SHU4_R1_CA_CMD6_RG_RK1_RX_ARCS0_F_DLY	GENMASK(29, 24)
#define SHU4_R1_CA_CMD7					0x00001ebc
	#define SHU4_R1_CA_CMD7_RG_RK1_RX_ARCS1_R_DLY	GENMASK(5, 0)
	#define SHU4_R1_CA_CMD7_RG_RK1_RX_ARCS1_F_DLY	GENMASK(13, 8)
	#define SHU4_R1_CA_CMD7_RG_RK1_RX_ARCS2_R_DLY	GENMASK(21, 16)
	#define SHU4_R1_CA_CMD7_RG_RK1_RX_ARCS2_F_DLY	GENMASK(29, 24)
#define SHU4_R1_CA_CMD8					0x00001ec0
	#define SHU4_R1_CA_CMD8_RG_RK1_RX_ARCLK_R_DLY	GENMASK(22, 16)
	#define SHU4_R1_CA_CMD8_RG_RK1_RX_ARCLK_F_DLY	GENMASK(30, 24)
#define SHU4_R1_CA_CMD9					0x00001ec4
	#define SHU4_R1_CA_CMD9_RG_RK1_ARPI_CS		GENMASK(5, 0)
	#define SHU4_R1_CA_CMD9_RG_RK1_ARPI_CMD		GENMASK(13, 8)
	#define SHU4_R1_CA_CMD9_RG_RK1_ARPI_CLK		GENMASK(29, 24)
#define RFU_0X1EC8					0x00001ec8
	#define RFU_0X1EC8_RESERVED_0X1EC8		GENMASK(31, 0)
#define RFU_0X1ECC					0x00001ecc
	#define RFU_0X1ECC_RESERVED_0X1ECC		GENMASK(31, 0)
#define SHU4_R2_B0_DQ0					0x00001f00
	#define SHU4_R2_B0_DQ0_RK2_TX_ARDQ0_DLY_B0	GENMASK(3, 0)
	#define SHU4_R2_B0_DQ0_RK2_TX_ARDQ1_DLY_B0	GENMASK(7, 4)
	#define SHU4_R2_B0_DQ0_RK2_TX_ARDQ2_DLY_B0	GENMASK(11, 8)
	#define SHU4_R2_B0_DQ0_RK2_TX_ARDQ3_DLY_B0	GENMASK(15, 12)
	#define SHU4_R2_B0_DQ0_RK2_TX_ARDQ4_DLY_B0	GENMASK(19, 16)
	#define SHU4_R2_B0_DQ0_RK2_TX_ARDQ5_DLY_B0	GENMASK(23, 20)
	#define SHU4_R2_B0_DQ0_RK2_TX_ARDQ6_DLY_B0	GENMASK(27, 24)
	#define SHU4_R2_B0_DQ0_RK2_TX_ARDQ7_DLY_B0	GENMASK(31, 28)
#define SHU4_R2_B0_DQ1					0x00001f04
	#define SHU4_R2_B0_DQ1_RK2_TX_ARDQM0_DLY_B0	GENMASK(3, 0)
	#define SHU4_R2_B0_DQ1_RK2_TX_ARDQS0_DLYB_B0	GENMASK(19, 16)
	#define SHU4_R2_B0_DQ1_RK2_TX_ARDQS0B_DLYB_B0	GENMASK(23, 20)
	#define SHU4_R2_B0_DQ1_RK2_TX_ARDQS0_DLY_B0	GENMASK(27, 24)
	#define SHU4_R2_B0_DQ1_RK2_TX_ARDQS0B_DLY_B0	GENMASK(31, 28)
#define SHU4_R2_B0_DQ2					0x00001f08
	#define SHU4_R2_B0_DQ2_RK2_RX_ARDQ0_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R2_B0_DQ2_RK2_RX_ARDQ0_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R2_B0_DQ2_RK2_RX_ARDQ1_R_DLY_B0	GENMASK(21, 16)
	#define SHU4_R2_B0_DQ2_RK2_RX_ARDQ1_F_DLY_B0	GENMASK(29, 24)
#define SHU4_R2_B0_DQ3					0x00001f0c
	#define SHU4_R2_B0_DQ3_RK2_RX_ARDQ2_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R2_B0_DQ3_RK2_RX_ARDQ2_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R2_B0_DQ3_RK2_RX_ARDQ3_R_DLY_B0	GENMASK(21, 16)
	#define SHU4_R2_B0_DQ3_RK2_RX_ARDQ3_F_DLY_B0	GENMASK(29, 24)
#define SHU4_R2_B0_DQ4					0x00001f10
	#define SHU4_R2_B0_DQ4_RK2_RX_ARDQ4_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R2_B0_DQ4_RK2_RX_ARDQ4_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R2_B0_DQ4_RK2_RX_ARDQ5_R_DLY_B0	GENMASK(21, 16)
	#define SHU4_R2_B0_DQ4_RK2_RX_ARDQ5_F_DLY_B0	GENMASK(29, 24)
#define SHU4_R2_B0_DQ5					0x00001f14
	#define SHU4_R2_B0_DQ5_RK2_RX_ARDQ6_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R2_B0_DQ5_RK2_RX_ARDQ6_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R2_B0_DQ5_RK2_RX_ARDQ7_R_DLY_B0	GENMASK(21, 16)
	#define SHU4_R2_B0_DQ5_RK2_RX_ARDQ7_F_DLY_B0	GENMASK(29, 24)
#define SHU4_R2_B0_DQ6					0x00001f18
	#define SHU4_R2_B0_DQ6_RK2_RX_ARDQM0_R_DLY_B0	GENMASK(5, 0)
	#define SHU4_R2_B0_DQ6_RK2_RX_ARDQM0_F_DLY_B0	GENMASK(13, 8)
	#define SHU4_R2_B0_DQ6_RK2_RX_ARDQS0_R_DLY_B0	GENMASK(22, 16)
	#define SHU4_R2_B0_DQ6_RK2_RX_ARDQS0_F_DLY_B0	GENMASK(30, 24)
#define SHU4_R2_B0_DQ7					0x00001f1c
	#define SHU4_R2_B0_DQ7_RK2_ARPI_DQ_B0		GENMASK(13, 8)
	#define SHU4_R2_B0_DQ7_RK2_ARPI_DQM_B0		GENMASK(21, 16)
	#define SHU4_R2_B0_DQ7_RK2_ARPI_PBYTE_B0	GENMASK(29, 24)
#define RFU_0X1F20					0x00001f20
	#define RFU_0X1F20_RESERVED_0X1F20		GENMASK(31, 0)
#define RFU_0X1F24					0x00001f24
	#define RFU_0X1F24_RESERVED_0X1F24		GENMASK(31, 0)
#define RFU_0X1F28					0x00001f28
	#define RFU_0X1F28_RESERVED_0X1F28		GENMASK(31, 0)
#define RFU_0X1F2C					0x00001f2c
	#define RFU_0X1F2C_RESERVED_0X1F2C		GENMASK(31, 0)
#define SHU4_R2_B1_DQ0					0x00001f50
	#define SHU4_R2_B1_DQ0_RK2_TX_ARDQ0_DLY_B1	GENMASK(3, 0)
	#define SHU4_R2_B1_DQ0_RK2_TX_ARDQ1_DLY_B1	GENMASK(7, 4)
	#define SHU4_R2_B1_DQ0_RK2_TX_ARDQ2_DLY_B1	GENMASK(11, 8)
	#define SHU4_R2_B1_DQ0_RK2_TX_ARDQ3_DLY_B1	GENMASK(15, 12)
	#define SHU4_R2_B1_DQ0_RK2_TX_ARDQ4_DLY_B1	GENMASK(19, 16)
	#define SHU4_R2_B1_DQ0_RK2_TX_ARDQ5_DLY_B1	GENMASK(23, 20)
	#define SHU4_R2_B1_DQ0_RK2_TX_ARDQ6_DLY_B1	GENMASK(27, 24)
	#define SHU4_R2_B1_DQ0_RK2_TX_ARDQ7_DLY_B1	GENMASK(31, 28)
#define SHU4_R2_B1_DQ1					0x00001f54
	#define SHU4_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1	GENMASK(3, 0)
	#define SHU4_R2_B1_DQ1_RK2_TX_ARDQS0_DLYB_B1	GENMASK(19, 16)
	#define SHU4_R2_B1_DQ1_RK2_TX_ARDQS0B_DLYB_B1	GENMASK(23, 20)
	#define SHU4_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1	GENMASK(27, 24)
	#define SHU4_R2_B1_DQ1_RK2_TX_ARDQS0B_DLY_B1	GENMASK(31, 28)
#define SHU4_R2_B1_DQ2					0x00001f58
	#define SHU4_R2_B1_DQ2_RK2_RX_ARDQ0_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R2_B1_DQ2_RK2_RX_ARDQ0_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R2_B1_DQ2_RK2_RX_ARDQ1_R_DLY_B1	GENMASK(21, 16)
	#define SHU4_R2_B1_DQ2_RK2_RX_ARDQ1_F_DLY_B1	GENMASK(29, 24)
#define SHU4_R2_B1_DQ3					0x00001f5c
	#define SHU4_R2_B1_DQ3_RK2_RX_ARDQ2_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R2_B1_DQ3_RK2_RX_ARDQ2_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R2_B1_DQ3_RK2_RX_ARDQ3_R_DLY_B1	GENMASK(21, 16)
	#define SHU4_R2_B1_DQ3_RK2_RX_ARDQ3_F_DLY_B1	GENMASK(29, 24)
#define SHU4_R2_B1_DQ4					0x00001f60
	#define SHU4_R2_B1_DQ4_RK2_RX_ARDQ4_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R2_B1_DQ4_RK2_RX_ARDQ4_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R2_B1_DQ4_RK2_RX_ARDQ5_R_DLY_B1	GENMASK(21, 16)
	#define SHU4_R2_B1_DQ4_RK2_RX_ARDQ5_F_DLY_B1	GENMASK(29, 24)
#define SHU4_R2_B1_DQ5					0x00001f64
	#define SHU4_R2_B1_DQ5_RK2_RX_ARDQ6_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R2_B1_DQ5_RK2_RX_ARDQ6_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R2_B1_DQ5_RK2_RX_ARDQ7_R_DLY_B1	GENMASK(21, 16)
	#define SHU4_R2_B1_DQ5_RK2_RX_ARDQ7_F_DLY_B1	GENMASK(29, 24)
#define SHU4_R2_B1_DQ6					0x00001f68
	#define SHU4_R2_B1_DQ6_RK2_RX_ARDQM0_R_DLY_B1	GENMASK(5, 0)
	#define SHU4_R2_B1_DQ6_RK2_RX_ARDQM0_F_DLY_B1	GENMASK(13, 8)
	#define SHU4_R2_B1_DQ6_RK2_RX_ARDQS0_R_DLY_B1	GENMASK(22, 16)
	#define SHU4_R2_B1_DQ6_RK2_RX_ARDQS0_F_DLY_B1	GENMASK(30, 24)
#define SHU4_R2_B1_DQ7					0x00001f6c
	#define SHU4_R2_B1_DQ7_RK2_ARPI_DQ_B1		GENMASK(13, 8)
	#define SHU4_R2_B1_DQ7_RK2_ARPI_DQM_B1		GENMASK(21, 16)
	#define SHU4_R2_B1_DQ7_RK2_ARPI_PBYTE_B1	GENMASK(29, 24)
#define RFU_0X1F70					0x00001f70
	#define RFU_0X1F70_RESERVED_0X1F70		GENMASK(31, 0)
#define RFU_0X1F74					0x00001f74
	#define RFU_0X1F74_RESERVED_0X1F74		GENMASK(31, 0)
#define RFU_0X1F78					0x00001f78
	#define RFU_0X1F78_RESERVED_0X1F78		GENMASK(31, 0)
#define RFU_0X1F7C					0x00001f7c
	#define RFU_0X1F7C_RESERVED_0X1F7C		GENMASK(31, 0)
#define SHU4_R2_CA_CMD0					0x00001fa0
	#define SHU4_R2_CA_CMD0_RK2_TX_ARCA0_DLY	GENMASK(3, 0)
	#define SHU4_R2_CA_CMD0_RK2_TX_ARCA1_DLY	GENMASK(7, 4)
	#define SHU4_R2_CA_CMD0_RK2_TX_ARCA2_DLY	GENMASK(11, 8)
	#define SHU4_R2_CA_CMD0_RK2_TX_ARCA3_DLY	GENMASK(15, 12)
	#define SHU4_R2_CA_CMD0_RK2_TX_ARCA4_DLY	GENMASK(19, 16)
	#define SHU4_R2_CA_CMD0_RK2_TX_ARCA5_DLY	GENMASK(23, 20)
	#define SHU4_R2_CA_CMD0_RK2_TX_ARCLK_DLYB	GENMASK(27, 24)
	#define SHU4_R2_CA_CMD0_RK2_TX_ARCLKB_DLYB	GENMASK(31, 28)
#define SHU4_R2_CA_CMD1					0x00001fa4
	#define SHU4_R2_CA_CMD1_RK2_TX_ARCKE0_DLY	GENMASK(3, 0)
	#define SHU4_R2_CA_CMD1_RK2_TX_ARCKE1_DLY	GENMASK(7, 4)
	#define SHU4_R2_CA_CMD1_RK2_TX_ARCKE2_DLY	GENMASK(11, 8)
	#define SHU4_R2_CA_CMD1_RK2_TX_ARCS0_DLY	GENMASK(15, 12)
	#define SHU4_R2_CA_CMD1_RK2_TX_ARCS1_DLY	GENMASK(19, 16)
	#define SHU4_R2_CA_CMD1_RK2_TX_ARCS2_DLY	GENMASK(23, 20)
	#define SHU4_R2_CA_CMD1_RK2_TX_ARCLK_DLY	GENMASK(27, 24)
	#define SHU4_R2_CA_CMD1_RK2_TX_ARCLKB_DLY	GENMASK(31, 28)
#define SHU4_R2_CA_CMD2					0x00001fa8
	#define SHU4_R2_CA_CMD2_RG_RK2_RX_ARCA0_R_DLY	GENMASK(5, 0)
	#define SHU4_R2_CA_CMD2_RG_RK2_RX_ARCA0_F_DLY	GENMASK(13, 8)
	#define SHU4_R2_CA_CMD2_RG_RK2_RX_ARCA1_R_DLY	GENMASK(21, 16)
	#define SHU4_R2_CA_CMD2_RG_RK2_RX_ARCA1_F_DLY	GENMASK(29, 24)
#define SHU4_R2_CA_CMD3					0x00001fac
	#define SHU4_R2_CA_CMD3_RG_RK2_RX_ARCA2_R_DLY	GENMASK(5, 0)
	#define SHU4_R2_CA_CMD3_RG_RK2_RX_ARCA2_F_DLY	GENMASK(13, 8)
	#define SHU4_R2_CA_CMD3_RG_RK2_RX_ARCA3_R_DLY	GENMASK(21, 16)
	#define SHU4_R2_CA_CMD3_RG_RK2_RX_ARCA3_F_DLY	GENMASK(29, 24)
#define SHU4_R2_CA_CMD4					0x00001fb0
	#define SHU4_R2_CA_CMD4_RG_RK2_RX_ARCA4_R_DLY	GENMASK(5, 0)
	#define SHU4_R2_CA_CMD4_RG_RK2_RX_ARCA4_F_DLY	GENMASK(13, 8)
	#define SHU4_R2_CA_CMD4_RG_RK2_RX_ARCA5_R_DLY	GENMASK(21, 16)
	#define SHU4_R2_CA_CMD4_RG_RK2_RX_ARCA5_F_DLY	GENMASK(29, 24)
#define SHU4_R2_CA_CMD5					0x00001fb4
	#define SHU4_R2_CA_CMD5_RG_RK2_RX_ARCKE0_R_DLY	GENMASK(5, 0)
	#define SHU4_R2_CA_CMD5_RG_RK2_RX_ARCKE0_F_DLY	GENMASK(13, 8)
	#define SHU4_R2_CA_CMD5_RG_RK2_RX_ARCKE1_R_DLY	GENMASK(21, 16)
	#define SHU4_R2_CA_CMD5_RG_RK2_RX_ARCKE1_F_DLY	GENMASK(29, 24)
#define SHU4_R2_CA_CMD6					0x00001fb8
	#define SHU4_R2_CA_CMD6_RG_RK2_RX_ARCKE2_R_DLY	GENMASK(5, 0)
	#define SHU4_R2_CA_CMD6_RG_RK2_RX_ARCKE2_F_DLY	GENMASK(13, 8)
	#define SHU4_R2_CA_CMD6_RG_RK2_RX_ARCS0_R_DLY	GENMASK(21, 16)
	#define SHU4_R2_CA_CMD6_RG_RK2_RX_ARCS0_F_DLY	GENMASK(29, 24)
#define SHU4_R2_CA_CMD7					0x00001fbc
	#define SHU4_R2_CA_CMD7_RG_RK2_RX_ARCS1_R_DLY	GENMASK(5, 0)
	#define SHU4_R2_CA_CMD7_RG_RK2_RX_ARCS1_F_DLY	GENMASK(13, 8)
	#define SHU4_R2_CA_CMD7_RG_RK2_RX_ARCS2_R_DLY	GENMASK(21, 16)
	#define SHU4_R2_CA_CMD7_RG_RK2_RX_ARCS2_F_DLY	GENMASK(29, 24)
#define SHU4_R2_CA_CMD8					0x00001fc0
	#define SHU4_R2_CA_CMD8_RG_RK2_RX_ARCLK_R_DLY	GENMASK(22, 16)
	#define SHU4_R2_CA_CMD8_RG_RK2_RX_ARCLK_F_DLY	GENMASK(30, 24)
#define SHU4_R2_CA_CMD9					0x00001fc4
	#define SHU4_R2_CA_CMD9_RG_RK2_ARPI_CS		GENMASK(5, 0)
	#define SHU4_R2_CA_CMD9_RG_RK2_ARPI_CMD		GENMASK(13, 8)
	#define SHU4_R2_CA_CMD9_RG_RK2_ARPI_CLK		GENMASK(29, 24)
#define RFU_0X1FC8					0x00001fc8
	#define RFU_0X1FC8_RESERVED_0X1FC8		GENMASK(31, 0)
#define RFU_0X1FCC					0x00001fcc
	#define RFU_0X1FCC_RESERVED_0X1FCC		GENMASK(31, 0)

#endif /*__DDRPHY_WO_PLL_REG_H__*/