| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 43 Register llvm::constrainRegToClass(MachineRegisterInfo &MRI, in constrainRegToClass()
55 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass()
107 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass()
160 MachineRegisterInfo &MRI = MF.getRegInfo(); in constrainSelectedInstRegOperands() local
199 MachineRegisterInfo &MRI) { in canReplaceReg()
213 const MachineRegisterInfo &MRI) { in isTriviallyDead()
289 const MachineRegisterInfo &MRI) { in getIConstantVRegVal()
300 llvm::getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI) { in getIConstantVRegSExtVal()
313 Register VReg, const MachineRegisterInfo &MRI, IsOpcodeFn IsConstantOpcode, in getConstantVRegValWithLookThrough()
410 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) { in getIConstantVRegValWithLookThrough()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 222 static bool matchREV(MachineInstr &MI, MachineRegisterInfo &MRI, in matchREV()
251 static bool matchTRN(MachineInstr &MI, MachineRegisterInfo &MRI, in matchTRN()
272 static bool matchUZP(MachineInstr &MI, MachineRegisterInfo &MRI, in matchUZP()
288 static bool matchZip(MachineInstr &MI, MachineRegisterInfo &MRI, in matchZip()
306 MachineRegisterInfo &MRI, in matchDupFromInsertVectorElt()
345 MachineRegisterInfo &MRI, in matchDupFromBuildVector()
360 static bool matchDup(MachineInstr &MI, MachineRegisterInfo &MRI, in matchDup()
406 static bool matchEXT(MachineInstr &MI, MachineRegisterInfo &MRI, in matchEXT()
471 static bool matchINS(MachineInstr &MI, MachineRegisterInfo &MRI, in matchINS()
498 static bool applyINS(MachineInstr &MI, MachineRegisterInfo &MRI, in applyINS()
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| H A D | AArch64InstructionSelector.cpp | 681 auto &MRI = MF.getRegInfo(); in getImmedFromMO() local
706 const MachineRegisterInfo &MRI, in unsupportedBinOp()
859 static bool copySubReg(MachineInstr &I, MachineRegisterInfo &MRI, in copySubReg()
886 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in getRegClassesForCopy()
913 static bool selectDebugInstr(MachineInstr &I, MachineRegisterInfo &MRI, in selectDebugInstr()
943 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in selectCopy()
1113 MachineRegisterInfo &MRI = *MIB.getMRI(); in emitSelect() local
1393 MachineRegisterInfo &MRI) { in getTestBitReg()
1529 MachineRegisterInfo &MRI = *MIB.getMRI(); in emitTestBit() local
1602 MachineRegisterInfo &MRI = *MIB.getMRI(); in emitCBZ() local
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| H A D | AArch64PostLegalizerCombiner.cpp | 54 MachineInstr &MI, MachineRegisterInfo &MRI, in matchExtractVecEltPairwiseAdd()
97 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, in applyExtractVecEltPairwiseAdd()
113 static bool isSignExtended(Register R, MachineRegisterInfo &MRI) { in isSignExtended()
119 static bool isZeroExtended(Register R, MachineRegisterInfo &MRI) { in isZeroExtended()
125 MachineInstr &MI, MachineRegisterInfo &MRI, in matchAArch64MulConstCombine()
238 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, in applyAArch64MulConstCombine()
248 bool matchFoldMergeToZext(MachineInstr &MI, MachineRegisterInfo &MRI) { in matchFoldMergeToZext()
256 void applyFoldMergeToZext(MachineInstr &MI, MachineRegisterInfo &MRI, in applyFoldMergeToZext()
269 static bool matchMutateAnyExtToZExt(MachineInstr &MI, MachineRegisterInfo &MRI) { in matchMutateAnyExtToZExt()
286 static void applyMutateAnyExtToZExt(MachineInstr &MI, MachineRegisterInfo &MRI, in applyMutateAnyExtToZExt()
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| H A D | AArch64LegalizerInfo.cpp | 884 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in legalizeCustom() local
927 MachineRegisterInfo &MRI, in legalizeRotate()
943 static void extractParts(Register Reg, MachineRegisterInfo &MRI, in extractParts()
954 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in legalizeVectorTrunc() local
992 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder, in legalizeSmallCMGlobalValue()
1135 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder, in legalizeShlAshrLshr()
1158 MachineRegisterInfo &MRI) { in matchLDPSTPAddrMode()
1174 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder, in legalizeLoadStore()
1244 MachineRegisterInfo &MRI, in legalizeVaArg()
1292 MachineInstr &MI, MachineRegisterInfo &MRI, LegalizerHelper &Helper) const { in legalizeBitfieldExtract()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 350 MachineRegisterInfo &MRI = MF.getRegInfo(); in select() local
513 const MachineRegisterInfo &MRI, in X86SelectAddress()
539 MachineRegisterInfo &MRI, in selectLoadStoreOp()
599 MachineRegisterInfo &MRI, in selectFrameIndexOrGep()
627 MachineRegisterInfo &MRI, in selectGlobalValue()
673 MachineRegisterInfo &MRI, in selectConstant()
730 MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg, in selectTurnIntoCOPY()
745 MachineRegisterInfo &MRI, in selectTruncOrPtrToInt()
811 MachineRegisterInfo &MRI, in selectZext()
876 MachineRegisterInfo &MRI, in selectAnyext()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 30 unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI, in constrainRegToClass()
42 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass()
72 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass()
119 MachineRegisterInfo &MRI = MF.getRegInfo(); in constrainSelectedInstRegOperands() local
159 const MachineRegisterInfo &MRI) { in isTriviallyDead()
208 const MachineRegisterInfo &MRI) { in getConstantVRegVal()
219 unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs, in getConstantVRegValWithLookThrough()
296 const MachineRegisterInfo &MRI) { in getConstantFPVRegVal()
304 const MachineRegisterInfo &MRI) { in getDefIgnoringCopies()
320 const MachineRegisterInfo &MRI) { in getOpcodeDef()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 314 MachineRegisterInfo &MRI = MF.getRegInfo(); in select() local
474 const MachineRegisterInfo &MRI, in X86SelectAddress()
500 MachineRegisterInfo &MRI, in selectLoadStoreOp()
560 MachineRegisterInfo &MRI, in selectFrameIndexOrGep()
588 MachineRegisterInfo &MRI, in selectGlobalValue()
634 MachineRegisterInfo &MRI, in selectConstant()
691 MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg, in selectTurnIntoCOPY()
706 MachineRegisterInfo &MRI, in selectTruncOrPtrToInt()
772 MachineRegisterInfo &MRI, in selectZext()
883 MachineRegisterInfo &MRI, in selectAnyext()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 1135 MachineRegisterInfo &MRI, in legalizeCustom()
1182 MachineRegisterInfo &MRI, in getSegmentAperture()
1251 MachineInstr &MI, MachineRegisterInfo &MRI, in legalizeAddrSpaceCast()
1357 MachineInstr &MI, MachineRegisterInfo &MRI, in legalizeFrint()
1384 MachineInstr &MI, MachineRegisterInfo &MRI, in legalizeFceil()
1429 MachineInstr &MI, MachineRegisterInfo &MRI, in legalizeIntrinsicTrunc()
1475 MachineInstr &MI, MachineRegisterInfo &MRI, in legalizeITOFP()
1507 MachineInstr &MI, MachineRegisterInfo &MRI, in legalizeMinNumMaxNum()
1531 MachineInstr &MI, MachineRegisterInfo &MRI, in legalizeExtractVectorElt()
1560 MachineInstr &MI, MachineRegisterInfo &MRI, in legalizeInsertVectorElt()
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| H A D | SIInstrInfo.cpp | 482 const MachineRegisterInfo &MRI = in shouldClusterMemOps() local
762 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); in materializeImmediate() local
825 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); in insertVectorSelect() local
951 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in insertEQ() local
964 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in insertNE() local
1081 MachineRegisterInfo &MRI = MF->getRegInfo(); in storeRegToStackSlot() local
1105 MachineRegisterInfo &MRI = MF->getRegInfo(); in storeRegToStackSlot() local
1207 MachineRegisterInfo &MRI = MF->getRegInfo(); in loadRegFromStackSlot() local
1225 MachineRegisterInfo &MRI = MF->getRegInfo(); in loadRegFromStackSlot() local
1579 MachineRegisterInfo &MRI = MF->getRegInfo(); in expandMovDPP64() local
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| H A D | AMDGPURegisterBankInfo.cpp | 45 MachineRegisterInfo &MRI; member in __anonb2c26eb80111::ApplyRegBankMapping
240 const MachineInstr &MI, const MachineRegisterInfo &MRI, in addMappingFromTable()
421 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrAlternativeMappings() local
681 MachineRegisterInfo *MRI = B.getMRI(); in split64BitValueForMapping() local
698 static void setRegsToType(MachineRegisterInfo &MRI, ArrayRef<Register> Regs, in setRegsToType()
1037 MachineRegisterInfo &MRI, ArrayRef<unsigned> OpIndices) const { in collectWaterfallOperands()
1051 MachineIRBuilder &B, MachineInstr &MI, MachineRegisterInfo &MRI, in executeInWaterfallLoop()
1066 MachineInstr &MI, MachineRegisterInfo &MRI, in executeInWaterfallLoop()
1074 MachineInstr &MI, MachineRegisterInfo &MRI, unsigned OpIdx) const { in constrainOpWithReadfirstlane()
1101 static MachineInstr *getOtherVRegDef(const MachineRegisterInfo &MRI, in getOtherVRegDef()
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| H A D | GCNRegPressure.cpp | 38 const MachineRegisterInfo &MRI) { in printLivesAt()
86 const MachineRegisterInfo &MRI) { in getRegKind()
100 const MachineRegisterInfo &MRI) { in inc()
199 const MachineRegisterInfo &MRI) { in getDefRegMask()
211 const MachineRegisterInfo &MRI, in getUsedRegMask()
231 const MachineRegisterInfo &MRI) { in collectVirtualRegUses()
259 const MachineRegisterInfo &MRI) { in getLiveLaneMask()
277 const MachineRegisterInfo &MRI) { in getLiveRegs()
498 const MachineRegisterInfo &MRI) { in printLiveRegs()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 135 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in resultDependsOnExec() local
1072 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); in materializeImmediate() local
1135 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); in insertVectorSelect() local
1259 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in insertEQ() local
1272 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in insertNE() local
1594 MachineRegisterInfo &MRI = MF->getRegInfo(); in storeRegToStackSlot() local
1806 MachineRegisterInfo &MRI = MF->getRegInfo(); in loadRegFromStackSlot() local
2298 MachineRegisterInfo &MRI = MF->getRegInfo(); in expandMovDPP64() local
2524 MachineRegisterInfo &MRI = MF->getRegInfo(); in insertIndirectBranch() local
2856 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); in canInsertSelect() local
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| H A D | AMDGPULegalizerInfo.cpp | 1742 MachineRegisterInfo &MRI = *B.getMRI(); in legalizeCustom() local
1824 MachineRegisterInfo &MRI, in getSegmentAperture()
1909 static bool isKnownNonNull(Register Val, MachineRegisterInfo &MRI, in isKnownNonNull()
1929 MachineInstr &MI, MachineRegisterInfo &MRI, in legalizeAddrSpaceCast()
2042 MachineInstr &MI, MachineRegisterInfo &MRI, in legalizeFrint()
2068 MachineInstr &MI, MachineRegisterInfo &MRI, in legalizeFceil()
2097 MachineInstr &MI, MachineRegisterInfo &MRI, in legalizeFrem()
2131 MachineInstr &MI, MachineRegisterInfo &MRI, in legalizeIntrinsicTrunc()
2176 MachineInstr &MI, MachineRegisterInfo &MRI, in legalizeITOFP()
2239 MachineRegisterInfo &MRI, in legalizeFPTOI()
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| H A D | AMDGPURegisterBankInfo.cpp | 101 MachineRegisterInfo &MRI; member in __anon881ae5be0111::ApplyRegBankMapping
298 const MachineInstr &MI, const MachineRegisterInfo &MRI, in addMappingFromTable()
457 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrAlternativeMappings() local
646 MachineRegisterInfo *MRI = B.getMRI(); in split64BitValueForMapping() local
663 static void setRegsToType(MachineRegisterInfo &MRI, ArrayRef<Register> Regs, in setRegsToType()
685 MachineRegisterInfo &MRI, in buildReadFirstLane()
974 MachineRegisterInfo &MRI, ArrayRef<unsigned> OpIndices) const { in collectWaterfallOperands()
988 MachineIRBuilder &B, MachineInstr &MI, MachineRegisterInfo &MRI, in executeInWaterfallLoop()
1003 MachineInstr &MI, MachineRegisterInfo &MRI, in executeInWaterfallLoop()
1011 MachineInstr &MI, MachineRegisterInfo &MRI, unsigned OpIdx) const { in constrainOpWithReadfirstlane()
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| H A D | GCNRegPressure.cpp | 39 const MachineRegisterInfo &MRI) { in getRegKind()
53 const MachineRegisterInfo &MRI) { in inc()
159 const MachineRegisterInfo &MRI) { in getDefRegMask()
171 const MachineRegisterInfo &MRI, in getUsedRegMask()
191 const MachineRegisterInfo &MRI) { in collectVirtualRegUses()
218 const MachineRegisterInfo &MRI) { in getLiveLaneMask()
236 const MachineRegisterInfo &MRI) { in getLiveRegs()
457 const MachineRegisterInfo &MRI) { in print()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 432 const MachineRegisterInfo &MRI, in unsupportedBinOp()
584 const MachineRegisterInfo &MRI, in isValidCopy()
620 static bool selectSubregisterCopy(MachineInstr &I, MachineRegisterInfo &MRI, in selectSubregisterCopy()
646 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in getRegClassesForCopy()
671 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in selectCopy()
859 static unsigned selectSelectOpc(MachineInstr &I, MachineRegisterInfo &MRI, in selectSelectOpc()
873 static unsigned selectFCMPOpc(MachineInstr &I, MachineRegisterInfo &MRI) { in selectFCMPOpc()
1040 MachineRegisterInfo &MRI) { in getVectorShiftImm()
1065 static Optional<int64_t> getVectorSHLImm(LLT SrcTy, Register Reg, MachineRegisterInfo &MRI) { in getVectorSHLImm()
1215 MachineRegisterInfo &MRI = MF.getRegInfo(); in materializeLargeCMVal() local
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 334 const MachineRegisterInfo &MRI = in shouldClusterMemOps() local
594 MachineRegisterInfo &MRI = MF->getRegInfo(); in storeRegToStackSlot() local
694 MachineRegisterInfo &MRI = MF->getRegInfo(); in loadRegFromStackSlot() local
977 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in commuteInstructionImpl() local
1577 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI, in usesConstantBus()
1651 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in verifyInstruction() local
1849 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in getOpRegClass() local
1880 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in legalizeOpWithMove() local
1902 MachineRegisterInfo &MRI, in buildExtractSubReg()
1935 MachineRegisterInfo &MRI, in buildExtractSubRegOrImm()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPreLegalizer.cpp | 42 MachineRegisterInfo &MRI = MF.getRegInfo(); in addConstantsToTrack() local
97 MachineRegisterInfo &MRI = MF.getRegInfo(); in foldConstantsIntoIntrinsics() local
146 MachineRegisterInfo &MRI, in propagateSPIRVType()
197 MachineRegisterInfo &MRI) { in insertAssignInstr()
227 MachineRegisterInfo &MRI = MF.getRegInfo(); in generateAssignInstrs() local
303 createNewIdReg(Register ValReg, unsigned Opcode, MachineRegisterInfo &MRI, in createNewIdReg()
331 MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR) { in processInstr()
357 MachineRegisterInfo &MRI = MF.getRegInfo(); in processInstrsWithTypeFolding() local
422 MachineRegisterInfo &MRI = MF.getRegInfo(); in processSwitches() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/ |
| H A D | AliasAnalysis.h | 139 LLVM_NODISCARD inline bool isNoModRef(const ModRefInfo MRI) { in isNoModRef()
143 LLVM_NODISCARD inline bool isModOrRefSet(const ModRefInfo MRI) { in isModOrRefSet()
146 LLVM_NODISCARD inline bool isModAndRefSet(const ModRefInfo MRI) { in isModAndRefSet()
150 LLVM_NODISCARD inline bool isModSet(const ModRefInfo MRI) { in isModSet()
153 LLVM_NODISCARD inline bool isRefSet(const ModRefInfo MRI) { in isRefSet()
156 LLVM_NODISCARD inline bool isMustSet(const ModRefInfo MRI) { in isMustSet()
160 LLVM_NODISCARD inline ModRefInfo setMod(const ModRefInfo MRI) { in setMod()
164 LLVM_NODISCARD inline ModRefInfo setRef(const ModRefInfo MRI) { in setRef()
168 LLVM_NODISCARD inline ModRefInfo setMust(const ModRefInfo MRI) { in setMust()
172 LLVM_NODISCARD inline ModRefInfo setModAndRef(const ModRefInfo MRI) { in setModAndRef()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.cpp | 173 Register Reg, const MachineRegisterInfo &MRI) { in addDefUses()
188 Register Reg, const MachineRegisterInfo &MRI) { in addUseDef()
199 const MachineRegisterInfo &MRI = MF.getRegInfo(); in skipCopiesOutgoing() local
213 const MachineRegisterInfo &MRI = MF.getRegInfo(); in skipCopiesIncoming() local
226 const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo(); in AmbiguousRegDefUseContainer() local
341 const MachineRegisterInfo &MRI = MF.getRegInfo(); in setTypesAccordingToPhysicalRegister() local
406 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrMapping() local
669 MachineRegisterInfo &MRI = OpdMapper.getMRI(); in applyMappingImpl() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.cpp | 180 Register Reg, const MachineRegisterInfo &MRI) { in addDefUses()
195 Register Reg, const MachineRegisterInfo &MRI) { in addUseDef()
206 const MachineRegisterInfo &MRI = MF.getRegInfo(); in skipCopiesOutgoing() local
220 const MachineRegisterInfo &MRI = MF.getRegInfo(); in skipCopiesIncoming() local
233 const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo(); in AmbiguousRegDefUseContainer() local
367 const MachineRegisterInfo &MRI = MF.getRegInfo(); in setTypesAccordingToPhysicalRegister() local
433 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrMapping() local
731 MachineRegisterInfo &MRI = OpdMapper.getMRI(); in applyMappingImpl() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 102 void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, in checkADDrr()
154 void BPFMISimplifyPatchable::checkShift(MachineRegisterInfo *MRI, in checkShift()
168 void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI, in processCandidate()
203 void BPFMISimplifyPatchable::processDstReg(MachineRegisterInfo *MRI, in processDstReg()
240 void BPFMISimplifyPatchable::processInst(MachineRegisterInfo *MRI, in processInst()
260 MachineRegisterInfo *MRI = &MF->getRegInfo(); in removeLD() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 88 void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, in checkADDrr()
131 void BPFMISimplifyPatchable::checkShift(MachineRegisterInfo *MRI, in checkShift()
145 void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI, in processCandidate()
178 void BPFMISimplifyPatchable::processDstReg(MachineRegisterInfo *MRI, in processDstReg()
215 void BPFMISimplifyPatchable::processInst(MachineRegisterInfo *MRI, in processInst()
230 MachineRegisterInfo *MRI = &MF->getRegInfo(); in removeLD() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 99 MachineRegisterInfo &MRI, in convertImplicitDefToConstZero()
266 const MachineRegisterInfo &MRI, in getVRegDef()
283 static bool hasOneUse(unsigned Reg, MachineInstr *Def, MachineRegisterInfo &MRI, in hasOneUse()
315 const MachineRegisterInfo &MRI) { in isSafeToMove()
436 const MachineRegisterInfo &MRI, in oneUseDominatesOtherUses()
524 MachineRegisterInfo &MRI) { in moveForSingleUse()
568 WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, in rematerializeCheapDef()
636 MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII) { in moveAndTeeForMultiUse()
810 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction() local
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