1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_tsc.h 4 * @author MCD Application Team 5 * @brief Header file of TSC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_HAL_TSC_H 22 #define STM32L4xx_HAL_TSC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l4xx_hal_def.h" 30 31 /** @addtogroup STM32L4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup TSC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup TSC_Exported_Types TSC Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief TSC state structure definition 46 */ 47 typedef enum 48 { 49 HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */ 50 HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */ 51 HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */ 52 HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */ 53 } HAL_TSC_StateTypeDef; 54 55 /** 56 * @brief TSC group status structure definition 57 */ 58 typedef enum 59 { 60 TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */ 61 TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */ 62 } TSC_GroupStatusTypeDef; 63 64 /** 65 * @brief TSC init structure definition 66 */ 67 typedef struct 68 { 69 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length 70 This parameter can be a value of @ref TSC_CTPulseHL_Config */ 71 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length 72 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 73 FunctionalState SpreadSpectrum; /*!< Spread spectrum activation 74 This parameter can be set to ENABLE or DISABLE. */ 75 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation 76 This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ 77 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler 78 This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ 79 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler 80 This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */ 81 uint32_t MaxCountValue; /*!< Max count value 82 This parameter can be a value of @ref TSC_MaxCount_Value */ 83 uint32_t IODefaultMode; /*!< IO default mode 84 This parameter can be a value of @ref TSC_IO_Default_Mode */ 85 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity 86 This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ 87 uint32_t AcquisitionMode; /*!< Acquisition mode 88 This parameter can be a value of @ref TSC_Acquisition_Mode */ 89 FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation 90 This parameter can be set to ENABLE or DISABLE. */ 91 uint32_t ChannelIOs; /*!< Channel IOs mask */ 92 uint32_t ShieldIOs; /*!< Shield IOs mask */ 93 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 94 } TSC_InitTypeDef; 95 96 /** 97 * @brief TSC IOs configuration structure definition 98 */ 99 typedef struct 100 { 101 uint32_t ChannelIOs; /*!< Channel IOs mask */ 102 uint32_t ShieldIOs; /*!< Shield IOs mask */ 103 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 104 } TSC_IOConfigTypeDef; 105 106 /** 107 * @brief TSC handle Structure definition 108 */ 109 typedef struct __TSC_HandleTypeDef 110 { 111 TSC_TypeDef *Instance; /*!< Register base address */ 112 TSC_InitTypeDef Init; /*!< Initialization parameters */ 113 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ 114 HAL_LockTypeDef Lock; /*!< Lock feature */ 115 __IO uint32_t ErrorCode; /*!< I2C Error code */ 116 117 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 118 void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ 119 void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ 120 121 void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ 122 void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ 123 124 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 125 } TSC_HandleTypeDef; 126 127 enum 128 { 129 TSC_GROUP1_IDX = 0x00UL, 130 TSC_GROUP2_IDX, 131 TSC_GROUP3_IDX, 132 TSC_GROUP4_IDX, 133 #if defined(TSC_IOCCR_G5_IO1) 134 TSC_GROUP5_IDX, 135 #endif 136 #if defined(TSC_IOCCR_G6_IO1) 137 TSC_GROUP6_IDX, 138 #endif 139 #if defined(TSC_IOCCR_G7_IO1) 140 TSC_GROUP7_IDX, 141 #endif 142 #if defined(TSC_IOCCR_G8_IO1) 143 TSC_GROUP8_IDX, 144 #endif 145 TSC_NB_OF_GROUPS 146 }; 147 148 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 149 /** 150 * @brief HAL TSC Callback ID enumeration definition 151 */ 152 typedef enum 153 { 154 HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */ 155 HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */ 156 157 HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */ 158 HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */ 159 160 } HAL_TSC_CallbackIDTypeDef; 161 162 /** 163 * @brief HAL TSC Callback pointer definition 164 */ 165 typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ 166 167 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 168 169 /** 170 * @} 171 */ 172 173 /* Exported constants --------------------------------------------------------*/ 174 /** @defgroup TSC_Exported_Constants TSC Exported Constants 175 * @{ 176 */ 177 178 /** @defgroup TSC_Error_Code_definition TSC Error Code definition 179 * @brief TSC Error Code definition 180 * @{ 181 */ 182 #define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */ 183 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 184 #define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */ 185 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 186 /** 187 * @} 188 */ 189 190 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length 191 * @{ 192 */ 193 #define TSC_CTPH_1CYCLE 0x00000000UL /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ 194 #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ 195 #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ 196 #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ 197 #define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ 198 #define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ 199 #define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ 200 #define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ 201 #define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ 202 #define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ 203 #define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ 204 #define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ 205 #define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ 206 #define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ 207 #define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ 208 #define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ 209 /** 210 * @} 211 */ 212 213 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length 214 * @{ 215 */ 216 #define TSC_CTPL_1CYCLE 0x00000000UL /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ 217 #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ 218 #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ 219 #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ 220 #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ 221 #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ 222 #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ 223 #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ 224 #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ 225 #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ 226 #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ 227 #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ 228 #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ 229 #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ 230 #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ 231 #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ 232 /** 233 * @} 234 */ 235 236 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler 237 * @{ 238 */ 239 #define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */ 240 #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ 241 /** 242 * @} 243 */ 244 245 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler 246 * @{ 247 */ 248 #define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */ 249 #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ 250 #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ 251 #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ 252 #define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ 253 #define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ 254 #define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ 255 #define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ 256 /** 257 * @} 258 */ 259 260 /** @defgroup TSC_MaxCount_Value Max Count Value 261 * @{ 262 */ 263 #define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */ 264 #define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ 265 #define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ 266 #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ 267 #define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ 268 #define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ 269 #define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ 270 /** 271 * @} 272 */ 273 274 /** @defgroup TSC_IO_Default_Mode IO Default Mode 275 * @{ 276 */ 277 #define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */ 278 #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ 279 /** 280 * @} 281 */ 282 283 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity 284 * @{ 285 */ 286 #define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */ 287 #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ 288 /** 289 * @} 290 */ 291 292 /** @defgroup TSC_Acquisition_Mode Acquisition Mode 293 * @{ 294 */ 295 #define TSC_ACQ_MODE_NORMAL 0x00000000UL /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ 296 #define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */ 297 /** 298 * @} 299 */ 300 301 /** @defgroup TSC_interrupts_definition Interrupts definition 302 * @{ 303 */ 304 #define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ 305 #define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ 306 /** 307 * @} 308 */ 309 310 /** @defgroup TSC_flags_definition Flags definition 311 * @{ 312 */ 313 #define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ 314 #define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ 315 /** 316 * @} 317 */ 318 319 /** @defgroup TSC_Group_definition Group definition 320 * @{ 321 */ 322 #define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX) 323 #define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX) 324 #define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX) 325 #define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX) 326 #if defined(TSC_IOCCR_G5_IO1) 327 #define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) 328 #endif 329 #if defined(TSC_IOCCR_G6_IO1) 330 #define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) 331 #endif 332 #if defined(TSC_IOCCR_G7_IO1) 333 #define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) 334 #endif 335 #if defined(TSC_IOCCR_G8_IO1) 336 #define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX) 337 #endif 338 339 #define TSC_GROUPX_NOT_SUPPORTED 0xFF000000UL /*!< TSC GroupX not supported */ 340 341 #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ 342 #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ 343 #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ 344 #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ 345 346 #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ 347 #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ 348 #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ 349 #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ 350 351 #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ 352 #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ 353 #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ 354 #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ 355 356 #define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ 357 #define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ 358 #define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ 359 #define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ 360 #if defined(TSC_IOCCR_G5_IO1) 361 362 #define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ 363 #define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ 364 #define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ 365 #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ 366 #else 367 368 #define TSC_GROUP5_IO1 (uint32_t)(0x00000010UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group5 IO1 not supported */ 369 #define TSC_GROUP5_IO2 TSC_GROUP5_IO1 /*!< TSC Group5 IO2 not supported */ 370 #define TSC_GROUP5_IO3 TSC_GROUP5_IO1 /*!< TSC Group5 IO3 not supported */ 371 #define TSC_GROUP5_IO4 TSC_GROUP5_IO1 /*!< TSC Group5 IO4 not supported */ 372 #endif 373 #if defined(TSC_IOCCR_G6_IO1) 374 375 #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ 376 #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ 377 #define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ 378 #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ 379 #else 380 381 #define TSC_GROUP6_IO1 (uint32_t)(0x00000020UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group6 IO1 not supported */ 382 #define TSC_GROUP6_IO2 TSC_GROUP6_IO1 /*!< TSC Group6 IO2 not supported */ 383 #define TSC_GROUP6_IO3 TSC_GROUP6_IO1 /*!< TSC Group6 IO3 not supported */ 384 #define TSC_GROUP6_IO4 TSC_GROUP6_IO1 /*!< TSC Group6 IO4 not supported */ 385 #endif 386 #if defined(TSC_IOCCR_G7_IO1) 387 388 #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ 389 #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ 390 #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ 391 #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ 392 #else 393 394 #define TSC_GROUP7_IO1 (uint32_t)(0x00000040UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group7 IO1 not supported */ 395 #define TSC_GROUP7_IO2 TSC_GROUP7_IO1 /*!< TSC Group7 IO2 not supported */ 396 #define TSC_GROUP7_IO3 TSC_GROUP7_IO1 /*!< TSC Group7 IO3 not supported */ 397 #define TSC_GROUP7_IO4 TSC_GROUP7_IO1 /*!< TSC Group7 IO4 not supported */ 398 #endif 399 #if defined(TSC_IOCCR_G8_IO1) 400 401 #define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ 402 #define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ 403 #define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ 404 #define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ 405 #else 406 407 #define TSC_GROUP8_IO1 (uint32_t)(0x00000080UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */ 408 #define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */ 409 #define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */ 410 #define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */ 411 #endif 412 /** 413 * @} 414 */ 415 416 /** 417 * @} 418 */ 419 420 /* Exported macros -----------------------------------------------------------*/ 421 422 /** @defgroup TSC_Exported_Macros TSC Exported Macros 423 * @{ 424 */ 425 426 /** @brief Reset TSC handle state. 427 * @param __HANDLE__ TSC handle 428 * @retval None 429 */ 430 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 431 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 432 (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ 433 (__HANDLE__)->MspInitCallback = NULL; \ 434 (__HANDLE__)->MspDeInitCallback = NULL; \ 435 } while(0) 436 #else 437 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) 438 #endif 439 440 /** 441 * @brief Enable the TSC peripheral. 442 * @param __HANDLE__ TSC handle 443 * @retval None 444 */ 445 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) 446 447 /** 448 * @brief Disable the TSC peripheral. 449 * @param __HANDLE__ TSC handle 450 * @retval None 451 */ 452 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE)) 453 454 /** 455 * @brief Start acquisition. 456 * @param __HANDLE__ TSC handle 457 * @retval None 458 */ 459 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) 460 461 /** 462 * @brief Stop acquisition. 463 * @param __HANDLE__ TSC handle 464 * @retval None 465 */ 466 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START)) 467 468 /** 469 * @brief Set IO default mode to output push-pull low. 470 * @param __HANDLE__ TSC handle 471 * @retval None 472 */ 473 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF)) 474 475 /** 476 * @brief Set IO default mode to input floating. 477 * @param __HANDLE__ TSC handle 478 * @retval None 479 */ 480 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) 481 482 /** 483 * @brief Set synchronization polarity to falling edge. 484 * @param __HANDLE__ TSC handle 485 * @retval None 486 */ 487 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL)) 488 489 /** 490 * @brief Set synchronization polarity to rising edge and high level. 491 * @param __HANDLE__ TSC handle 492 * @retval None 493 */ 494 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) 495 496 /** 497 * @brief Enable TSC interrupt. 498 * @param __HANDLE__ TSC handle 499 * @param __INTERRUPT__ TSC interrupt 500 * @retval None 501 */ 502 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 503 504 /** 505 * @brief Disable TSC interrupt. 506 * @param __HANDLE__ TSC handle 507 * @param __INTERRUPT__ TSC interrupt 508 * @retval None 509 */ 510 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 511 512 /** @brief Check whether the specified TSC interrupt source is enabled or not. 513 * @param __HANDLE__ TSC Handle 514 * @param __INTERRUPT__ TSC interrupt 515 * @retval SET or RESET 516 */ 517 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 518 519 /** 520 * @brief Check whether the specified TSC flag is set or not. 521 * @param __HANDLE__ TSC handle 522 * @param __FLAG__ TSC flag 523 * @retval SET or RESET 524 */ 525 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 526 527 /** 528 * @brief Clear the TSC's pending flag. 529 * @param __HANDLE__ TSC handle 530 * @param __FLAG__ TSC flag 531 * @retval None 532 */ 533 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 534 535 /** 536 * @brief Enable schmitt trigger hysteresis on a group of IOs. 537 * @param __HANDLE__ TSC handle 538 * @param __GX_IOY_MASK__ IOs mask 539 * @retval None 540 */ 541 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) 542 543 /** 544 * @brief Disable schmitt trigger hysteresis on a group of IOs. 545 * @param __HANDLE__ TSC handle 546 * @param __GX_IOY_MASK__ IOs mask 547 * @retval None 548 */ 549 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (~(__GX_IOY_MASK__))) 550 551 /** 552 * @brief Open analog switch on a group of IOs. 553 * @param __HANDLE__ TSC handle 554 * @param __GX_IOY_MASK__ IOs mask 555 * @retval None 556 */ 557 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (~(__GX_IOY_MASK__))) 558 559 /** 560 * @brief Close analog switch on a group of IOs. 561 * @param __HANDLE__ TSC handle 562 * @param __GX_IOY_MASK__ IOs mask 563 * @retval None 564 */ 565 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) 566 567 /** 568 * @brief Enable a group of IOs in channel mode. 569 * @param __HANDLE__ TSC handle 570 * @param __GX_IOY_MASK__ IOs mask 571 * @retval None 572 */ 573 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) 574 575 /** 576 * @brief Disable a group of channel IOs. 577 * @param __HANDLE__ TSC handle 578 * @param __GX_IOY_MASK__ IOs mask 579 * @retval None 580 */ 581 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (~(__GX_IOY_MASK__))) 582 583 /** 584 * @brief Enable a group of IOs in sampling mode. 585 * @param __HANDLE__ TSC handle 586 * @param __GX_IOY_MASK__ IOs mask 587 * @retval None 588 */ 589 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) 590 591 /** 592 * @brief Disable a group of sampling IOs. 593 * @param __HANDLE__ TSC handle 594 * @param __GX_IOY_MASK__ IOs mask 595 * @retval None 596 */ 597 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__))) 598 599 /** 600 * @brief Enable acquisition groups. 601 * @param __HANDLE__ TSC handle 602 * @param __GX_MASK__ Groups mask 603 * @retval None 604 */ 605 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) 606 607 /** 608 * @brief Disable acquisition groups. 609 * @param __HANDLE__ TSC handle 610 * @param __GX_MASK__ Groups mask 611 * @retval None 612 */ 613 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__))) 614 615 /** @brief Gets acquisition group status. 616 * @param __HANDLE__ TSC Handle 617 * @param __GX_INDEX__ Group index 618 * @retval SET or RESET 619 */ 620 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ 621 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) 622 623 /** 624 * @} 625 */ 626 627 /* Private macros ------------------------------------------------------------*/ 628 629 /** @defgroup TSC_Private_Macros TSC Private Macros 630 * @{ 631 */ 632 633 #define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ 634 ((__VALUE__) == TSC_CTPH_2CYCLES) || \ 635 ((__VALUE__) == TSC_CTPH_3CYCLES) || \ 636 ((__VALUE__) == TSC_CTPH_4CYCLES) || \ 637 ((__VALUE__) == TSC_CTPH_5CYCLES) || \ 638 ((__VALUE__) == TSC_CTPH_6CYCLES) || \ 639 ((__VALUE__) == TSC_CTPH_7CYCLES) || \ 640 ((__VALUE__) == TSC_CTPH_8CYCLES) || \ 641 ((__VALUE__) == TSC_CTPH_9CYCLES) || \ 642 ((__VALUE__) == TSC_CTPH_10CYCLES) || \ 643 ((__VALUE__) == TSC_CTPH_11CYCLES) || \ 644 ((__VALUE__) == TSC_CTPH_12CYCLES) || \ 645 ((__VALUE__) == TSC_CTPH_13CYCLES) || \ 646 ((__VALUE__) == TSC_CTPH_14CYCLES) || \ 647 ((__VALUE__) == TSC_CTPH_15CYCLES) || \ 648 ((__VALUE__) == TSC_CTPH_16CYCLES)) 649 650 #define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ 651 ((__VALUE__) == TSC_CTPL_2CYCLES) || \ 652 ((__VALUE__) == TSC_CTPL_3CYCLES) || \ 653 ((__VALUE__) == TSC_CTPL_4CYCLES) || \ 654 ((__VALUE__) == TSC_CTPL_5CYCLES) || \ 655 ((__VALUE__) == TSC_CTPL_6CYCLES) || \ 656 ((__VALUE__) == TSC_CTPL_7CYCLES) || \ 657 ((__VALUE__) == TSC_CTPL_8CYCLES) || \ 658 ((__VALUE__) == TSC_CTPL_9CYCLES) || \ 659 ((__VALUE__) == TSC_CTPL_10CYCLES) || \ 660 ((__VALUE__) == TSC_CTPL_11CYCLES) || \ 661 ((__VALUE__) == TSC_CTPL_12CYCLES) || \ 662 ((__VALUE__) == TSC_CTPL_13CYCLES) || \ 663 ((__VALUE__) == TSC_CTPL_14CYCLES) || \ 664 ((__VALUE__) == TSC_CTPL_15CYCLES) || \ 665 ((__VALUE__) == TSC_CTPL_16CYCLES)) 666 667 #define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE)) 668 669 #define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) 670 671 #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) 672 673 #define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ 674 ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ 675 ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ 676 ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ 677 ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ 678 ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ 679 ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ 680 ((__VALUE__) == TSC_PG_PRESC_DIV128)) 681 682 #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ 683 ((__VALUE__) == TSC_MCV_511) || \ 684 ((__VALUE__) == TSC_MCV_1023) || \ 685 ((__VALUE__) == TSC_MCV_2047) || \ 686 ((__VALUE__) == TSC_MCV_4095) || \ 687 ((__VALUE__) == TSC_MCV_8191) || \ 688 ((__VALUE__) == TSC_MCV_16383)) 689 690 #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) 691 692 #define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING) || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) 693 694 #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) 695 696 #define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE)) 697 698 #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) 699 700 701 #define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \ 702 ((((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ 703 (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ 704 (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ 705 (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ 706 (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ 707 (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ 708 (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ 709 (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ 710 (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ 711 (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ 712 (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ 713 (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ 714 (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ 715 (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ 716 (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ 717 (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ 718 (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ 719 (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ 720 (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ 721 (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ 722 (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ 723 (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ 724 (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ 725 (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ 726 (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ 727 (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ 728 (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ 729 (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ 730 (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ 731 (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ 732 (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ 733 (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))) 734 735 /** 736 * @} 737 */ 738 739 /* Exported functions --------------------------------------------------------*/ 740 /** @addtogroup TSC_Exported_Functions 741 * @{ 742 */ 743 744 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions 745 * @{ 746 */ 747 /* Initialization and de-initialization functions *****************************/ 748 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); 749 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); 750 void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); 751 void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); 752 753 /* Callbacks Register/UnRegister functions ***********************************/ 754 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 755 HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback); 756 HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); 757 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 758 /** 759 * @} 760 */ 761 762 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions 763 * @{ 764 */ 765 /* IO operation functions *****************************************************/ 766 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); 767 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); 768 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); 769 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); 770 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); 771 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index); 772 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index); 773 /** 774 * @} 775 */ 776 777 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions 778 * @{ 779 */ 780 /* Peripheral Control functions ***********************************************/ 781 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config); 782 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice); 783 /** 784 * @} 785 */ 786 787 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions 788 * @{ 789 */ 790 /* Peripheral State and Error functions ***************************************/ 791 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); 792 /** 793 * @} 794 */ 795 796 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 797 * @{ 798 */ 799 /******* TSC IRQHandler and Callbacks used in Interrupt mode */ 800 void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); 801 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); 802 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); 803 /** 804 * @} 805 */ 806 807 /** 808 * @} 809 */ 810 811 /** 812 * @} 813 */ 814 815 /** 816 * @} 817 */ 818 819 #ifdef __cplusplus 820 } 821 #endif 822 823 #endif /* STM32L4xx_HAL_TSC_H */ 824 825 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 826