1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * This file contains the CSS-firmware specific definitions for the second 7 * generation platforms based on the N2/V2 CPU. 8 */ 9 10 #ifndef NRD_CSS_FW_DEF2_H 11 #define NRD_CSS_FW_DEF2_H 12 13 #include <nrd_css_def2.h> 14 15 /******************************************************************************* 16 * BL sizes 17 ******************************************************************************/ 18 19 #define NRD_CSS_BL1_RW_SIZE UL(64 * 1024) /* 64KB */ 20 21 #if TRUSTED_BOARD_BOOT 22 # define NRD_CSS_BL2_SIZE UL(0x20000) 23 #else 24 # define NRD_CSS_BL2_SIZE UL(0x14000) 25 #endif 26 /* 27 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 28 * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2 29 * and BL1-RW. NRD_BL31_SIZE - is tuned with respect to the actual BL31 30 * PROGBITS size which is around 64-68KB at the time this change is being made. 31 * A buffer of ~35KB is added to account for future expansion of the image, 32 * making it a total of 100KB. 33 */ 34 #define NRD_CSS_BL31_SIZE UL(116 * 1024) /* 116 KB */ 35 36 /******************************************************************************* 37 * Console config 38 ******************************************************************************/ 39 40 #define NRD_CSS_UART_CLK_IN_HZ UL(7372800) 41 42 /******************************************************************************* 43 * Watchdog config 44 ******************************************************************************/ 45 46 #define NRD_CSS_SECURE_WDOG_TIMEOUT UL(100) 47 48 /******************************************************************************* 49 * RAS config 50 ******************************************************************************/ 51 52 #define NRD_CSS_NS_RAM_ECC_CE_INT U(87) 53 #define NRD_CSS_NS_RAM_ECC_UE_INT U(88) 54 55 #if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) \ 56 && ENABLE_FEAT_RAS && FFH_SUPPORT 57 /* 58 * CPER buffer memory of 128KB is reserved and it is placed adjacent to the 59 * memory shared between EL3 and S-EL0. 60 */ 61 #define NRD_CSS_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 62 PLAT_SP_IMAGE_NS_BUF_SIZE) 63 #define NRD_CSS_SP_CPER_BUF_SIZE UL(0x10000) 64 #endif /* SPM_MM && ENABLE_FEAT_RAS && FFH_SUPPORT */ 65 66 /******************************************************************************* 67 * MMU mapping 68 ******************************************************************************/ 69 70 #define NRD_CSS_SHARED_RAM_MMAP(n) \ 71 MAP_REGION_FLAT( \ 72 NRD_REMOTE_CHIP_MEM_OFFSET(n) + \ 73 ARM_SHARED_RAM_BASE, \ 74 ARM_SHARED_RAM_SIZE, \ 75 MT_NON_CACHEABLE | MT_RW | MT_SECURE) 76 77 #define NRD_CSS_PERIPH_MMAP(n) \ 78 MAP_REGION_FLAT( \ 79 NRD_REMOTE_CHIP_MEM_OFFSET(n) + \ 80 NRD_CSS_PERIPH_BASE, \ 81 NRD_CSS_PERIPH_SIZE, \ 82 MT_DEVICE | MT_RW | MT_SECURE) 83 84 #if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) && \ 85 ENABLE_FEAT_RAS && FFH_SUPPORT 86 /* 87 * CPER buffer memory of 128KB is reserved and it is placed adjacent to the 88 * memory shared between EL3 and S-EL0. 89 */ 90 #define NRD_CSS_SP_CPER_BUF_MMAP \ 91 MAP_REGION2( \ 92 NRD_CSS_SP_CPER_BUF_BASE, \ 93 NRD_CSS_SP_CPER_BUF_BASE, \ 94 NRD_CSS_SP_CPER_BUF_SIZE, \ 95 MT_RW_DATA | MT_NS | MT_USER, \ 96 PAGE_SIZE) 97 #endif 98 99 #if SPM_MM 100 #define NRD_CSS_SECURE_UART_USER_MMAP \ 101 MAP_REGION_FLAT( \ 102 NRD_CSS_SEC_UART_BASE, \ 103 NRD_CSS_UART_SIZE, \ 104 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 105 #endif 106 107 #endif /* NRD_CSS_FW_DEF2_H */ 108