1 /*++ 2 3 Copyright (c) Microsoft Corporation. All rights reserved. 4 5 Module Name: 6 7 WinHvPlatformDefs.h 8 9 Abstract: 10 11 This module contains the constant, type and structure definitions for 12 the Windows Hypervisor User-Mode APIs. 13 14 --*/ 15 16 #ifndef _WINHVAPIDEFS_H_ 17 #define _WINHVAPIDEFS_H_ 18 19 #if defined(_MSC_VER) && (_MSC_VER >= 1200) 20 #pragma once 21 #pragma warning(push) 22 #pragma warning(disable:4201) /* nonstandard extension used: nameless struct/union */ 23 #pragma warning(disable:4214) /* nonstandard extension used: bit field types other than int */ 24 #endif 25 26 // 27 // Platform capabilities 28 // 29 typedef enum WHV_CAPABILITY_CODE 30 { 31 // Capabilities of the API implementation 32 WHvCapabilityCodeHypervisorPresent = 0x00000000, 33 WHvCapabilityCodeFeatures = 0x00000001, 34 WHvCapabilityCodeExtendedVmExits = 0x00000002, 35 WHvCapabilityCodeExceptionExitBitmap = 0x00000003, 36 WHvCapabilityCodeX64MsrExitBitmap = 0x00000004, 37 38 // Capabilities of the system's processor 39 WHvCapabilityCodeProcessorVendor = 0x00001000, 40 WHvCapabilityCodeProcessorFeatures = 0x00001001, 41 WHvCapabilityCodeProcessorClFlushSize = 0x00001002, 42 WHvCapabilityCodeProcessorXsaveFeatures = 0x00001003, 43 WHvCapabilityCodeProcessorClockFrequency = 0x00001004, 44 WHvCapabilityCodeInterruptClockFrequency = 0x00001005, 45 WHvCapabilityCodeProcessorFeaturesBanks = 0x00001006, 46 } WHV_CAPABILITY_CODE; 47 48 // 49 // Return values for WhvCapabilityCodeFeatures 50 // 51 typedef union WHV_CAPABILITY_FEATURES 52 { 53 struct 54 { 55 UINT64 PartialUnmap : 1; 56 UINT64 LocalApicEmulation : 1; 57 UINT64 Xsave : 1; 58 UINT64 DirtyPageTracking : 1; 59 UINT64 SpeculationControl : 1; 60 UINT64 ApicRemoteRead : 1; 61 UINT64 IdleSuspend : 1; 62 UINT64 Reserved : 57; 63 }; 64 65 UINT64 AsUINT64; 66 } WHV_CAPABILITY_FEATURES; 67 68 C_ASSERT(sizeof(WHV_CAPABILITY_FEATURES) == sizeof(UINT64)); 69 70 // 71 // Return values for WhvCapabilityCodeExtendedVmExits and input buffer for 72 // WHvPartitionPropertyCodeExtendedVmExits 73 // 74 typedef union WHV_EXTENDED_VM_EXITS 75 { 76 struct 77 { 78 UINT64 X64CpuidExit : 1; // WHvRunVpExitReasonX64CPUID supported 79 UINT64 X64MsrExit : 1; // WHvRunVpExitX64ReasonMSRAccess supported 80 UINT64 ExceptionExit : 1; // WHvRunVpExitReasonException supported 81 UINT64 X64RdtscExit : 1; // WHvRunVpExitReasonX64Rdtsc supported 82 UINT64 X64ApicSmiExitTrap : 1; // WHvRunVpExitReasonX64ApicSmiTrap supported 83 UINT64 HypercallExit : 1; // WHvRunVpExitReasonHypercall supported 84 UINT64 X64ApicInitSipiExitTrap : 1; // WHvRunVpExitReasonX64ApicInitSipiTrap supported 85 UINT64 Reserved : 57; 86 }; 87 88 UINT64 AsUINT64; 89 } WHV_EXTENDED_VM_EXITS; 90 91 C_ASSERT(sizeof(WHV_EXTENDED_VM_EXITS) == sizeof(UINT64)); 92 93 // 94 // Return values for WhvCapabilityCodeProcessorVendor 95 // 96 typedef enum WHV_PROCESSOR_VENDOR 97 { 98 WHvProcessorVendorAmd = 0x0000, 99 WHvProcessorVendorIntel = 0x0001, 100 WHvProcessorVendorHygon = 0x0002 101 102 } WHV_PROCESSOR_VENDOR; 103 104 // 105 // Return values for WhvCapabilityCodeProcessorFeatures and input buffer for 106 // WHvPartitionPropertyCodeProcessorFeatures. Additionally the value is embeded 107 // in WHV_PROCESSOR_FEATURES_BANKS. 108 // 109 typedef union WHV_PROCESSOR_FEATURES 110 { 111 struct 112 { 113 UINT64 Sse3Support : 1; 114 UINT64 LahfSahfSupport : 1; 115 UINT64 Ssse3Support : 1; 116 UINT64 Sse4_1Support : 1; 117 UINT64 Sse4_2Support : 1; 118 UINT64 Sse4aSupport : 1; 119 UINT64 XopSupport : 1; 120 UINT64 PopCntSupport : 1; 121 UINT64 Cmpxchg16bSupport : 1; 122 UINT64 Altmovcr8Support : 1; 123 UINT64 LzcntSupport : 1; 124 UINT64 MisAlignSseSupport : 1; 125 UINT64 MmxExtSupport : 1; 126 UINT64 Amd3DNowSupport : 1; 127 UINT64 ExtendedAmd3DNowSupport : 1; 128 UINT64 Page1GbSupport : 1; 129 UINT64 AesSupport : 1; 130 UINT64 PclmulqdqSupport : 1; 131 UINT64 PcidSupport : 1; 132 UINT64 Fma4Support : 1; 133 UINT64 F16CSupport : 1; 134 UINT64 RdRandSupport : 1; 135 UINT64 RdWrFsGsSupport : 1; 136 UINT64 SmepSupport : 1; 137 UINT64 EnhancedFastStringSupport : 1; 138 UINT64 Bmi1Support : 1; 139 UINT64 Bmi2Support : 1; 140 UINT64 Reserved1 : 2; 141 UINT64 MovbeSupport : 1; 142 UINT64 Npiep1Support : 1; 143 UINT64 DepX87FPUSaveSupport : 1; 144 UINT64 RdSeedSupport : 1; 145 UINT64 AdxSupport : 1; 146 UINT64 IntelPrefetchSupport : 1; 147 UINT64 SmapSupport : 1; 148 UINT64 HleSupport : 1; 149 UINT64 RtmSupport : 1; 150 UINT64 RdtscpSupport : 1; 151 UINT64 ClflushoptSupport : 1; 152 UINT64 ClwbSupport : 1; 153 UINT64 ShaSupport : 1; 154 UINT64 X87PointersSavedSupport : 1; 155 UINT64 InvpcidSupport : 1; 156 UINT64 IbrsSupport : 1; 157 UINT64 StibpSupport : 1; 158 UINT64 IbpbSupport : 1; 159 UINT64 Reserved2 : 1; 160 UINT64 SsbdSupport : 1; 161 UINT64 FastShortRepMovSupport : 1; 162 UINT64 Reserved3 : 1; 163 UINT64 RdclNo : 1; 164 UINT64 IbrsAllSupport : 1; 165 UINT64 Reserved4 : 1; 166 UINT64 SsbNo : 1; 167 UINT64 RsbANo : 1; 168 UINT64 Reserved5 : 1; 169 UINT64 RdPidSupport : 1; 170 UINT64 UmipSupport : 1; 171 UINT64 MdsNoSupport : 1; 172 UINT64 MdClearSupport : 1; 173 UINT64 Reserved6 : 3; 174 }; 175 176 UINT64 AsUINT64; 177 } WHV_PROCESSOR_FEATURES; 178 179 C_ASSERT(sizeof(WHV_PROCESSOR_FEATURES) == sizeof(UINT64)); 180 181 // 182 // Return values for WhvCapabilityCodeProcessorFeaturesBanks and input buffer 183 // for WHvPartitionPropertyCodeProcessorFeaturesBanks. BanksCount must be populated 184 // before calling WHP APIs. 185 // 186 typedef union WHV_PROCESSOR_FEATURES1 187 { 188 struct 189 { 190 UINT64 Reserved1 : 2; 191 UINT64 ClZeroSupport : 1; 192 UINT64 Reserved2 : 61; 193 }; 194 195 UINT64 AsUINT64; 196 } WHV_PROCESSOR_FEATURES1; 197 198 C_ASSERT(sizeof(WHV_PROCESSOR_FEATURES1) == sizeof(UINT64)); 199 200 #define WHV_PROCESSOR_FEATURES_BANKS_COUNT 2 201 202 typedef struct WHV_PROCESSOR_FEATURES_BANKS 203 { 204 UINT32 BanksCount; 205 UINT32 Reserved0; 206 union 207 { 208 struct 209 { 210 WHV_PROCESSOR_FEATURES Bank0; 211 WHV_PROCESSOR_FEATURES1 Bank1; 212 }; 213 214 UINT64 AsUINT64[WHV_PROCESSOR_FEATURES_BANKS_COUNT]; 215 }; 216 } WHV_PROCESSOR_FEATURES_BANKS; 217 218 C_ASSERT(sizeof(WHV_PROCESSOR_FEATURES_BANKS) == sizeof(UINT64) * (WHV_PROCESSOR_FEATURES_BANKS_COUNT + 1)); 219 220 // 221 // Return values for WHvCapabilityCodeProcessorXsaveFeatures and input buffer 222 // for WHvPartitionPropertyCodeProcessorXsaveFeatures 223 // 224 typedef union _WHV_PROCESSOR_XSAVE_FEATURES 225 { 226 struct 227 { 228 UINT64 XsaveSupport : 1; 229 UINT64 XsaveoptSupport : 1; 230 UINT64 AvxSupport : 1; 231 UINT64 Avx2Support : 1; 232 UINT64 FmaSupport : 1; 233 UINT64 MpxSupport : 1; 234 UINT64 Avx512Support : 1; 235 UINT64 Avx512DQSupport : 1; 236 UINT64 Avx512CDSupport : 1; 237 UINT64 Avx512BWSupport : 1; 238 UINT64 Avx512VLSupport : 1; 239 UINT64 XsaveCompSupport : 1; 240 UINT64 XsaveSupervisorSupport : 1; 241 UINT64 Xcr1Support : 1; 242 UINT64 Avx512BitalgSupport : 1; 243 UINT64 Avx512IfmaSupport : 1; 244 UINT64 Avx512VBmiSupport : 1; 245 UINT64 Avx512VBmi2Support : 1; 246 UINT64 Avx512VnniSupport : 1; 247 UINT64 GfniSupport : 1; 248 UINT64 VaesSupport : 1; 249 UINT64 Avx512VPopcntdqSupport : 1; 250 UINT64 VpclmulqdqSupport : 1; 251 UINT64 Avx512Bf16Support:1; 252 UINT64 Avx512Vp2IntersectSupport:1; 253 UINT64 Reserved : 39; 254 }; 255 256 UINT64 AsUINT64; 257 } WHV_PROCESSOR_XSAVE_FEATURES, *PWHV_PROCESSOR_XSAVE_FEATURES; 258 259 C_ASSERT(sizeof(WHV_PROCESSOR_XSAVE_FEATURES) == sizeof(UINT64)); 260 261 // 262 // Return value for WHvCapabilityCodeX64MsrExits and input buffer for 263 // WHvPartitionPropertyCodeX64MsrcExits 264 // 265 typedef union WHV_X64_MSR_EXIT_BITMAP 266 { 267 UINT64 AsUINT64; 268 struct 269 { 270 UINT64 UnhandledMsrs:1; 271 UINT64 TscMsrWrite:1; 272 UINT64 TscMsrRead:1; 273 UINT64 ApicBaseMsrWrite:1; 274 UINT64 Reserved:60; 275 }; 276 277 } WHV_X64_MSR_EXIT_BITMAP; 278 279 C_ASSERT(sizeof(WHV_X64_MSR_EXIT_BITMAP) == sizeof(UINT64)); 280 281 // 282 // WHvGetCapability output buffer 283 // 284 typedef union WHV_CAPABILITY 285 { 286 BOOL HypervisorPresent; 287 WHV_CAPABILITY_FEATURES Features; 288 WHV_EXTENDED_VM_EXITS ExtendedVmExits; 289 WHV_PROCESSOR_VENDOR ProcessorVendor; 290 WHV_PROCESSOR_FEATURES ProcessorFeatures; 291 WHV_PROCESSOR_XSAVE_FEATURES ProcessorXsaveFeatures; 292 UINT8 ProcessorClFlushSize; 293 UINT64 ExceptionExitBitmap; 294 WHV_X64_MSR_EXIT_BITMAP X64MsrExitBitmap; 295 UINT64 ProcessorClockFrequency; 296 UINT64 InterruptClockFrequency; 297 WHV_PROCESSOR_FEATURES_BANKS ProcessorFeaturesBanks; 298 } WHV_CAPABILITY; 299 300 // 301 // Partitions 302 // 303 304 typedef VOID* WHV_PARTITION_HANDLE; 305 306 typedef enum WHV_PARTITION_PROPERTY_CODE 307 { 308 WHvPartitionPropertyCodeExtendedVmExits = 0x00000001, 309 WHvPartitionPropertyCodeExceptionExitBitmap = 0x00000002, 310 WHvPartitionPropertyCodeSeparateSecurityDomain = 0x00000003, 311 // Nested virtualization support is experimental and not supported. 312 WHvPartitionPropertyCodeNestedVirtualization = 0x00000004, 313 WHvPartitionPropertyCodeX64MsrExitBitmap = 0x00000005, 314 315 WHvPartitionPropertyCodeProcessorFeatures = 0x00001001, 316 WHvPartitionPropertyCodeProcessorClFlushSize = 0x00001002, 317 WHvPartitionPropertyCodeCpuidExitList = 0x00001003, 318 WHvPartitionPropertyCodeCpuidResultList = 0x00001004, 319 WHvPartitionPropertyCodeLocalApicEmulationMode = 0x00001005, 320 WHvPartitionPropertyCodeProcessorXsaveFeatures = 0x00001006, 321 WHvPartitionPropertyCodeProcessorClockFrequency = 0x00001007, 322 WHvPartitionPropertyCodeInterruptClockFrequency = 0x00001008, 323 WHvPartitionPropertyCodeApicRemoteReadSupport = 0x00001009, 324 WHvPartitionPropertyCodeProcessorFeaturesBanks = 0x0000100A, 325 WHvPartitionPropertyCodeReferenceTime = 0x0000100B, 326 327 WHvPartitionPropertyCodeProcessorCount = 0x00001fff 328 } WHV_PARTITION_PROPERTY_CODE; 329 330 // 331 // WHvPartitionPropertyCodeCpuidResultList input buffer list element. 332 // 333 typedef struct WHV_X64_CPUID_RESULT 334 { 335 UINT32 Function; 336 UINT32 Reserved[3]; 337 UINT32 Eax; 338 UINT32 Ebx; 339 UINT32 Ecx; 340 UINT32 Edx; 341 } WHV_X64_CPUID_RESULT; 342 343 // 344 // WHvPartitionPropertyCodeExceptionBitmap enumeration values. 345 // 346 typedef enum WHV_EXCEPTION_TYPE 347 { 348 WHvX64ExceptionTypeDivideErrorFault = 0x0, 349 WHvX64ExceptionTypeDebugTrapOrFault = 0x1, 350 WHvX64ExceptionTypeBreakpointTrap = 0x3, 351 WHvX64ExceptionTypeOverflowTrap = 0x4, 352 WHvX64ExceptionTypeBoundRangeFault = 0x5, 353 WHvX64ExceptionTypeInvalidOpcodeFault = 0x6, 354 WHvX64ExceptionTypeDeviceNotAvailableFault = 0x7, 355 WHvX64ExceptionTypeDoubleFaultAbort = 0x8, 356 WHvX64ExceptionTypeInvalidTaskStateSegmentFault = 0x0A, 357 WHvX64ExceptionTypeSegmentNotPresentFault = 0x0B, 358 WHvX64ExceptionTypeStackFault = 0x0C, 359 WHvX64ExceptionTypeGeneralProtectionFault = 0x0D, 360 WHvX64ExceptionTypePageFault = 0x0E, 361 WHvX64ExceptionTypeFloatingPointErrorFault = 0x10, 362 WHvX64ExceptionTypeAlignmentCheckFault = 0x11, 363 WHvX64ExceptionTypeMachineCheckAbort = 0x12, 364 WHvX64ExceptionTypeSimdFloatingPointFault = 0x13, 365 } WHV_EXCEPTION_TYPE; 366 367 typedef enum WHV_X64_LOCAL_APIC_EMULATION_MODE 368 { 369 WHvX64LocalApicEmulationModeNone, 370 WHvX64LocalApicEmulationModeXApic, 371 WHvX64LocalApicEmulationModeX2Apic 372 } WHV_X64_LOCAL_APIC_EMULATION_MODE; 373 374 // 375 // WHvGetPartitionProperty output buffer / WHvSetPartitionProperty input buffer 376 // 377 typedef union WHV_PARTITION_PROPERTY 378 { 379 WHV_EXTENDED_VM_EXITS ExtendedVmExits; 380 WHV_PROCESSOR_FEATURES ProcessorFeatures; 381 WHV_PROCESSOR_XSAVE_FEATURES ProcessorXsaveFeatures; 382 UINT8 ProcessorClFlushSize; 383 UINT32 ProcessorCount; 384 UINT32 CpuidExitList[1]; 385 WHV_X64_CPUID_RESULT CpuidResultList[1]; 386 UINT64 ExceptionExitBitmap; 387 WHV_X64_LOCAL_APIC_EMULATION_MODE LocalApicEmulationMode; 388 BOOL SeparateSecurityDomain; 389 // Nested virtualization support is experimental and not supported. 390 BOOL NestedVirtualization; 391 WHV_X64_MSR_EXIT_BITMAP X64MsrExitBitmap; 392 UINT64 ProcessorClockFrequency; 393 UINT64 InterruptClockFrequency; 394 BOOL ApicRemoteRead; 395 WHV_PROCESSOR_FEATURES_BANKS ProcessorFeaturesBanks; 396 UINT64 ReferenceTime; 397 } WHV_PARTITION_PROPERTY; 398 399 // 400 // Memory Management 401 // 402 403 // 404 // Guest physical or virtual address 405 // 406 typedef UINT64 WHV_GUEST_PHYSICAL_ADDRESS; 407 typedef UINT64 WHV_GUEST_VIRTUAL_ADDRESS; 408 409 // 410 // Flags used by WHvMapGpaRange 411 // 412 typedef enum WHV_MAP_GPA_RANGE_FLAGS 413 { 414 WHvMapGpaRangeFlagNone = 0x00000000, 415 WHvMapGpaRangeFlagRead = 0x00000001, 416 WHvMapGpaRangeFlagWrite = 0x00000002, 417 WHvMapGpaRangeFlagExecute = 0x00000004, 418 WHvMapGpaRangeFlagTrackDirtyPages = 0x00000008, 419 } WHV_MAP_GPA_RANGE_FLAGS; 420 421 DEFINE_ENUM_FLAG_OPERATORS(WHV_MAP_GPA_RANGE_FLAGS); 422 423 // 424 // Flags used by WHvTranslateGva 425 // 426 typedef enum WHV_TRANSLATE_GVA_FLAGS 427 { 428 WHvTranslateGvaFlagNone = 0x00000000, 429 WHvTranslateGvaFlagValidateRead = 0x00000001, 430 WHvTranslateGvaFlagValidateWrite = 0x00000002, 431 WHvTranslateGvaFlagValidateExecute = 0x00000004, 432 WHvTranslateGvaFlagPrivilegeExempt = 0x00000008, 433 WHvTranslateGvaFlagSetPageTableBits = 0x00000010 434 } WHV_TRANSLATE_GVA_FLAGS; 435 436 DEFINE_ENUM_FLAG_OPERATORS(WHV_TRANSLATE_GVA_FLAGS); 437 438 // 439 // Result of an attempt to translate a guest virtual address 440 // 441 typedef enum WHV_TRANSLATE_GVA_RESULT_CODE 442 { 443 WHvTranslateGvaResultSuccess = 0, 444 445 // Translation failures 446 WHvTranslateGvaResultPageNotPresent = 1, 447 WHvTranslateGvaResultPrivilegeViolation = 2, 448 WHvTranslateGvaResultInvalidPageTableFlags = 3, 449 450 // GPA access failures 451 WHvTranslateGvaResultGpaUnmapped = 4, 452 WHvTranslateGvaResultGpaNoReadAccess = 5, 453 WHvTranslateGvaResultGpaNoWriteAccess = 6, 454 WHvTranslateGvaResultGpaIllegalOverlayAccess = 7, 455 WHvTranslateGvaResultIntercept = 8 456 } WHV_TRANSLATE_GVA_RESULT_CODE; 457 458 // 459 // Output buffer of WHvTranslateGva 460 // 461 typedef struct WHV_TRANSLATE_GVA_RESULT 462 { 463 WHV_TRANSLATE_GVA_RESULT_CODE ResultCode; 464 UINT32 Reserved; 465 } WHV_TRANSLATE_GVA_RESULT; 466 467 // 468 // Virtual Processor Register Definitions 469 // 470 typedef enum WHV_REGISTER_NAME 471 { 472 // X64 General purpose registers 473 WHvX64RegisterRax = 0x00000000, 474 WHvX64RegisterRcx = 0x00000001, 475 WHvX64RegisterRdx = 0x00000002, 476 WHvX64RegisterRbx = 0x00000003, 477 WHvX64RegisterRsp = 0x00000004, 478 WHvX64RegisterRbp = 0x00000005, 479 WHvX64RegisterRsi = 0x00000006, 480 WHvX64RegisterRdi = 0x00000007, 481 WHvX64RegisterR8 = 0x00000008, 482 WHvX64RegisterR9 = 0x00000009, 483 WHvX64RegisterR10 = 0x0000000A, 484 WHvX64RegisterR11 = 0x0000000B, 485 WHvX64RegisterR12 = 0x0000000C, 486 WHvX64RegisterR13 = 0x0000000D, 487 WHvX64RegisterR14 = 0x0000000E, 488 WHvX64RegisterR15 = 0x0000000F, 489 WHvX64RegisterRip = 0x00000010, 490 WHvX64RegisterRflags = 0x00000011, 491 492 // X64 Segment registers 493 WHvX64RegisterEs = 0x00000012, 494 WHvX64RegisterCs = 0x00000013, 495 WHvX64RegisterSs = 0x00000014, 496 WHvX64RegisterDs = 0x00000015, 497 WHvX64RegisterFs = 0x00000016, 498 WHvX64RegisterGs = 0x00000017, 499 WHvX64RegisterLdtr = 0x00000018, 500 WHvX64RegisterTr = 0x00000019, 501 502 // X64 Table registers 503 WHvX64RegisterIdtr = 0x0000001A, 504 WHvX64RegisterGdtr = 0x0000001B, 505 506 // X64 Control Registers 507 WHvX64RegisterCr0 = 0x0000001C, 508 WHvX64RegisterCr2 = 0x0000001D, 509 WHvX64RegisterCr3 = 0x0000001E, 510 WHvX64RegisterCr4 = 0x0000001F, 511 WHvX64RegisterCr8 = 0x00000020, 512 513 // X64 Debug Registers 514 WHvX64RegisterDr0 = 0x00000021, 515 WHvX64RegisterDr1 = 0x00000022, 516 WHvX64RegisterDr2 = 0x00000023, 517 WHvX64RegisterDr3 = 0x00000024, 518 WHvX64RegisterDr6 = 0x00000025, 519 WHvX64RegisterDr7 = 0x00000026, 520 521 // X64 Extended Control Registers 522 WHvX64RegisterXCr0 = 0x00000027, 523 524 // X64 Floating Point and Vector Registers 525 WHvX64RegisterXmm0 = 0x00001000, 526 WHvX64RegisterXmm1 = 0x00001001, 527 WHvX64RegisterXmm2 = 0x00001002, 528 WHvX64RegisterXmm3 = 0x00001003, 529 WHvX64RegisterXmm4 = 0x00001004, 530 WHvX64RegisterXmm5 = 0x00001005, 531 WHvX64RegisterXmm6 = 0x00001006, 532 WHvX64RegisterXmm7 = 0x00001007, 533 WHvX64RegisterXmm8 = 0x00001008, 534 WHvX64RegisterXmm9 = 0x00001009, 535 WHvX64RegisterXmm10 = 0x0000100A, 536 WHvX64RegisterXmm11 = 0x0000100B, 537 WHvX64RegisterXmm12 = 0x0000100C, 538 WHvX64RegisterXmm13 = 0x0000100D, 539 WHvX64RegisterXmm14 = 0x0000100E, 540 WHvX64RegisterXmm15 = 0x0000100F, 541 WHvX64RegisterFpMmx0 = 0x00001010, 542 WHvX64RegisterFpMmx1 = 0x00001011, 543 WHvX64RegisterFpMmx2 = 0x00001012, 544 WHvX64RegisterFpMmx3 = 0x00001013, 545 WHvX64RegisterFpMmx4 = 0x00001014, 546 WHvX64RegisterFpMmx5 = 0x00001015, 547 WHvX64RegisterFpMmx6 = 0x00001016, 548 WHvX64RegisterFpMmx7 = 0x00001017, 549 WHvX64RegisterFpControlStatus = 0x00001018, 550 WHvX64RegisterXmmControlStatus = 0x00001019, 551 552 // X64 MSRs 553 WHvX64RegisterTsc = 0x00002000, 554 WHvX64RegisterEfer = 0x00002001, 555 WHvX64RegisterKernelGsBase = 0x00002002, 556 WHvX64RegisterApicBase = 0x00002003, 557 WHvX64RegisterPat = 0x00002004, 558 WHvX64RegisterSysenterCs = 0x00002005, 559 WHvX64RegisterSysenterEip = 0x00002006, 560 WHvX64RegisterSysenterEsp = 0x00002007, 561 WHvX64RegisterStar = 0x00002008, 562 WHvX64RegisterLstar = 0x00002009, 563 WHvX64RegisterCstar = 0x0000200A, 564 WHvX64RegisterSfmask = 0x0000200B, 565 WHvX64RegisterInitialApicId = 0x0000200C, 566 567 WHvX64RegisterMsrMtrrCap = 0x0000200D, 568 WHvX64RegisterMsrMtrrDefType = 0x0000200E, 569 570 WHvX64RegisterMsrMtrrPhysBase0 = 0x00002010, 571 WHvX64RegisterMsrMtrrPhysBase1 = 0x00002011, 572 WHvX64RegisterMsrMtrrPhysBase2 = 0x00002012, 573 WHvX64RegisterMsrMtrrPhysBase3 = 0x00002013, 574 WHvX64RegisterMsrMtrrPhysBase4 = 0x00002014, 575 WHvX64RegisterMsrMtrrPhysBase5 = 0x00002015, 576 WHvX64RegisterMsrMtrrPhysBase6 = 0x00002016, 577 WHvX64RegisterMsrMtrrPhysBase7 = 0x00002017, 578 WHvX64RegisterMsrMtrrPhysBase8 = 0x00002018, 579 WHvX64RegisterMsrMtrrPhysBase9 = 0x00002019, 580 WHvX64RegisterMsrMtrrPhysBaseA = 0x0000201A, 581 WHvX64RegisterMsrMtrrPhysBaseB = 0x0000201B, 582 WHvX64RegisterMsrMtrrPhysBaseC = 0x0000201C, 583 WHvX64RegisterMsrMtrrPhysBaseD = 0x0000201D, 584 WHvX64RegisterMsrMtrrPhysBaseE = 0x0000201E, 585 WHvX64RegisterMsrMtrrPhysBaseF = 0x0000201F, 586 587 WHvX64RegisterMsrMtrrPhysMask0 = 0x00002040, 588 WHvX64RegisterMsrMtrrPhysMask1 = 0x00002041, 589 WHvX64RegisterMsrMtrrPhysMask2 = 0x00002042, 590 WHvX64RegisterMsrMtrrPhysMask3 = 0x00002043, 591 WHvX64RegisterMsrMtrrPhysMask4 = 0x00002044, 592 WHvX64RegisterMsrMtrrPhysMask5 = 0x00002045, 593 WHvX64RegisterMsrMtrrPhysMask6 = 0x00002046, 594 WHvX64RegisterMsrMtrrPhysMask7 = 0x00002047, 595 WHvX64RegisterMsrMtrrPhysMask8 = 0x00002048, 596 WHvX64RegisterMsrMtrrPhysMask9 = 0x00002049, 597 WHvX64RegisterMsrMtrrPhysMaskA = 0x0000204A, 598 WHvX64RegisterMsrMtrrPhysMaskB = 0x0000204B, 599 WHvX64RegisterMsrMtrrPhysMaskC = 0x0000204C, 600 WHvX64RegisterMsrMtrrPhysMaskD = 0x0000204D, 601 WHvX64RegisterMsrMtrrPhysMaskE = 0x0000204E, 602 WHvX64RegisterMsrMtrrPhysMaskF = 0x0000204F, 603 604 WHvX64RegisterMsrMtrrFix64k00000 = 0x00002070, 605 WHvX64RegisterMsrMtrrFix16k80000 = 0x00002071, 606 WHvX64RegisterMsrMtrrFix16kA0000 = 0x00002072, 607 WHvX64RegisterMsrMtrrFix4kC0000 = 0x00002073, 608 WHvX64RegisterMsrMtrrFix4kC8000 = 0x00002074, 609 WHvX64RegisterMsrMtrrFix4kD0000 = 0x00002075, 610 WHvX64RegisterMsrMtrrFix4kD8000 = 0x00002076, 611 WHvX64RegisterMsrMtrrFix4kE0000 = 0x00002077, 612 WHvX64RegisterMsrMtrrFix4kE8000 = 0x00002078, 613 WHvX64RegisterMsrMtrrFix4kF0000 = 0x00002079, 614 WHvX64RegisterMsrMtrrFix4kF8000 = 0x0000207A, 615 616 WHvX64RegisterTscAux = 0x0000207B, 617 WHvX64RegisterSpecCtrl = 0x00002084, 618 WHvX64RegisterPredCmd = 0x00002085, 619 WHvX64RegisterTscVirtualOffset = 0x00002087, 620 621 // APIC state (also accessible via WHv(Get/Set)VirtualProcessorInterruptControllerState) 622 WHvX64RegisterApicId = 0x00003002, 623 WHvX64RegisterApicVersion = 0x00003003, 624 625 // Interrupt / Event Registers 626 WHvRegisterPendingInterruption = 0x80000000, 627 WHvRegisterInterruptState = 0x80000001, 628 WHvRegisterPendingEvent = 0x80000002, 629 WHvX64RegisterDeliverabilityNotifications = 0x80000004, 630 WHvRegisterInternalActivityState = 0x80000005, 631 WHvX64RegisterPendingDebugException = 0x80000006, 632 633 } WHV_REGISTER_NAME; 634 635 typedef union DECLSPEC_ALIGN(16) WHV_UINT128 636 { 637 struct 638 { 639 UINT64 Low64; 640 UINT64 High64; 641 }; 642 643 UINT32 Dword[4]; 644 } WHV_UINT128; 645 646 typedef union WHV_X64_FP_REGISTER 647 { 648 struct 649 { 650 UINT64 Mantissa; 651 UINT64 BiasedExponent:15; 652 UINT64 Sign:1; 653 UINT64 Reserved:48; 654 }; 655 656 WHV_UINT128 AsUINT128; 657 } WHV_X64_FP_REGISTER; 658 659 typedef union WHV_X64_FP_CONTROL_STATUS_REGISTER 660 { 661 struct 662 { 663 UINT16 FpControl; 664 UINT16 FpStatus; 665 UINT8 FpTag; 666 UINT8 Reserved; 667 UINT16 LastFpOp; 668 union 669 { 670 // Long Mode 671 UINT64 LastFpRip; 672 673 // 32 Bit Mode 674 struct 675 { 676 UINT32 LastFpEip; 677 UINT16 LastFpCs; 678 UINT16 Reserved2; 679 }; 680 }; 681 }; 682 683 WHV_UINT128 AsUINT128; 684 } WHV_X64_FP_CONTROL_STATUS_REGISTER; 685 686 typedef union WHV_X64_XMM_CONTROL_STATUS_REGISTER 687 { 688 struct 689 { 690 union 691 { 692 // Long Mode 693 UINT64 LastFpRdp; 694 695 // 32 Bit Mode 696 struct 697 { 698 UINT32 LastFpDp; 699 UINT16 LastFpDs; 700 UINT16 Reserved; 701 }; 702 }; 703 UINT32 XmmStatusControl; 704 UINT32 XmmStatusControlMask; 705 }; 706 707 WHV_UINT128 AsUINT128; 708 } WHV_X64_XMM_CONTROL_STATUS_REGISTER; 709 710 typedef struct WHV_X64_SEGMENT_REGISTER 711 { 712 UINT64 Base; 713 UINT32 Limit; 714 UINT16 Selector; 715 716 union 717 { 718 struct 719 { 720 UINT16 SegmentType:4; 721 UINT16 NonSystemSegment:1; 722 UINT16 DescriptorPrivilegeLevel:2; 723 UINT16 Present:1; 724 UINT16 Reserved:4; 725 UINT16 Available:1; 726 UINT16 Long:1; 727 UINT16 Default:1; 728 UINT16 Granularity:1; 729 }; 730 731 UINT16 Attributes; 732 }; 733 } WHV_X64_SEGMENT_REGISTER; 734 735 typedef struct WHV_X64_TABLE_REGISTER 736 { 737 UINT16 Pad[3]; 738 UINT16 Limit; 739 UINT64 Base; 740 } WHV_X64_TABLE_REGISTER; 741 742 typedef union WHV_X64_INTERRUPT_STATE_REGISTER 743 { 744 struct 745 { 746 UINT64 InterruptShadow:1; 747 UINT64 NmiMasked:1; 748 UINT64 Reserved:62; 749 }; 750 751 UINT64 AsUINT64; 752 } WHV_X64_INTERRUPT_STATE_REGISTER; 753 754 typedef union WHV_X64_PENDING_INTERRUPTION_REGISTER 755 { 756 struct 757 { 758 UINT32 InterruptionPending:1; 759 UINT32 InterruptionType:3; // WHV_X64_PENDING_INTERRUPTION_TYPE 760 UINT32 DeliverErrorCode:1; 761 UINT32 InstructionLength:4; 762 UINT32 NestedEvent:1; 763 UINT32 Reserved:6; 764 UINT32 InterruptionVector:16; 765 UINT32 ErrorCode; 766 }; 767 768 UINT64 AsUINT64; 769 } WHV_X64_PENDING_INTERRUPTION_REGISTER; 770 771 C_ASSERT(sizeof(WHV_X64_PENDING_INTERRUPTION_REGISTER) == sizeof(UINT64)); 772 773 typedef union WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER 774 { 775 struct 776 { 777 UINT64 NmiNotification:1; 778 UINT64 InterruptNotification:1; 779 UINT64 InterruptPriority:4; 780 UINT64 Reserved:58; 781 }; 782 783 UINT64 AsUINT64; 784 } WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER; 785 786 C_ASSERT(sizeof(WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) == sizeof(UINT64)); 787 788 789 typedef enum WHV_X64_PENDING_EVENT_TYPE 790 { 791 WHvX64PendingEventException = 0, 792 WHvX64PendingEventExtInt = 5, 793 } WHV_X64_PENDING_EVENT_TYPE; 794 795 typedef union WHV_X64_PENDING_EXCEPTION_EVENT 796 { 797 struct 798 { 799 UINT32 EventPending : 1; 800 UINT32 EventType : 3; // Must be WHvX64PendingEventException 801 UINT32 Reserved0 : 4; 802 803 UINT32 DeliverErrorCode : 1; 804 UINT32 Reserved1 : 7; 805 UINT32 Vector : 16; 806 UINT32 ErrorCode; 807 UINT64 ExceptionParameter; 808 }; 809 810 WHV_UINT128 AsUINT128; 811 } WHV_X64_PENDING_EXCEPTION_EVENT; 812 813 C_ASSERT(sizeof(WHV_X64_PENDING_EXCEPTION_EVENT) == sizeof(WHV_UINT128)); 814 815 typedef union WHV_X64_PENDING_EXT_INT_EVENT 816 { 817 struct 818 { 819 UINT64 EventPending : 1; 820 UINT64 EventType : 3; // Must be WHvX64PendingEventExtInt 821 UINT64 Reserved0 : 4; 822 UINT64 Vector : 8; 823 UINT64 Reserved1 : 48; 824 825 UINT64 Reserved2; 826 }; 827 828 WHV_UINT128 AsUINT128; 829 } WHV_X64_PENDING_EXT_INT_EVENT; 830 831 C_ASSERT(sizeof(WHV_X64_PENDING_EXT_INT_EVENT) == sizeof(WHV_UINT128)); 832 833 typedef union WHV_INTERNAL_ACTIVITY_REGISTER 834 { 835 struct 836 { 837 UINT64 StartupSuspend : 1; 838 UINT64 HaltSuspend : 1; 839 UINT64 IdleSuspend : 1; 840 UINT64 Reserved:61; 841 }; 842 843 UINT64 AsUINT64; 844 } WHV_INTERNAL_ACTIVITY_REGISTER; 845 846 C_ASSERT(sizeof(WHV_INTERNAL_ACTIVITY_REGISTER) == sizeof(UINT64)); 847 848 typedef union WHV_X64_PENDING_DEBUG_EXCEPTION 849 { 850 UINT64 AsUINT64; 851 852 struct 853 { 854 UINT64 Breakpoint0 : 1; 855 UINT64 Breakpoint1 : 1; 856 UINT64 Breakpoint2 : 1; 857 UINT64 Breakpoint3 : 1; 858 UINT64 SingleStep : 1; 859 UINT64 Reserved0 : 59; 860 }; 861 862 } WHV_X64_PENDING_DEBUG_EXCEPTION; 863 864 C_ASSERT(sizeof(WHV_X64_PENDING_DEBUG_EXCEPTION) == sizeof(UINT64)); 865 866 // 867 // Register values 868 // 869 typedef union WHV_REGISTER_VALUE 870 { 871 WHV_UINT128 Reg128; 872 UINT64 Reg64; 873 UINT32 Reg32; 874 UINT16 Reg16; 875 UINT8 Reg8; 876 WHV_X64_FP_REGISTER Fp; 877 WHV_X64_FP_CONTROL_STATUS_REGISTER FpControlStatus; 878 WHV_X64_XMM_CONTROL_STATUS_REGISTER XmmControlStatus; 879 WHV_X64_SEGMENT_REGISTER Segment; 880 WHV_X64_TABLE_REGISTER Table; 881 WHV_X64_INTERRUPT_STATE_REGISTER InterruptState; 882 WHV_X64_PENDING_INTERRUPTION_REGISTER PendingInterruption; 883 WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER DeliverabilityNotifications; 884 WHV_X64_PENDING_EXCEPTION_EVENT ExceptionEvent; 885 WHV_X64_PENDING_EXT_INT_EVENT ExtIntEvent; 886 WHV_INTERNAL_ACTIVITY_REGISTER InternalActivity; 887 WHV_X64_PENDING_DEBUG_EXCEPTION PendingDebugException; 888 } WHV_REGISTER_VALUE; 889 890 // 891 // Virtual Processor Execution 892 // 893 894 // 895 // Reason for a VM exit 896 // 897 typedef enum WHV_RUN_VP_EXIT_REASON 898 { 899 WHvRunVpExitReasonNone = 0x00000000, 900 901 // Standard exits caused by operations of the virtual processor 902 WHvRunVpExitReasonMemoryAccess = 0x00000001, 903 WHvRunVpExitReasonX64IoPortAccess = 0x00000002, 904 WHvRunVpExitReasonUnrecoverableException = 0x00000004, 905 WHvRunVpExitReasonInvalidVpRegisterValue = 0x00000005, 906 WHvRunVpExitReasonUnsupportedFeature = 0x00000006, 907 WHvRunVpExitReasonX64InterruptWindow = 0x00000007, 908 WHvRunVpExitReasonX64Halt = 0x00000008, 909 WHvRunVpExitReasonX64ApicEoi = 0x00000009, 910 911 // Additional exits that can be configured through partition properties 912 WHvRunVpExitReasonX64MsrAccess = 0x00001000, 913 WHvRunVpExitReasonX64Cpuid = 0x00001001, 914 WHvRunVpExitReasonException = 0x00001002, 915 WHvRunVpExitReasonX64Rdtsc = 0x00001003, 916 WHvRunVpExitReasonX64ApicSmiTrap = 0x00001004, 917 WHvRunVpExitReasonHypercall = 0x00001005, 918 WHvRunVpExitReasonX64ApicInitSipiTrap = 0x00001006, 919 920 // Exits caused by the host 921 WHvRunVpExitReasonCanceled = 0x00002001, 922 } WHV_RUN_VP_EXIT_REASON; 923 924 // 925 // Execution state of the virtual processor 926 // 927 typedef union WHV_X64_VP_EXECUTION_STATE 928 { 929 struct 930 { 931 UINT16 Cpl : 2; 932 UINT16 Cr0Pe : 1; 933 UINT16 Cr0Am : 1; 934 UINT16 EferLma : 1; 935 UINT16 DebugActive : 1; 936 UINT16 InterruptionPending : 1; 937 UINT16 Reserved0 : 5; 938 UINT16 InterruptShadow : 1; 939 UINT16 Reserved1 : 3; 940 }; 941 942 UINT16 AsUINT16; 943 } WHV_X64_VP_EXECUTION_STATE; 944 945 C_ASSERT(sizeof(WHV_X64_VP_EXECUTION_STATE) == sizeof(UINT16)); 946 947 // 948 // Execution context of a virtual processor at the time of an exit 949 // 950 typedef struct WHV_VP_EXIT_CONTEXT 951 { 952 WHV_X64_VP_EXECUTION_STATE ExecutionState; 953 UINT8 InstructionLength : 4; 954 UINT8 Cr8 : 4; 955 UINT8 Reserved; 956 UINT32 Reserved2; 957 WHV_X64_SEGMENT_REGISTER Cs; 958 UINT64 Rip; 959 UINT64 Rflags; 960 } WHV_VP_EXIT_CONTEXT; 961 962 // 963 // Context data for a VM exit caused by a memory access (WHvRunVpExitReasonMemoryAccess) 964 // 965 typedef enum WHV_MEMORY_ACCESS_TYPE 966 { 967 WHvMemoryAccessRead = 0, 968 WHvMemoryAccessWrite = 1, 969 WHvMemoryAccessExecute = 2 970 } WHV_MEMORY_ACCESS_TYPE; 971 972 typedef union WHV_MEMORY_ACCESS_INFO 973 { 974 struct { 975 UINT32 AccessType : 2; // WHV_MEMORY_ACCESS_TYPE 976 UINT32 GpaUnmapped : 1; 977 UINT32 GvaValid : 1; 978 UINT32 Reserved : 28; 979 }; 980 981 UINT32 AsUINT32; 982 } WHV_MEMORY_ACCESS_INFO; 983 984 typedef struct WHV_MEMORY_ACCESS_CONTEXT 985 { 986 // Context of the virtual processor 987 UINT8 InstructionByteCount; 988 UINT8 Reserved[3]; 989 UINT8 InstructionBytes[16]; 990 991 // Memory access info 992 WHV_MEMORY_ACCESS_INFO AccessInfo; 993 WHV_GUEST_PHYSICAL_ADDRESS Gpa; 994 WHV_GUEST_VIRTUAL_ADDRESS Gva; 995 } WHV_MEMORY_ACCESS_CONTEXT; 996 997 // 998 // Context data for an exit caused by an I/O port access (WHvRunVpExitReasonX64IOPortAccess) 999 // 1000 typedef union WHV_X64_IO_PORT_ACCESS_INFO 1001 { 1002 struct 1003 { 1004 UINT32 IsWrite : 1; 1005 UINT32 AccessSize: 3; 1006 UINT32 StringOp : 1; 1007 UINT32 RepPrefix : 1; 1008 UINT32 Reserved : 26; 1009 }; 1010 1011 UINT32 AsUINT32; 1012 } WHV_X64_IO_PORT_ACCESS_INFO; 1013 1014 C_ASSERT(sizeof(WHV_X64_IO_PORT_ACCESS_INFO) == sizeof(UINT32)); 1015 1016 typedef struct WHV_X64_IO_PORT_ACCESS_CONTEXT 1017 { 1018 // Context of the virtual processor 1019 UINT8 InstructionByteCount; 1020 UINT8 Reserved[3]; 1021 UINT8 InstructionBytes[16]; 1022 1023 // I/O port access info 1024 WHV_X64_IO_PORT_ACCESS_INFO AccessInfo; 1025 UINT16 PortNumber; 1026 UINT16 Reserved2[3]; 1027 UINT64 Rax; 1028 UINT64 Rcx; 1029 UINT64 Rsi; 1030 UINT64 Rdi; 1031 WHV_X64_SEGMENT_REGISTER Ds; 1032 WHV_X64_SEGMENT_REGISTER Es; 1033 } WHV_X64_IO_PORT_ACCESS_CONTEXT; 1034 1035 // 1036 // Context data for an exit caused by an MSR access (WHvRunVpExitReasonX64MSRAccess) 1037 // 1038 typedef union WHV_X64_MSR_ACCESS_INFO 1039 { 1040 struct 1041 { 1042 UINT32 IsWrite : 1; 1043 UINT32 Reserved : 31; 1044 }; 1045 1046 UINT32 AsUINT32; 1047 } WHV_X64_MSR_ACCESS_INFO; 1048 1049 C_ASSERT(sizeof(WHV_X64_MSR_ACCESS_INFO) == sizeof(UINT32)); 1050 1051 typedef struct WHV_X64_MSR_ACCESS_CONTEXT 1052 { 1053 // MSR access info 1054 WHV_X64_MSR_ACCESS_INFO AccessInfo; 1055 UINT32 MsrNumber; 1056 UINT64 Rax; 1057 UINT64 Rdx; 1058 } WHV_X64_MSR_ACCESS_CONTEXT; 1059 1060 // 1061 // Context data for an exit caused by a CPUID call (WHvRunVpExitReasonX64CPUID) 1062 // 1063 typedef struct WHV_X64_CPUID_ACCESS_CONTEXT 1064 { 1065 // CPUID access info 1066 UINT64 Rax; 1067 UINT64 Rcx; 1068 UINT64 Rdx; 1069 UINT64 Rbx; 1070 UINT64 DefaultResultRax; 1071 UINT64 DefaultResultRcx; 1072 UINT64 DefaultResultRdx; 1073 UINT64 DefaultResultRbx; 1074 } WHV_X64_CPUID_ACCESS_CONTEXT; 1075 1076 // 1077 // Context data for an exit caused by an exception generated by the virtual processor 1078 // (WHvRunVpExitReasonException) 1079 // 1080 typedef union WHV_VP_EXCEPTION_INFO 1081 { 1082 struct 1083 { 1084 UINT32 ErrorCodeValid : 1; 1085 UINT32 SoftwareException : 1; 1086 UINT32 Reserved : 30; 1087 }; 1088 1089 UINT32 AsUINT32; 1090 } WHV_VP_EXCEPTION_INFO; 1091 1092 C_ASSERT(sizeof(WHV_VP_EXCEPTION_INFO) == sizeof(UINT32)); 1093 1094 typedef struct WHV_VP_EXCEPTION_CONTEXT 1095 { 1096 UINT8 InstructionByteCount; 1097 UINT8 Reserved[3]; 1098 UINT8 InstructionBytes[16]; 1099 1100 // Exception info 1101 WHV_VP_EXCEPTION_INFO ExceptionInfo; 1102 UINT8 ExceptionType; // WHV_EXCEPTION_TYPE 1103 UINT8 Reserved2[3]; 1104 UINT32 ErrorCode; 1105 UINT64 ExceptionParameter; 1106 } WHV_VP_EXCEPTION_CONTEXT; 1107 1108 // 1109 // Context data for an exit caused by the use of an unsupported processor feature 1110 // (WHvRunVpExitReasonUnsupportedFeature) 1111 // 1112 typedef enum WHV_X64_UNSUPPORTED_FEATURE_CODE 1113 { 1114 WHvUnsupportedFeatureIntercept = 1, 1115 WHvUnsupportedFeatureTaskSwitchTss = 2 1116 } WHV_X64_UNSUPPORTED_FEATURE_CODE; 1117 1118 typedef struct WHV_X64_UNSUPPORTED_FEATURE_CONTEXT 1119 { 1120 WHV_X64_UNSUPPORTED_FEATURE_CODE FeatureCode; 1121 UINT32 Reserved; 1122 UINT64 FeatureParameter; 1123 } WHV_X64_UNSUPPORTED_FEATURE_CONTEXT; 1124 1125 // 1126 // Context data for an exit caused by a cancellation from the host (WHvRunVpExitReasonCanceled) 1127 // 1128 typedef enum WHV_RUN_VP_CANCEL_REASON 1129 { 1130 WHvRunVpCancelReasonUser = 0 // Execution canceled by WHvCancelRunVirtualProcessor 1131 } WHV_RUN_VP_CANCEL_REASON; 1132 1133 // 1134 // Alias for non-standard capitalization found in earlier versions of the header 1135 // 1136 #define WhvRunVpCancelReasonUser WHvRunVpCancelReasonUser 1137 1138 typedef struct WHV_RUN_VP_CANCELED_CONTEXT 1139 { 1140 WHV_RUN_VP_CANCEL_REASON CancelReason; 1141 } WHV_RUN_VP_CANCELED_CONTEXT; 1142 1143 // 1144 // Context data for an exit caused by an interrupt delivery window cancellation from the host 1145 // (WHvRunVpExitReasonX64InterruptWindow) 1146 // 1147 typedef enum WHV_X64_PENDING_INTERRUPTION_TYPE 1148 { 1149 WHvX64PendingInterrupt = 0, 1150 WHvX64PendingNmi = 2, 1151 WHvX64PendingException = 3 1152 } WHV_X64_PENDING_INTERRUPTION_TYPE, *PWHV_X64_PENDING_INTERRUPTION_TYPE; 1153 1154 typedef struct WHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT 1155 { 1156 WHV_X64_PENDING_INTERRUPTION_TYPE DeliverableType; 1157 } WHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT, *PWHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT; 1158 1159 // 1160 // Context data for an exit caused by an APIC EOI of a level-triggered 1161 // interrupt (WHvRunVpExitReasonX64ApicEoi) 1162 // 1163 typedef struct WHV_X64_APIC_EOI_CONTEXT 1164 { 1165 UINT32 InterruptVector; 1166 } WHV_X64_APIC_EOI_CONTEXT; 1167 1168 // 1169 // Context data for an exit caused by a rdtsc(p) instruction (WHvRunVpExitReasonX64Rdtsc) 1170 // 1171 typedef union WHV_X64_RDTSC_INFO 1172 { 1173 struct 1174 { 1175 UINT64 IsRdtscp:1; 1176 UINT64 Reserved:63; 1177 }; 1178 1179 UINT64 AsUINT64; 1180 } WHV_X64_RDTSC_INFO; 1181 1182 typedef struct WHV_X64_RDTSC_CONTEXT 1183 { 1184 UINT64 TscAux; 1185 UINT64 VirtualOffset; 1186 UINT64 Tsc; 1187 UINT64 ReferenceTime; 1188 WHV_X64_RDTSC_INFO RdtscInfo; 1189 } WHV_X64_RDTSC_CONTEXT; 1190 1191 // 1192 // Context data for an exit caused by an APIC SMI (WHvRunVpExitReasonX64ApicSmiTrap) 1193 // 1194 typedef struct WHV_X64_APIC_SMI_CONTEXT 1195 { 1196 UINT64 ApicIcr; 1197 } WHV_X64_APIC_SMI_CONTEXT; 1198 1199 // 1200 // Context data for an exit caused by a hypercall (WHvRunVpExitReasonHypercall) 1201 // 1202 1203 #define WHV_HYPERCALL_CONTEXT_MAX_XMM_REGISTERS 6 1204 1205 typedef struct _WHV_HYPERCALL_CONTEXT 1206 { 1207 UINT64 Rax; 1208 UINT64 Rbx; 1209 UINT64 Rcx; 1210 UINT64 Rdx; 1211 UINT64 R8; 1212 UINT64 Rsi; 1213 UINT64 Rdi; 1214 UINT64 Reserved0; 1215 WHV_UINT128 XmmRegisters[WHV_HYPERCALL_CONTEXT_MAX_XMM_REGISTERS]; 1216 UINT64 Reserved1[2]; 1217 } WHV_HYPERCALL_CONTEXT, *PWHV_HYPERCALL_CONTEXT; 1218 1219 // 1220 // Context data for an exit caused by an APIC INIT SIPI (WHvRunVpExitReasonX64ApicInitSipiTrap) 1221 // 1222 typedef struct WHV_X64_APIC_INIT_SIPI_CONTEXT 1223 { 1224 UINT64 ApicIcr; 1225 } WHV_X64_APIC_INIT_SIPI_CONTEXT; 1226 1227 // WHvRunVirtualProcessor output buffer 1228 typedef struct WHV_RUN_VP_EXIT_CONTEXT 1229 { 1230 WHV_RUN_VP_EXIT_REASON ExitReason; 1231 UINT32 Reserved; 1232 WHV_VP_EXIT_CONTEXT VpContext; 1233 1234 union 1235 { 1236 WHV_MEMORY_ACCESS_CONTEXT MemoryAccess; 1237 WHV_X64_IO_PORT_ACCESS_CONTEXT IoPortAccess; 1238 WHV_X64_MSR_ACCESS_CONTEXT MsrAccess; 1239 WHV_X64_CPUID_ACCESS_CONTEXT CpuidAccess; 1240 WHV_VP_EXCEPTION_CONTEXT VpException; 1241 WHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT InterruptWindow; 1242 WHV_X64_UNSUPPORTED_FEATURE_CONTEXT UnsupportedFeature; 1243 WHV_RUN_VP_CANCELED_CONTEXT CancelReason; 1244 WHV_X64_APIC_EOI_CONTEXT ApicEoi; 1245 WHV_X64_RDTSC_CONTEXT ReadTsc; 1246 WHV_X64_APIC_SMI_CONTEXT ApicSmi; 1247 WHV_HYPERCALL_CONTEXT Hypercall; 1248 WHV_X64_APIC_INIT_SIPI_CONTEXT ApicInitSipi; 1249 }; 1250 } WHV_RUN_VP_EXIT_CONTEXT; 1251 1252 typedef enum WHV_INTERRUPT_TYPE 1253 { 1254 WHvX64InterruptTypeFixed = 0, 1255 WHvX64InterruptTypeLowestPriority = 1, 1256 WHvX64InterruptTypeNmi = 4, 1257 WHvX64InterruptTypeInit = 5, 1258 WHvX64InterruptTypeSipi = 6, 1259 WHvX64InterruptTypeLocalInt1 = 9, 1260 } WHV_INTERRUPT_TYPE; 1261 1262 typedef enum WHV_INTERRUPT_DESTINATION_MODE 1263 { 1264 WHvX64InterruptDestinationModePhysical, 1265 WHvX64InterruptDestinationModeLogical, 1266 } WHV_INTERRUPT_DESTINATION_MODE; 1267 1268 typedef enum WHV_INTERRUPT_TRIGGER_MODE 1269 { 1270 WHvX64InterruptTriggerModeEdge, 1271 WHvX64InterruptTriggerModeLevel, 1272 } WHV_INTERRUPT_TRIGGER_MODE; 1273 1274 typedef struct WHV_INTERRUPT_CONTROL 1275 { 1276 UINT64 Type : 8; // WHV_INTERRUPT_TYPE 1277 UINT64 DestinationMode : 4; // WHV_INTERRUPT_DESTINATION_MODE 1278 UINT64 TriggerMode : 4; // WHV_INTERRUPT_TRIGGER_MODE 1279 UINT64 Reserved : 48; 1280 UINT32 Destination; 1281 UINT32 Vector; 1282 } WHV_INTERRUPT_CONTROL; 1283 1284 typedef struct WHV_DOORBELL_MATCH_DATA 1285 { 1286 WHV_GUEST_PHYSICAL_ADDRESS GuestAddress; 1287 UINT64 Value; 1288 UINT32 Length; 1289 UINT32 MatchOnValue:1; 1290 UINT32 MatchOnLength:1; 1291 UINT32 Reserved:30; 1292 } WHV_DOORBELL_MATCH_DATA; 1293 1294 // WHvGetPartitionCounters types 1295 typedef enum WHV_PARTITION_COUNTER_SET 1296 { 1297 WHvPartitionCounterSetMemory, 1298 } WHV_PARTITION_COUNTER_SET; 1299 1300 typedef struct WHV_PARTITION_MEMORY_COUNTERS 1301 { 1302 UINT64 Mapped4KPageCount; 1303 UINT64 Mapped2MPageCount; 1304 UINT64 Mapped1GPageCount; 1305 } WHV_PARTITION_MEMORY_COUNTERS; 1306 1307 // WHvGetVirtualProcessorCounters types 1308 typedef enum WHV_PROCESSOR_COUNTER_SET 1309 { 1310 WHvProcessorCounterSetRuntime, 1311 WHvProcessorCounterSetIntercepts, 1312 WHvProcessorCounterSetEvents, 1313 WHvProcessorCounterSetApic, 1314 } WHV_PROCESSOR_COUNTER_SET; 1315 1316 typedef struct WHV_PROCESSOR_RUNTIME_COUNTERS 1317 { 1318 UINT64 TotalRuntime100ns; 1319 UINT64 HypervisorRuntime100ns; 1320 } WHV_PROCESSOR_RUNTIME_COUNTERS; 1321 1322 typedef struct WHV_PROCESSOR_INTERCEPT_COUNTER 1323 { 1324 UINT64 Count; 1325 UINT64 Time100ns; 1326 } WHV_PROCESSOR_INTERCEPT_COUNTER; 1327 1328 typedef struct WHV_PROCESSOR_INTERCEPT_COUNTERS 1329 { 1330 WHV_PROCESSOR_INTERCEPT_COUNTER PageInvalidations; 1331 WHV_PROCESSOR_INTERCEPT_COUNTER ControlRegisterAccesses; 1332 WHV_PROCESSOR_INTERCEPT_COUNTER IoInstructions; 1333 WHV_PROCESSOR_INTERCEPT_COUNTER HaltInstructions; 1334 WHV_PROCESSOR_INTERCEPT_COUNTER CpuidInstructions; 1335 WHV_PROCESSOR_INTERCEPT_COUNTER MsrAccesses; 1336 WHV_PROCESSOR_INTERCEPT_COUNTER OtherIntercepts; 1337 WHV_PROCESSOR_INTERCEPT_COUNTER PendingInterrupts; 1338 WHV_PROCESSOR_INTERCEPT_COUNTER EmulatedInstructions; 1339 WHV_PROCESSOR_INTERCEPT_COUNTER DebugRegisterAccesses; 1340 WHV_PROCESSOR_INTERCEPT_COUNTER PageFaultIntercepts; 1341 } WHV_PROCESSOR_ACTIVITY_COUNTERS; 1342 1343 typedef struct WHV_PROCESSOR_EVENT_COUNTERS 1344 { 1345 UINT64 PageFaultCount; 1346 UINT64 ExceptionCount; 1347 UINT64 InterruptCount; 1348 } WHV_PROCESSOR_GUEST_EVENT_COUNTERS; 1349 1350 typedef struct WHV_PROCESSOR_APIC_COUNTERS 1351 { 1352 UINT64 MmioAccessCount; 1353 UINT64 EoiAccessCount; 1354 UINT64 TprAccessCount; 1355 UINT64 SentIpiCount; 1356 UINT64 SelfIpiCount; 1357 } WHV_PROCESSOR_APIC_COUNTERS; 1358 1359 #if defined(_MSC_VER) && (_MSC_VER >= 1200) 1360 #pragma warning(pop) 1361 #endif 1362 1363 #endif // _WINHVAPIDEFS_H_ 1364