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Searched defs:NumVecs (Results 1 – 18 of 18) sorted by relevance

/aosp_15_r20/external/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1019 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable()
1134 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectLoad()
1155 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs, in SelectPostLoad()
1187 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs, in SelectStore()
1203 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs, in SelectPostStore()
1259 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs, in SelectLoadLane()
1298 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs, in SelectPostLoadLane()
1353 void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs, in SelectStoreLane()
1383 void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs, in SelectPostStoreLane()
H A DAArch64ISelLowering.cpp9229 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1486 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable()
1608 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectLoad()
1637 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs, in SelectPostLoad()
1751 void AArch64DAGToDAGISel::SelectCVTIntrinsic(SDNode *N, unsigned NumVecs, in SelectCVTIntrinsic()
1767 void AArch64DAGToDAGISel::SelectPredicatedLoad(SDNode *N, unsigned NumVecs, in SelectPredicatedLoad()
1800 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs, in SelectStore()
1820 void AArch64DAGToDAGISel::SelectPredicatedStore(SDNode *N, unsigned NumVecs, in SelectPredicatedStore()
1862 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs, in SelectPostStore()
1918 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs, in SelectLoadLane()
1957 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs, in SelectPostLoadLane()
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H A DAArch64TargetTransformInfo.cpp3148 unsigned NumVecs = (TpNumElts + LTNumElts - 1) / LTNumElts; in getShuffleCost() local
H A DAArch64ISelLowering.cpp19596 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1164 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable()
1279 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectLoad()
1305 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs, in SelectPostLoad()
1337 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs, in SelectStore()
1357 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs, in SelectPostStore()
1413 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs, in SelectLoadLane()
1452 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs, in SelectPostLoadLane()
1507 void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs, in SelectStoreLane()
1536 void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs, in SelectPostStoreLane()
H A DAArch64ISelLowering.cpp11657 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1868 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign()
2003 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement()
2008 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD()
2147 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST()
2299 unsigned NumVecs, in SelectVLDSTLane()
2646 void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs, in SelectMVE_VLD()
2688 bool isUpdating, unsigned NumVecs, in SelectVLDDup()
H A DARMISelLowering.cpp13105 unsigned NumVecs = 0; in CombineBaseUpdate() local
13309 unsigned NumVecs = 0; in CombineVLDDUP() local
/aosp_15_r20/external/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1688 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign()
1808 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD()
1944 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST()
2093 unsigned NumVecs, in SelectVLDSTLane()
2214 void ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLDDup()
2296 void ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, in SelectVTBL()
H A DARMISelLowering.cpp9923 unsigned NumVecs = 0; in CombineBaseUpdate() local
10123 unsigned NumVecs = 0; in CombineVLDDUP() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1940 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign()
2105 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement()
2110 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD()
2252 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST()
2407 unsigned NumVecs, in SelectVLDSTLane()
2790 void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs, in SelectMVE_VLD()
2953 bool isUpdating, unsigned NumVecs, in SelectVLDDup()
H A DARMISelLowering.cpp15672 unsigned NumVecs = 0; in TryCombineBaseUpdate() local
16166 unsigned NumVecs = 0; in PerformMVEVLDCombine() local
16259 unsigned NumVecs = 0; in CombineVLDDUP() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
H A DVectorUtils.cpp669 unsigned NumVecs) { in createInterleaveMask()
727 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Analysis/
H A DVectorUtils.cpp967 unsigned NumVecs) { in createInterleaveMask()
1042 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp10640 int NumVecs = 2; in LowerINTRINSIC_WO_CHAIN() local
11061 unsigned NumVecs = VT.getSizeInBits() / 128; in LowerVectorLoad() local
11107 unsigned NumVecs = 2; in LowerVectorStore() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp5613 unsigned NumVecs, in selectVectorLoadIntrinsic()
/aosp_15_r20/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp30142 unsigned NumVecs = VT.getSizeInBits() / 128; in combineToExtendVectorInReg() local