1 /* Copyright (c) 2018-2019 Alyssa Rosenzweig ([email protected])
2 * Copyright (C) 2019-2020 Collabora, Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23 #ifndef __MDG_HELPERS_H
24 #define __MDG_HELPERS_H
25
26 #include <stdio.h>
27 #include <string.h>
28 #include "util/macros.h"
29 #include "midgard.h"
30
31 #define OP_IS_LOAD_VARY_F(op) \
32 (op == midgard_op_ld_vary_16 || op == midgard_op_ld_vary_32)
33
34 #define OP_IS_PROJECTION(op) \
35 (op == midgard_op_ldst_perspective_div_y || \
36 op == midgard_op_ldst_perspective_div_z || \
37 op == midgard_op_ldst_perspective_div_w)
38
39 #define OP_IS_VEC4_ONLY(op) \
40 (OP_IS_PROJECTION(op) || op == midgard_op_ld_cubemap_coords)
41
42 #define OP_IS_MOVE(op) \
43 ((op >= midgard_alu_op_fmov && op <= midgard_alu_op_fmov_rtp) || \
44 op == midgard_alu_op_imov)
45
46 #define OP_IS_UBO_READ(op) \
47 (op >= midgard_op_ld_ubo_u8 && op <= midgard_op_ld_ubo_128_bswap8)
48
49 #define OP_IS_CSEL_V(op) \
50 (op == midgard_alu_op_icsel_v || op == midgard_alu_op_fcsel_v)
51
52 #define OP_IS_CSEL(op) \
53 (OP_IS_CSEL_V(op) || op == midgard_alu_op_icsel || \
54 op == midgard_alu_op_fcsel)
55
56 #define OP_IS_UNSIGNED_CMP(op) \
57 (op == midgard_alu_op_ult || op == midgard_alu_op_ule)
58
59 #define OP_IS_INTEGER_CMP(op) \
60 (op == midgard_alu_op_ieq || op == midgard_alu_op_ine || \
61 op == midgard_alu_op_ilt || op == midgard_alu_op_ile || \
62 OP_IS_UNSIGNED_CMP(op))
63
64 #define OP_IS_COMMON_STORE(op) \
65 (op >= midgard_op_st_u8 && op <= midgard_op_st_128_bswap8)
66
67 #define OP_IS_IMAGE(op) \
68 ((op >= midgard_op_ld_image_32f && op <= midgard_op_ld_image_32i) || \
69 (op >= midgard_op_st_image_32f && op <= midgard_op_st_image_32i) || \
70 op == midgard_op_lea_image)
71
72 #define OP_IS_SPECIAL(op) \
73 ((op >= midgard_op_ld_special_32f && op <= midgard_op_ld_special_32i) || \
74 (op >= midgard_op_st_special_32f && op <= midgard_op_st_special_32i))
75
76 #define OP_IS_PACK_COLOUR(op) \
77 ((op >= midgard_op_pack_colour_f32 && op <= midgard_op_pack_colour_s32))
78
79 #define OP_IS_UNPACK_COLOUR(op) \
80 ((op >= midgard_op_unpack_colour_f32 && op <= midgard_op_unpack_colour_s32))
81
82 /* Instructions that are on the load/store unit but don't access memory */
83 #define OP_IS_REG2REG_LDST(op) \
84 (op >= midgard_op_unpack_colour_f32 && \
85 op <= midgard_op_ldst_perspective_div_w)
86
87 /* ALU control words are single bit fields with a lot of space */
88
89 #define ALU_ENAB_VEC_MUL (1 << 17)
90 #define ALU_ENAB_SCAL_ADD (1 << 19)
91 #define ALU_ENAB_VEC_ADD (1 << 21)
92 #define ALU_ENAB_SCAL_MUL (1 << 23)
93 #define ALU_ENAB_VEC_LUT (1 << 25)
94 #define ALU_ENAB_BR_COMPACT (1 << 26)
95 #define ALU_ENAB_BRANCH (1 << 27)
96
97 /* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
98
99 /* Denotes an opcode that takes a vector input with a fixed-number of
100 * channels, but outputs to only a single output channel, like dot products.
101 * For these, to determine the effective mask, this quirk can be set. We have
102 * an intentional off-by-one, since 0-channel makes no sense but we need to fit
103 * 4 channels in 2-bits. Similarly, 1-channel doesn't make sense (since then why
104 * are we quirked?), so that corresponds to "no count set".
105 */
106 #define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
107 #define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
108
109 /* For instructions that take a single argument, normally the first argument
110 * slot is used for the argument and the second slot is a dummy #0 constant.
111 * However, there are exceptions: instructions like fmov store their argument
112 * in the _second_ slot and store a dummy r24 in the first slot, designated by
113 * QUIRK_FLIPPED_R24 */
114
115 #define QUIRK_FLIPPED_R24 (1 << 2)
116
117 /* Is the op commutative? */
118 #define OP_COMMUTES (1 << 3)
119
120 /* Does the op convert types between int- and float- space (i2f/f2u/etc) */
121 #define OP_TYPE_CONVERT (1 << 4)
122
123 /* Is this opcode the first in a f2x (rte, rtz, rtn, rtp) sequence? If so,
124 * takes a roundmode argument in the IR. This has the semantic of rounding the
125 * source (it's all fused in), which is why it doesn't necessarily make sense
126 * for i2f (though folding there might be necessary for OpenCL reasons). Comes
127 * up in format conversion, i.e. f2u_rte */
128 #define MIDGARD_ROUNDS (1 << 5)
129
130 /* Vector-independant shorthands for the above; these numbers are arbitrary and
131 * not from the ISA. Convert to the above with unit_enum_to_midgard */
132
133 #define UNIT_MUL 0
134 #define UNIT_ADD 1
135 #define UNIT_LUT 2
136
137 #define IS_ALU(tag) (tag >= TAG_ALU_4)
138
139 /* Special register aliases */
140
141 #define MAX_WORK_REGISTERS 16
142
143 /* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
144 #define REGISTER_UNIFORMS 24
145
146 /* r24 and r25 are special registers that only exist during the pipeline,
147 * by using them when we don't care about the register we skip a roundtrip
148 * to the register file. */
149 #define REGISTER_UNUSED 24
150 #define REGISTER_CONSTANT 26
151 #define REGISTER_LDST_BASE 26
152 #define REGISTER_TEXTURE_BASE 28
153 #define REGISTER_SELECT 31
154
155 /* The following registers are read-only */
156
157 /* XY is Program Counter, ZW is Stack Pointer */
158 #define REGISTER_LDST_PC_SP 2
159
160 /* XY is Thread Local Storage pointer, ZW is Workgroup Local Storage pointer */
161 #define REGISTER_LDST_LOCAL_STORAGE_PTR 3
162
163 #define REGISTER_LDST_LOCAL_THREAD_ID 4
164 #define REGISTER_LDST_GROUP_ID 5
165 #define REGISTER_LDST_GLOBAL_THREAD_ID 6
166
167 /* This register is always zeroed when read. */
168 #define REGISTER_LDST_ZERO 7
169
170 /* SSA helper aliases to mimic the registers. */
171
172 #define SSA_FIXED_SHIFT 24
173 #define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1)
174 #define SSA_REG_FROM_FIXED(reg) ((((reg) & ~1) >> SSA_FIXED_SHIFT) - 1)
175 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
176
177 #define COMPONENT_X 0x0
178 #define COMPONENT_Y 0x1
179 #define COMPONENT_Z 0x2
180 #define COMPONENT_W 0x3
181
182 #define SWIZZLE_IDENTITY \
183 { \
184 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, \
185 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, \
186 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, \
187 { \
188 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 \
189 } \
190 }
191
192 #define SWIZZLE_IDENTITY_4 \
193 { \
194 {0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
195 {0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
196 {0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
197 {0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
198 }
199
200 static inline unsigned
mask_of(unsigned nr_comp)201 mask_of(unsigned nr_comp)
202 {
203 return (1 << nr_comp) - 1;
204 }
205
206 /* See ISA notes */
207
208 #define LDST_NOP (3)
209
210 /* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
211 * implemented on some subset of these units (or occassionally all of them).
212 * This table encodes a bit mask of valid units for each opcode, so the
213 * scheduler can figure where to plonk the instruction. */
214
215 /* Shorthands for each unit */
216 #define UNIT_VMUL ALU_ENAB_VEC_MUL
217 #define UNIT_SADD ALU_ENAB_SCAL_ADD
218 #define UNIT_VADD ALU_ENAB_VEC_ADD
219 #define UNIT_SMUL ALU_ENAB_SCAL_MUL
220 #define UNIT_VLUT ALU_ENAB_VEC_LUT
221
222 /* Shorthands for usual combinations of units */
223
224 #define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
225 #define UNITS_ADD (UNIT_VADD | UNIT_SADD)
226 #define UNITS_MOST (UNITS_MUL | UNITS_ADD)
227 #define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
228 #define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
229 #define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
230 #define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
231
232 struct mir_op_props {
233 const char *name;
234 unsigned props;
235 };
236
237 /* For load/store */
238
239 struct mir_ldst_op_props {
240 const char *name;
241 unsigned props;
242 };
243
244 struct mir_tex_op_props {
245 const char *name;
246 unsigned props;
247 };
248
249 struct mir_tag_props {
250 const char *name;
251 unsigned size;
252 };
253
254 /* Lower 2-bits are a midgard_reg_mode */
255 #define GET_LDST_SIZE(c) (c & 3)
256
257 /* Store (so the primary register is a source, not a destination */
258 #define LDST_STORE (1 << 2)
259
260 /* Mask has special meaning and should not be manipulated directly */
261 #define LDST_SPECIAL_MASK (1 << 3)
262
263 /* Non-store operation has side effects and should not be eliminated even if
264 * its mask is 0 */
265 #define LDST_SIDE_FX (1 << 4)
266
267 /* Computes an address according to indirects/zext/shift/etc */
268 #define LDST_ADDRESS (1 << 5)
269
270 /* Some fields such swizzle and address have special meanings */
271 #define LDST_ATOMIC (1 << 6)
272
273 /* Operates on attributes/varyings (including images) */
274 #define LDST_ATTRIB (1 << 7)
275
276 /* This file is common, so don't define the tables themselves. #include
277 * midgard_op.h if you need that, or edit midgard_ops.c directly */
278
279 /* Duplicate bits to convert a per-component to duplicated 8-bit format,
280 * which is used for vector units */
281
282 static inline unsigned
expand_writemask(unsigned mask,unsigned log2_channels)283 expand_writemask(unsigned mask, unsigned log2_channels)
284 {
285 unsigned o = 0;
286 unsigned factor = 8 >> log2_channels;
287 unsigned expanded = (1 << factor) - 1;
288
289 for (unsigned i = 0; i < (1 << log2_channels); ++i)
290 if (mask & (1 << i))
291 o |= (expanded << (factor * i));
292
293 return o;
294 }
295
296 /* Coerce structs to integer */
297
298 static inline unsigned
vector_alu_srco_unsigned(midgard_vector_alu_src src)299 vector_alu_srco_unsigned(midgard_vector_alu_src src)
300 {
301 unsigned u;
302 memcpy(&u, &src, sizeof(src));
303 return u;
304 }
305
306 static inline midgard_vector_alu_src
vector_alu_from_unsigned(unsigned u)307 vector_alu_from_unsigned(unsigned u)
308 {
309 midgard_vector_alu_src s;
310 memcpy(&s, &u, sizeof(s));
311 return s;
312 }
313
314 static inline void
mir_compose_swizzle(unsigned * left,unsigned * right,unsigned * final_out)315 mir_compose_swizzle(unsigned *left, unsigned *right, unsigned *final_out)
316 {
317 unsigned out[16];
318
319 for (unsigned c = 0; c < 16; ++c)
320 out[c] = right[left[c]];
321
322 memcpy(final_out, out, sizeof(out));
323 }
324
325 /* Checks for an xyzw.. swizzle, given a mask */
326
327 static inline bool
mir_is_simple_swizzle(unsigned * swizzle,unsigned mask)328 mir_is_simple_swizzle(unsigned *swizzle, unsigned mask)
329 {
330 for (unsigned i = 0; i < 16; ++i) {
331 if (!(mask & (1 << i)))
332 continue;
333
334 if (swizzle[i] != i)
335 return false;
336 }
337
338 return true;
339 }
340
341 /* Packs a load/store argument */
342
343 static inline uint8_t
midgard_ldst_comp(unsigned reg,unsigned component,unsigned size)344 midgard_ldst_comp(unsigned reg, unsigned component, unsigned size)
345 {
346 assert((reg & ~1) == 0);
347 assert(size == 16 || size == 32 || size == 64);
348
349 /* Shift so everything is in terms of 32-bit units */
350 if (size == 64) {
351 assert(component < 2);
352 component <<= 1;
353 } else if (size == 16) {
354 assert((component & 1) == 0);
355 component >>= 1;
356 }
357
358 return component;
359 }
360
361 /* Packs/unpacks a ubo index immediate. The unpack must be defined here so it
362 * can be used with the disassembler, which need not be linked with the main
363 * compiler.
364 */
365
366 void midgard_pack_ubo_index_imm(midgard_load_store_word *word, unsigned index);
367
368 static inline unsigned
midgard_unpack_ubo_index_imm(midgard_load_store_word word)369 midgard_unpack_ubo_index_imm(midgard_load_store_word word)
370 {
371 unsigned ubo = word.arg_comp | (word.arg_reg << 2) |
372 (word.bitsize_toggle << 5) | (word.index_format << 6);
373
374 return ubo;
375 }
376
377 /* Packs/unpacks varying parameters.
378 * FIXME: IMPORTANT: We currently handle varying mode weirdly, by passing all
379 * parameters via an offset and using REGISTER_LDST_ZERO as base. This works
380 * for most parameters, but does not allow us to encode/decode direct sample
381 * position. */
382 void midgard_pack_varying_params(midgard_load_store_word *word,
383 midgard_varying_params p);
384 midgard_varying_params
385 midgard_unpack_varying_params(midgard_load_store_word word);
386
387 /* Load/store ops' displacement helpers.
388 * This is useful because different types of load/store ops have different
389 * displacement bitsize. */
390
391 #define UNPACK_LDST_ATTRIB_OFS(a) ((a) >> 9)
392 #define UNPACK_LDST_VERTEX_OFS(a) util_sign_extend((a) & 0x1FF, 9)
393 #define UNPACK_LDST_SELECTOR_OFS(a) ((a) >> 9)
394 #define UNPACK_LDST_UBO_OFS(a) ((a) >> 2)
395 #define UNPACK_LDST_MEM_OFS(a) ((a))
396
397 #define PACK_LDST_ATTRIB_OFS(a) ((a) << 9)
398 #define PACK_LDST_VERTEX_OFS(a) ((a) & 0x1FF)
399 #define PACK_LDST_SELECTOR_OFS(a) ((a) << 9)
400 #define PACK_LDST_UBO_OFS(a) ((a) << 2)
401 #define PACK_LDST_MEM_OFS(a) ((a))
402
403 static inline bool
midgard_is_branch_unit(unsigned unit)404 midgard_is_branch_unit(unsigned unit)
405 {
406 return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
407 }
408
409 /* Packs ALU mod argument */
410 struct midgard_instruction;
411 unsigned mir_pack_mod(struct midgard_instruction *ins, unsigned i, bool scalar);
412
413 void mir_print_constant_component(FILE *fp, const midgard_constants *consts,
414 unsigned c, midgard_reg_mode reg_mode,
415 bool half, unsigned mod, midgard_alu_op op);
416
417 void mir_print_outmod(FILE *fp, unsigned outmod, bool is_int);
418
419 #endif
420