1 /**
2 * \file
3 *
4 * \brief Chip-specific oscillator management functions.
5 *
6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43 /*
44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
45 */
46
47 #ifndef CHIP_OSC_H_INCLUDED
48 #define CHIP_OSC_H_INCLUDED
49
50 #include "board.h"
51 #include "pmc.h"
52
53 /// @cond 0
54 /**INDENT-OFF**/
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 /**INDENT-ON**/
59 /// @endcond
60
61 /*
62 * Below BOARD_XXX macros are related to the specific board, and
63 * should be defined by the board code, otherwise default value are used.
64 */
65 #if !defined(BOARD_FREQ_SLCK_XTAL)
66 # warning The board slow clock xtal frequency has not been defined.
67 # define BOARD_FREQ_SLCK_XTAL (32768UL)
68 #endif
69
70 #if !defined(BOARD_FREQ_SLCK_BYPASS)
71 # warning The board slow clock bypass frequency has not been defined.
72 # define BOARD_FREQ_SLCK_BYPASS (32768UL)
73 #endif
74
75 #if !defined(BOARD_FREQ_MAINCK_XTAL)
76 # warning The board main clock xtal frequency has not been defined.
77 # define BOARD_FREQ_MAINCK_XTAL (12000000UL)
78 #endif
79
80 #if !defined(BOARD_FREQ_MAINCK_BYPASS)
81 # warning The board main clock bypass frequency has not been defined.
82 # define BOARD_FREQ_MAINCK_BYPASS (12000000UL)
83 #endif
84
85 #if !defined(BOARD_OSC_STARTUP_US)
86 # warning The board main clock xtal startup time has not been defined.
87 # define BOARD_OSC_STARTUP_US (15625UL)
88 #endif
89
90 /**
91 * \weakgroup osc_group
92 * @{
93 */
94
95 //! \name Oscillator identifiers
96 //@{
97 #define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator.
98 #define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator.
99 #define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator.
100 #define OSC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator.
101 #define OSC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator.
102 #define OSC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator.
103 #define OSC_MAINCK_XTAL 6 //!< External crystal oscillator.
104 #define OSC_MAINCK_BYPASS 7 //!< External bypass oscillator.
105 //@}
106
107 //! \name Oscillator clock speed in hertz
108 //@{
109 #define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator.
110 #define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator.
111 #define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator.
112 #define OSC_MAINCK_4M_RC_HZ CHIP_FREQ_MAINCK_RC_4MHZ //!< Internal 4MHz RC oscillator.
113 #define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator.
114 #define OSC_MAINCK_12M_RC_HZ CHIP_FREQ_MAINCK_RC_12MHZ //!< Internal 12MHz RC oscillator.
115 #define OSC_MAINCK_XTAL_HZ BOARD_FREQ_MAINCK_XTAL //!< External crystal oscillator.
116 #define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator.
117 //@}
118
osc_enable(uint32_t ul_id)119 static inline void osc_enable(uint32_t ul_id)
120 {
121 switch (ul_id) {
122 case OSC_SLCK_32K_RC:
123 break;
124
125 case OSC_SLCK_32K_XTAL:
126 pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);
127 break;
128
129 case OSC_SLCK_32K_BYPASS:
130 pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS);
131 break;
132
133
134 case OSC_MAINCK_4M_RC:
135 pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);
136 break;
137
138 case OSC_MAINCK_8M_RC:
139 pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);
140 break;
141
142 case OSC_MAINCK_12M_RC:
143 pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);
144 break;
145
146
147 case OSC_MAINCK_XTAL:
148 pmc_switch_mainck_to_xtal(PMC_OSC_XTAL,
149 pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US,
150 OSC_SLCK_32K_RC_HZ));
151 break;
152
153 case OSC_MAINCK_BYPASS:
154 pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS,
155 pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US,
156 OSC_SLCK_32K_RC_HZ));
157 break;
158 }
159 }
160
osc_disable(uint32_t ul_id)161 static inline void osc_disable(uint32_t ul_id)
162 {
163 switch (ul_id) {
164 case OSC_SLCK_32K_RC:
165 case OSC_SLCK_32K_XTAL:
166 case OSC_SLCK_32K_BYPASS:
167 break;
168
169 case OSC_MAINCK_4M_RC:
170 case OSC_MAINCK_8M_RC:
171 case OSC_MAINCK_12M_RC:
172 pmc_osc_disable_fastrc();
173 break;
174
175 case OSC_MAINCK_XTAL:
176 pmc_osc_disable_xtal(PMC_OSC_XTAL);
177 break;
178
179 case OSC_MAINCK_BYPASS:
180 pmc_osc_disable_xtal(PMC_OSC_BYPASS);
181 break;
182 }
183 }
184
osc_is_ready(uint32_t ul_id)185 static inline bool osc_is_ready(uint32_t ul_id)
186 {
187 switch (ul_id) {
188 case OSC_SLCK_32K_RC:
189 return 1;
190
191 case OSC_SLCK_32K_XTAL:
192 case OSC_SLCK_32K_BYPASS:
193 return pmc_osc_is_ready_32kxtal();
194
195 case OSC_MAINCK_4M_RC:
196 case OSC_MAINCK_8M_RC:
197 case OSC_MAINCK_12M_RC:
198 case OSC_MAINCK_XTAL:
199 case OSC_MAINCK_BYPASS:
200 return pmc_osc_is_ready_mainck();
201 }
202
203 return 0;
204 }
205
osc_get_rate(uint32_t ul_id)206 static inline uint32_t osc_get_rate(uint32_t ul_id)
207 {
208 switch (ul_id) {
209 case OSC_SLCK_32K_RC:
210 return OSC_SLCK_32K_RC_HZ;
211
212 case OSC_SLCK_32K_XTAL:
213 return BOARD_FREQ_SLCK_XTAL;
214
215 case OSC_SLCK_32K_BYPASS:
216 return BOARD_FREQ_SLCK_BYPASS;
217
218 case OSC_MAINCK_4M_RC:
219 return OSC_MAINCK_4M_RC_HZ;
220
221 case OSC_MAINCK_8M_RC:
222 return OSC_MAINCK_8M_RC_HZ;
223
224 case OSC_MAINCK_12M_RC:
225 return OSC_MAINCK_12M_RC_HZ;
226
227 case OSC_MAINCK_XTAL:
228 return BOARD_FREQ_MAINCK_XTAL;
229
230 case OSC_MAINCK_BYPASS:
231 return BOARD_FREQ_MAINCK_BYPASS;
232 }
233
234 return 0;
235 }
236
237 //! @}
238
239 /// @cond 0
240 /**INDENT-OFF**/
241 #ifdef __cplusplus
242 }
243 #endif
244 /**INDENT-ON**/
245 /// @endcond
246
247 #endif /* CHIP_OSC_H_INCLUDED */
248