| /aosp_15_r20/external/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFrameLowering.cpp | 159 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
200 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFrameLowering.cpp | 193 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
247 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFrameLowering.cpp | 295 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
347 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 1014 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1028 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1097 unsigned OffsetReg, in buildIndirectWrite()
1129 unsigned OffsetReg, in buildIndirectRead()
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| H A D | AMDGPUCallLowering.cpp | 223 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress() local
404 auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset); in lowerParameterPtr() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 1040 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1054 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1123 unsigned OffsetReg, in buildIndirectWrite()
1155 unsigned OffsetReg, in buildIndirectRead()
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| H A D | SIFrameLowering.cpp | 120 MCPhysReg OffsetReg = findScratchNonCalleeSaveRegister( in buildPrologSpill() local
167 MCPhysReg OffsetReg = findScratchNonCalleeSaveRegister( in buildEpilogReload() local
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 1059 unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1073 unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1143 unsigned OffsetReg, in buildIndirectWrite()
1175 unsigned OffsetReg, in buildIndirectRead()
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| H A D | SIRegisterInfo.cpp | 293 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in materializeFrameBaseRegister() local
346 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in resolveFrameIndex() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 130 unsigned OffsetReg; member
624 unsigned OffsetReg = Op->getReg(); in MorphToMemRegReg() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 134 unsigned OffsetReg; member
628 unsigned OffsetReg = Op->getReg(); in MorphToMemRegReg() local
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| /aosp_15_r20/external/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 115 unsigned OffsetReg; member
608 unsigned OffsetReg = Op->getReg(); in MorphToMemRegReg() local
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| /aosp_15_r20/external/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 540 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg(); in rewriteT2FrameIndex() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.cpp | 62 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 100 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 566 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg(); in rewriteT2FrameIndex() local
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| H A D | ARMCallLowering.cpp | 105 Register OffsetReg = MRI.createGenericVirtualRegister(s32); in getStackAddress() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 104 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress() local
|
| H A D | Thumb2InstrInfo.cpp | 627 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg(); in rewriteT2FrameIndex() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 114 Register OffsetReg = MRI.createGenericVirtualRegister(SType); in getStackAddress() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 881 Register OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
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| /aosp_15_r20/external/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 715 unsigned OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
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| /aosp_15_r20/external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 147 unsigned OffsetReg = MI->getOperand(2).getReg(); in canRemoveAddasl() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 895 Register OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
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| H A D | MipsCallLowering.cpp | 238 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress() local
|