| /aosp_15_r20/external/capstone/arch/XCore/ |
| H A D | XCoreDisassembler.c | 195 static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2) in Decode2OpInstruction()
219 unsigned *Op1, unsigned *Op2, unsigned *Op3) in Decode3OpInstruction()
312 unsigned Op1, Op2; in Decode2RInstruction() local
326 unsigned Op1, Op2; in Decode2RImmInstruction() local
340 unsigned Op1, Op2; in DecodeR2RInstruction() local
354 unsigned Op1, Op2; in Decode2RSrcDstInstruction() local
369 unsigned Op1, Op2; in DecodeRUSInstruction() local
383 unsigned Op1, Op2; in DecodeRUSBitpInstruction() local
397 unsigned Op1, Op2; in DecodeRUSSrcDstBitpInstruction() local
484 unsigned Op1, Op2; in DecodeL2RInstruction() local
[all …]
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 240 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction()
258 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction()
346 unsigned Op1, Op2; in Decode2RInstruction() local
359 unsigned Op1, Op2; in Decode2RImmInstruction() local
372 unsigned Op1, Op2; in DecodeR2RInstruction() local
385 unsigned Op1, Op2; in Decode2RSrcDstInstruction() local
399 unsigned Op1, Op2; in DecodeRUSInstruction() local
412 unsigned Op1, Op2; in DecodeRUSBitpInstruction() local
425 unsigned Op1, Op2; in DecodeRUSSrcDstBitpInstruction() local
510 unsigned Op1, Op2; in DecodeL2RInstruction() local
[all …]
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| /aosp_15_r20/external/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction()
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction()
347 unsigned Op1, Op2; in Decode2RInstruction() local
360 unsigned Op1, Op2; in Decode2RImmInstruction() local
373 unsigned Op1, Op2; in DecodeR2RInstruction() local
386 unsigned Op1, Op2; in Decode2RSrcDstInstruction() local
400 unsigned Op1, Op2; in DecodeRUSInstruction() local
413 unsigned Op1, Op2; in DecodeRUSBitpInstruction() local
426 unsigned Op1, Op2; in DecodeRUSSrcDstBitpInstruction() local
511 unsigned Op1, Op2; in DecodeL2RInstruction() local
[all …]
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 216 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction()
234 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction()
322 unsigned Op1, Op2; in Decode2RInstruction() local
335 unsigned Op1, Op2; in Decode2RImmInstruction() local
348 unsigned Op1, Op2; in DecodeR2RInstruction() local
361 unsigned Op1, Op2; in Decode2RSrcDstInstruction() local
375 unsigned Op1, Op2; in DecodeRUSInstruction() local
388 unsigned Op1, Op2; in DecodeRUSBitpInstruction() local
401 unsigned Op1, Op2; in DecodeRUSSrcDstBitpInstruction() local
486 unsigned Op1, Op2; in DecodeL2RInstruction() local
[all …]
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| /aosp_15_r20/external/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGTargetInfo.h | 51 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
67 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove()
80 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset()
92 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp()
129 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp()
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/CodeGen/ |
| D | SelectionDAGTargetInfo.h | 53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove()
83 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset()
96 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp()
133 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGTargetInfo.h | 53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove()
83 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset()
96 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp()
133 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp()
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/CodeGen/ |
| D | SelectionDAGTargetInfo.h | 53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove()
83 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset()
96 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp()
133 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp()
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/CodeGen/ |
| D | SelectionDAGTargetInfo.h | 53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove()
83 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset()
96 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp()
133 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGTargetInfo.h | 53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
69 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove()
82 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset()
94 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp()
131 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp()
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/CodeGen/ |
| D | SelectionDAGTargetInfo.h | 53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove()
83 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset()
96 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp()
133 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiMCCodeEmitter.cpp | 142 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits() local
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue() local
222 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRrMemoryOpValue() local
261 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getSplsOpValue() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiMCCodeEmitter.cpp | 142 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits() local
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue() local
222 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRrMemoryOpValue() local
261 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getSplsOpValue() local
|
| /aosp_15_r20/external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiMCCodeEmitter.cpp | 145 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits() local
193 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue() local
225 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRrMemoryOpValue() local
264 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getSplsOpValue() local
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| /aosp_15_r20/external/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.cpp | 93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
111 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 283 const MachineMemOperand &Op2, in alias()
308 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.cpp | 135 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
153 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 283 const MachineMemOperand &Op2, in alias()
308 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 345 const MachineOperand &Op2 = MI->getOperand(2); in profit() local
727 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local
779 MachineOperand &Op2 = MI->getOperand(2); in splitShift() local
903 MachineOperand &Op2 = MI->getOperand(2); in splitAslOr() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 346 const MachineOperand &Op2 = MI->getOperand(2); in profit() local
731 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local
783 MachineOperand &Op2 = MI->getOperand(2); in splitShift() local
907 MachineOperand &Op2 = MI->getOperand(2); in splitAslOr() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand()
294 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.cpp | 158 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
176 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local
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| /aosp_15_r20/external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 291 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCOrOperation()
311 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCAndOperation()
839 SDValue Op1, SDValue Op2, in FindModifiedNodeSlot()
5746 SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) { in UpdateNodeOperands()
5775 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { in UpdateNodeOperands()
5781 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, in UpdateNodeOperands()
5788 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, in UpdateNodeOperands()
5853 SDValue Op2) { in SelectNodeTo()
5861 SDValue Op2, SDValue Op3) { in SelectNodeTo()
5909 SDValue Op1, SDValue Op2) { in SelectNodeTo()
[all …]
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| /aosp_15_r20/external/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand()
295 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr() local
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| /aosp_15_r20/external/executorch/exir/tests/ |
| H A D | test_verification.py | 76 class Op2(torch.nn.Module): class
122 class Op2(torch.nn.Module): class
|