/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
H A D | MipsRegisterBankInfo.h | 75 bool isAmbiguous_64(InstType InstTy, unsigned OpSize) const { in isAmbiguous_64() 81 bool isAmbiguous_32(InstType InstTy, unsigned OpSize) const { in isAmbiguous_32() 87 bool isAmbiguous_32or64(InstType InstTy, unsigned OpSize) const { in isAmbiguous_32or64() 94 unsigned OpSize) const { in isAmbiguousWithMergeOrUnmerge_64() 100 bool isFloatingPoint_32or64(InstType InstTy, unsigned OpSize) const { in isFloatingPoint_32or64() 106 bool isFloatingPoint_64(InstType InstTy, unsigned OpSize) const { in isFloatingPoint_64() 112 bool isInteger_32(InstType InstTy, unsigned OpSize) const { in isInteger_32()
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/aosp_15_r20/external/llvm/utils/TableGen/ |
H A D | X86RecognizableInstr.cpp | 483 uint8_t OpSize)) { in handleOperand() 914 uint8_t OpSize) { in typeFromString() 1048 uint8_t OpSize) { in immediateEncodingFromString() 1086 uint8_t OpSize) { in rmRegisterEncodingFromString() 1118 uint8_t OpSize) { in roRegisterEncodingFromString() 1159 uint8_t OpSize) { in vvvvRegisterEncodingFromString() 1185 uint8_t OpSize) { in writemaskRegisterEncodingFromString() 1199 uint8_t OpSize) { in memoryEncodingFromString() 1240 uint8_t OpSize) { in relocationEncodingFromString() 1287 uint8_t OpSize) { in opcodeModifierEncodingFromString()
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H A D | X86RecognizableInstr.h | 51 uint8_t OpSize; variable
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/MC/MCDisassembler/ |
H A D | MCDisassembler.cpp | 30 uint64_t Offset, uint64_t OpSize, in tryAddingSymbolicOperand()
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H A D | MCExternalSymbolizer.cpp | 36 bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) { in tryAddingSymbolicOperand()
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64ExternalSymbolizer.cpp | 63 bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) { in tryAddingSymbolicOperand()
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
H A D | ARMLegalizerInfo.cpp | 400 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); in legalizeCustom() local
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
H A D | ARMLegalizerInfo.cpp | 404 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); in legalizeCustom() local
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
H A D | AArch64InstructionSelector.cpp | 477 unsigned OpSize) { in selectBinaryOp() 548 unsigned OpSize) { in selectLoadStoreUIOp() 878 unsigned OpSize = MRI.getType(I.getOperand(2).getReg()).getSizeInBits(); in selectFCMPOpc() local 1965 const unsigned OpSize = Ty.getSizeInBits(); in select() local 1991 unsigned OpSize = Ty.getSizeInBits(); in select() local
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H A D | AArch64RegisterBankInfo.cpp | 616 SmallVector<unsigned, 4> OpSize(NumOperands); in getInstrMapping() local
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/aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
H A D | SIFoldOperands.cpp | 317 unsigned OpSize = TII->getOpSize(MI, 1); in runOnMachineFunction() local
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/aosp_15_r20/external/llvm/lib/IR/ |
H A D | Metadata.cpp | 445 size_t OpSize = NumOps * sizeof(MDOperand); in operator new() local 458 size_t OpSize = N->NumOperands * sizeof(MDOperand); in operator delete() local
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/IR/ |
H A D | Metadata.cpp | 481 size_t OpSize = NumOps * sizeof(MDOperand); in operator new() local 496 size_t OpSize = N->NumOperands * sizeof(MDOperand); in operator delete() local
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/GISel/ |
H A D | PPCInstructionSelector.cpp | 146 unsigned OpSize) { in selectLoadStoreOp()
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
H A D | GISelKnownBits.cpp | 485 unsigned OpSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in computeKnownBitsImpl() local
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64RegisterBankInfo.cpp | 676 SmallVector<unsigned, 4> OpSize(NumOperands); in getInstrMapping() local
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H A D | AArch64InstructionSelector.cpp | 751 unsigned OpSize) { in selectBinaryOp() 822 unsigned OpSize) { in selectLoadStoreUIOp() 3054 const unsigned OpSize = Ty.getSizeInBits(); in select() local 4647 unsigned OpSize = Ty.getSizeInBits(); in emitFPCompare() local
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/aosp_15_r20/external/llvm/include/llvm/Analysis/ |
H A D | TargetTransformInfoImpl.h | 76 unsigned OpSize = OpTy->getScalarSizeInBits(); in getOperationCost() local
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPURegisterBankInfo.cpp | 844 unsigned OpSize = OpTy.getSizeInBits(); in executeInWaterfallLoop() local 3011 unsigned OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); in getInstrMapping() local
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/ObjectYAML/ |
H A D | DWARFEmitter.cpp | 837 if (Expected<uint64_t> OpSize = in writeListEntry() local
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
H A D | TargetInstrInfo.cpp | 556 int64_t OpSize = MFI.getObjectSize(FI); in foldMemoryOperand() local
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
H A D | TargetInstrInfo.cpp | 581 int64_t OpSize = MFI.getObjectSize(FI); in foldMemoryOperand() local
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
H A D | MachineIRBuilder.cpp | 542 unsigned OpSize = OpTy.getSizeInBits(); in buildSequence() local
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/aosp_15_r20/external/llvm/lib/Analysis/ |
H A D | ConstantFolding.cpp | 676 unsigned OpSize = DL.getTypeSizeInBits(Op0->getType()); in SymbolicallyEvaluateBinop() local
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPURegisterBankInfo.cpp | 880 unsigned OpSize = OpTy.getSizeInBits(); in executeInWaterfallLoop() local 4337 unsigned OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); in getInstrMapping() local
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