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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp460 OperandMatchResultTy parseGR32(OperandVector &Operands) { in parseGR32()
463 OperandMatchResultTy parseGRH32(OperandVector &Operands) { in parseGRH32()
466 OperandMatchResultTy parseGRX32(OperandVector &Operands) { in parseGRX32()
469 OperandMatchResultTy parseGR64(OperandVector &Operands) { in parseGR64()
472 OperandMatchResultTy parseGR128(OperandVector &Operands) { in parseGR128()
475 OperandMatchResultTy parseADDR32(OperandVector &Operands) { in parseADDR32()
478 OperandMatchResultTy parseADDR64(OperandVector &Operands) { in parseADDR64()
481 OperandMatchResultTy parseADDR128(OperandVector &Operands) { in parseADDR128()
484 OperandMatchResultTy parseFP32(OperandVector &Operands) { in parseFP32()
487 OperandMatchResultTy parseFP64(OperandVector &Operands) { in parseFP64()
[all …]
/aosp_15_r20/external/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp412 OperandMatchResultTy parseGR32(OperandVector &Operands) { in parseGR32()
415 OperandMatchResultTy parseGRH32(OperandVector &Operands) { in parseGRH32()
418 OperandMatchResultTy parseGRX32(OperandVector &Operands) { in parseGRX32()
421 OperandMatchResultTy parseGR64(OperandVector &Operands) { in parseGR64()
424 OperandMatchResultTy parseGR128(OperandVector &Operands) { in parseGR128()
427 OperandMatchResultTy parseADDR32(OperandVector &Operands) { in parseADDR32()
430 OperandMatchResultTy parseADDR64(OperandVector &Operands) { in parseADDR64()
433 OperandMatchResultTy parseADDR128(OperandVector &Operands) { in parseADDR128()
436 OperandMatchResultTy parseFP32(OperandVector &Operands) { in parseFP32()
439 OperandMatchResultTy parseFP64(OperandVector &Operands) { in parseFP64()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp513 OperandMatchResultTy parseGR32(OperandVector &Operands) { in parseGR32()
516 OperandMatchResultTy parseGRH32(OperandVector &Operands) { in parseGRH32()
519 OperandMatchResultTy parseGRX32(OperandVector &Operands) { in parseGRX32()
522 OperandMatchResultTy parseGR64(OperandVector &Operands) { in parseGR64()
525 OperandMatchResultTy parseGR128(OperandVector &Operands) { in parseGR128()
528 OperandMatchResultTy parseADDR32(OperandVector &Operands) { in parseADDR32()
532 OperandMatchResultTy parseADDR64(OperandVector &Operands) { in parseADDR64()
536 OperandMatchResultTy parseADDR128(OperandVector &Operands) { in parseADDR128()
539 OperandMatchResultTy parseFP32(OperandVector &Operands) { in parseFP32()
542 OperandMatchResultTy parseFP64(OperandVector &Operands) { in parseFP64()
[all …]
/aosp_15_r20/external/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp692 …void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, f… in cvtMubuf()
693 …void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, tr… in cvtMubufAtomic()
694 …void cvtMubufAtomicReturn(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operan… in cvtMubufAtomicReturn()
968 AMDGPUAsmParser::parseImm(OperandVector &Operands) { in parseImm()
1012 AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands) { in parseRegOrImm()
1028 AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands) { in parseRegOrImmWithFPInputMods()
1092 AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands) { in parseRegOrImmWithIntInputMods()
1146 OperandVector &Operands, in MatchAndEmitInstruction()
1437 AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { in parseOperand()
1502 SMLoc NameLoc, OperandVector &Operands) { in ParseInstruction()
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1587 void cvtDS(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, false); } in cvtDS()
1588 void cvtDSGds(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, true); } in cvtDSGds()
1740 …void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false); } in cvtMubuf()
1741 …void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, tr… in cvtMubufAtomic()
1786 void cvtDPP8(MCInst &Inst, const OperandVector &Operands) { in cvtDPP8()
1791 void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) { in cvtVOP3DPP8()
2926 AMDGPUAsmParser::parseImm(OperandVector &Operands, bool HasSP3AbsModifier) { in parseImm()
3001 AMDGPUAsmParser::parseReg(OperandVector &Operands) { in parseReg()
3014 AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod) { in parseRegOrImm()
3114 AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands, in parseRegOrImmWithFPInputMods()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1282 void cvtDS(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, false); } in cvtDS()
1283 void cvtDSGds(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, true); } in cvtDSGds()
1382 …void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, f… in cvtMubuf()
1383 …void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, tr… in cvtMubufAtomic()
1384 …void cvtMubufAtomicReturn(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operan… in cvtMubufAtomicReturn()
1385 …void cvtMubufLds(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false… in cvtMubufLds()
1419 void cvtDPP8(MCInst &Inst, const OperandVector &Operands) { cvtDPP(Inst, Operands, true); } in cvtDPP8()
2338 AMDGPUAsmParser::parseImm(OperandVector &Operands, bool HasSP3AbsModifier) { in parseImm()
2412 AMDGPUAsmParser::parseReg(OperandVector &Operands) { in parseReg()
2425 AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod) { in parseRegOrImm()
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/aosp_15_r20/external/vixl/test/aarch32/
H A Dtest-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc68 struct Operands { struct
69 Condition cond;
70 Register rd;
71 Register rn;
72 Sign sign;
73 Register rm;
74 ShiftType shift;
75 uint32_t amount;
76 AddrMode addr_mode;
H A Dtest-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc68 struct Operands { struct
69 Condition cond;
70 Register rd;
71 Register rn;
72 Sign sign;
73 Register rm;
74 ShiftType shift;
75 uint32_t amount;
76 AddrMode addr_mode;
H A Dtest-assembler-negative-cond-rd-rn-operand-rm-shift-rs-a32.cc84 struct Operands { struct
85 Condition cond;
86 Register rd;
87 Register rn;
88 Register rm;
89 ShiftType shift;
90 Register rs;
H A Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc84 struct Operands { struct
85 Condition cond;
86 Register rd;
87 Register rn;
88 Register rm;
89 ShiftType shift;
90 uint32_t amount;
H A Dtest-assembler-cond-rd-memop-immediate-512-a32.cc68 struct Operands { struct
69 Condition cond;
70 Register rd;
71 Register rn;
72 Sign sign;
73 int32_t offset;
74 AddrMode addr_mode;
H A Dtest-assembler-cond-rd-memop-rs-a32.cc72 struct Operands { struct
73 Condition cond;
74 Register rd;
75 Register rn;
76 Sign sign;
77 Register rm;
78 AddrMode addr_mode;
H A Dtest-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc84 struct Operands { struct
85 Condition cond;
86 Register rd;
87 Register rn;
88 Register rm;
89 ShiftType shift;
90 Register rs;
H A Dtest-assembler-cond-rd-memop-immediate-8192-a32.cc68 struct Operands { struct
69 Condition cond;
70 Register rd;
71 Register rn;
72 Sign sign;
73 int32_t offset;
74 AddrMode addr_mode;
H A Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc84 struct Operands { struct
85 Condition cond;
86 Register rd;
87 Register rn;
88 Register rm;
89 ShiftType shift;
90 uint32_t amount;
H A Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc84 struct Operands { struct
85 Condition cond;
86 Register rd;
87 Register rn;
88 Register rm;
89 ShiftType shift;
90 uint32_t amount;
H A Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc84 struct Operands { struct
85 Condition cond;
86 Register rd;
87 Register rn;
88 Register rm;
89 ShiftType shift;
90 uint32_t amount;
H A Dtest-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc70 struct Operands { struct
71 Condition cond;
72 Register rd;
73 Register rn;
74 Register rm;
75 ShiftType ror;
76 uint32_t amount;
H A Dtest-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc70 struct Operands { struct
71 Condition cond;
72 Register rd;
73 Register rn;
74 Register rm;
75 ShiftType ror;
76 uint32_t amount;
H A Dtest-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc133 struct Operands { struct
134 Condition cond;
135 Register rd;
136 Register rn;
137 Sign sign;
138 Register rm;
139 ShiftType shift;
140 uint32_t amount;
141 AddrMode addr_mode;
H A Dtest-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc133 struct Operands { struct
134 Condition cond;
135 Register rd;
136 Register rn;
137 Sign sign;
138 Register rm;
139 ShiftType shift;
140 uint32_t amount;
141 AddrMode addr_mode;
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc64 struct Operands { struct
65 Condition cond;
66 Register rd;
67 Register rn;
68 ShiftType shift;
69 Register rs;
H A Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-in-it-block-t32.cc64 struct Operands { struct
65 Condition cond;
66 Register rd;
67 Register rn;
68 ShiftType shift;
69 uint32_t amount;
/aosp_15_r20/external/llvm/docs/
H A DMIRLangRef.rst362 Immediate Operands
375 .. _register-operands:
377 Register Operands
398 .. _register-flags:
400 Register Flags
441 Subregister Indices
456 Global Value Operands
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1060 OperandVector &Operands, uint64_t ErrorInfo, int64_t Lower, int64_t Upper, in generateImmOutOfRangeError()
1067 OperandVector &Operands, in MatchAndEmitInstruction()
1334 OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands, in parseRegister()
1384 RISCVAsmParser::parseInsnDirectiveOpcode(OperandVector &Operands) { in parseInsnDirectiveOpcode()
1445 RISCVAsmParser::parseCSRSystemRegister(OperandVector &Operands) { in parseCSRSystemRegister()
1519 OperandMatchResultTy RISCVAsmParser::parseImmediate(OperandVector &Operands) { in parseImmediate()
1548 RISCVAsmParser::parseOperandWithModifier(OperandVector &Operands) { in parseOperandWithModifier()
1587 OperandMatchResultTy RISCVAsmParser::parseBareSymbol(OperandVector &Operands) { in parseBareSymbol()
1642 OperandMatchResultTy RISCVAsmParser::parseCallSymbol(OperandVector &Operands) { in parseCallSymbol()
1671 RISCVAsmParser::parsePseudoJumpSymbol(OperandVector &Operands) { in parsePseudoJumpSymbol()
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