1 // Copyright 2021 The ChromiumOS Authors 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 mod pci_bridge; 6 mod pcie_device; 7 mod pcie_host; 8 mod pcie_port; 9 mod pcie_rp; 10 mod pcie_switch; 11 12 pub use pci_bridge::PciBridge; 13 pub use pcie_host::PcieHostPort; 14 pub use pcie_rp::PcieRootPort; 15 pub use pcie_switch::PcieDownstreamPort; 16 pub use pcie_switch::PcieUpstreamPort; 17 18 #[allow(dead_code)] 19 #[derive(Clone, Copy, Eq, PartialEq)] 20 pub enum PcieDevicePortType { 21 PcieEndpoint = 0, 22 PcieLegacyEndpoint = 1, 23 RootPort = 4, 24 UpstreamPort = 5, 25 DownstreamPort = 6, 26 Pcie2PciBridge = 7, 27 Pci2PcieBridge = 8, 28 RCIntegratedEndpoint = 9, 29 RCEventCollector = 0xa, 30 } 31 32 const PCIE_CAP_LEN: usize = 0x3C; 33 34 const PCIE_CAP_VERSION: u16 = 0x2; 35 const PCIE_TYPE_SHIFT: u16 = 0x4; 36 const PCIE_CAP_SLOT_SHIFT: u16 = 0x8; 37 const PCIE_CAP_IRQ_NUM_SHIFT: u16 = 0x9; 38 39 const PCIE_DEVCAP_RBER: u32 = 0x0000_8000; 40 const PCIE_LINK_X1: u16 = 0x10; 41 const PCIE_LINK_2_5GT: u16 = 0x01; 42 43 const PCIE_SLTCAP_ABP: u32 = 0x01; // Attention Button Present 44 const PCIE_SLTCAP_AIP: u32 = 0x08; // Attention Indicator Present 45 const PCIE_SLTCAP_PIP: u32 = 0x10; // Power Indicator Present 46 const PCIE_SLTCAP_HPS: u32 = 0x20; // Hot-Plug Surprise 47 const PCIE_SLTCAP_HPC: u32 = 0x40; // Hot-Plug Capable 48 49 const PCIE_SLTCTL_OFFSET: usize = 0x18; 50 const PCIE_SLTCTL_PIC: u16 = 0x300; // Power indicator 51 const PCIE_SLTCTL_PIC_ON: u16 = 0x100; // Power indicator on 52 const PCIE_SLTCTL_PIC_BLINK: u16 = 0x200; // Power indicator blink 53 const PCIE_SLTCTL_PIC_OFF: u16 = 0x300; // Power indicator off 54 const PCIE_SLTCTL_AIC_OFF: u16 = 0xC0; 55 const PCIE_SLTCTL_ABPE: u16 = 0x01; 56 const PCIE_SLTCTL_PDCE: u16 = 0x08; 57 const PCIE_SLTCTL_CCIE: u16 = 0x10; 58 const PCIE_SLTCTL_HPIE: u16 = 0x20; 59 60 const PCIE_SLTSTA_OFFSET: usize = 0x1A; 61 const PCIE_SLTSTA_ABP: u16 = 0x0001; 62 const PCIE_SLTSTA_PFD: u16 = 0x0002; 63 const PCIE_SLTSTA_PDC: u16 = 0x0008; 64 const PCIE_SLTSTA_CC: u16 = 0x0010; 65 const PCIE_SLTSTA_PDS: u16 = 0x0040; 66 const PCIE_SLTSTA_DLLSC: u16 = 0x0100; 67 68 const PCIE_ROOTCTL_OFFSET: usize = 0x1C; 69 const PCIE_ROOTCTL_PME_ENABLE: u16 = 0x08; 70 71 const PCIE_ROOTSTA_OFFSET: usize = 0x20; 72 const PCIE_ROOTSTA_PME_REQ_ID_MASK: u32 = 0xFFFF; 73 const PCIE_ROOTSTA_PME_STATUS: u32 = 0x10000; 74 const PCIE_ROOTSTA_PME_PENDING: u32 = 0x20000; 75