1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_METEORLAKE_PCI_DEVS_H_ 4 #define _SOC_METEORLAKE_PCI_DEVS_H_ 5 6 #include <device/pci_def.h> 7 8 #define _PCI_DEVFN(slot, func) PCI_DEVFN(PCI_DEV_SLOT_ ## slot, func) 9 #if !defined(__SIMPLE_DEVICE__) 10 #include <device/device.h> 11 #define _PCI_DEV(slot, func) pcidev_path_on_root_debug(_PCI_DEVFN(slot, func), __func__) 12 #else 13 #define _PCI_DEV(slot, func) PCI_DEV(0, PCI_DEV_SLOT_ ## slot, func) 14 #endif 15 16 /* System Agent Devices */ 17 #define PCI_DEV_SLOT_ROOT 0x00 18 #define PCI_DEVFN_ROOT _PCI_DEVFN(ROOT, 0) 19 #if defined(__SIMPLE_DEVICE__) 20 #define PCI_DEV_ROOT _PCI_DEV(ROOT, 0) 21 #endif 22 23 #define PCI_DEV_SLOT_PCIE_3 0x1 24 #define PCI_DEVFN_PCIE12 _PCI_DEVFN(PCIE_3, 0) 25 #define PCI_DEV_PCIE12 _PCI_DEV(PCIE_3, 0) 26 27 #define PCI_DEV_SLOT_IGD 0x02 28 #define PCI_DEVFN_IGD _PCI_DEVFN(IGD, 0) 29 #define PCI_DEV_IGD _PCI_DEV(IGD, 0) 30 31 #define PCI_DEV_SLOT_DPTF 0x04 32 #define PCI_DEVFN_DPTF _PCI_DEVFN(DPTF, 0) 33 #define PCI_DEV_DPTF _PCI_DEV(DPTF, 0) 34 35 #define PCI_DEV_SLOT_IPU 0x05 36 #define PCI_DEVFN_IPU _PCI_DEVFN(IPU, 0) 37 #define PCI_DEV_IPU _PCI_DEV(IPU, 0) 38 39 #define PCI_DEV_SLOT_PCIE_2 0x6 40 #define PCI_DEVFN_PCIE9 _PCI_DEVFN(PCIE_2, 0) 41 #define PCI_DEVFN_PCIE10 _PCI_DEVFN(PCIE_2, 1) 42 #define PCI_DEVFN_PCIE11 _PCI_DEVFN(PCIE_2, 2) 43 #define PCI_DEV_PCIE9 _PCI_DEV(PCIE_2, 0) 44 #define PCI_DEV_PCIE10 _PCI_DEV(PCIE_2, 1) 45 #define PCI_DEV_PCIE11 _PCI_DEV(PCIE_2, 2) 46 47 #define PCI_DEV_SLOT_TBT 0x07 48 #define PCI_DEVFN_TBT(x) _PCI_DEVFN(TBT, (x)) 49 #define NUM_TBT_FUNCTIONS 4 50 #define PCI_DEVFN_TBT0 _PCI_DEVFN(TBT, 0) 51 #define PCI_DEVFN_TBT1 _PCI_DEVFN(TBT, 1) 52 #define PCI_DEVFN_TBT2 _PCI_DEVFN(TBT, 2) 53 #define PCI_DEVFN_TBT3 _PCI_DEVFN(TBT, 3) 54 #define PCI_DEV_TBT0 _PCI_DEV(TBT, 0) 55 #define PCI_DEV_TBT1 _PCI_DEV(TBT, 1) 56 #define PCI_DEV_TBT2 _PCI_DEV(TBT, 2) 57 #define PCI_DEV_TBT3 _PCI_DEV(TBT, 3) 58 59 #define PCI_DEV_SLOT_GNA 0x08 60 #define PCI_DEVFN_GNA _PCI_DEVFN(GNA, 0) 61 #define PCI_DEV_GNA _PCI_DEV(GNA, 0) 62 63 #define PCI_DEV_SLOT_TELEMETRY 0x0a 64 #define PCI_DEVFN_TELEMETRY _PCI_DEVFN(TELEMETRY, 0) 65 #define PCI_DEV_TELEMETRY _PCI_DEV(TELEMETRY, 0) 66 67 #define PCI_DEV_SLOT_TCSS 0x0d 68 #define NUM_TCSS_DMA_FUNCTIONS 2 69 #define PCI_DEVFN_TCSS_DMA(x) _PCI_DEVFN(TCSS, ((x) + 2)) 70 #define PCI_DEVFN_TCSS_XHCI _PCI_DEVFN(TCSS, 0) 71 #define PCI_DEVFN_TCSS_XDCI _PCI_DEVFN(TCSS, 1) 72 #define PCI_DEVFN_TCSS_DMA0 _PCI_DEVFN(TCSS, 2) 73 #define PCI_DEVFN_TCSS_DMA1 _PCI_DEVFN(TCSS, 3) 74 #define PCI_DEV_TCSS_XHCI _PCI_DEV(TCSS, 0) 75 #define PCI_DEV_TCSS_XDCI _PCI_DEV(TCSS, 1) 76 #define PCI_DEV_TCSS_DMA0 _PCI_DEV(TCSS, 2) 77 #define PCI_DEV_TCSS_DMA1 _PCI_DEV(TCSS, 3) 78 79 #define PCI_DEV_SLOT_VPU 0x0b 80 #define PCI_DEVFN_VPU _PCI_DEVFN(VPU, 0) 81 #define PCI_DEV_VPU _PCI_DEV(VPU, 0) 82 83 #define PCI_DEV_SLOT_VMD 0x0e 84 #define PCI_DEVFN_VMD _PCI_DEVFN(VMD, 0) 85 #define PCI_DEV_VMD _PCI_DEV(VMD, 0) 86 87 #define PCI_DEV_SLOT_THC 0x10 88 #define PCI_DEVFN_THC0 _PCI_DEVFN(THC, 0) 89 #define PCI_DEVFN_THC1 _PCI_DEVFN(THC, 1) 90 #define PCI_DEV_THC0 _PCI_DEV(THC, 0) 91 #define PCI_DEV_THC1 _PCI_DEV(THC, 1) 92 93 #define PCI_DEV_SLOT_ISH 0x12 94 #define PCI_DEVFN_ISH _PCI_DEVFN(ISH, 0) 95 #define PCI_DEVFN_GSPI2 _PCI_DEVFN(ISH, 6) 96 #define PCI_DEVFN_UFS _PCI_DEVFN(ISH, 7) 97 #define PCI_DEV_ISH _PCI_DEV(ISH, 0) 98 #define PCI_DEV_GSPI2 _PCI_DEV(ISH, 6) 99 #define PCI_DEV_UFS _PCI_DEV(ISH, 7) 100 101 #define PCI_DEV_SLOT_IOE 0x13 102 #define PCI_DEVFN_IOE_P2SB _PCI_DEVFN(IOE, 0) 103 #define PCI_DEVFN_IOE_PMC _PCI_DEVFN(IOE, 2) 104 #define PCI_DEVFN_IOE_SRAM _PCI_DEVFN(IOE, 3) 105 #define PCI_DEV_IOE_P2SB _PCI_DEV(IOE, 0) 106 #define PCI_DEV_IOE_PMC _PCI_DEV(IOE, 2) 107 #define PCI_DEV_IOE_SRAM _PCI_DEV(IOE, 3) 108 109 #define PCI_DEV_SLOT_XHCI 0x14 110 #define PCI_DEVFN_XHCI _PCI_DEVFN(XHCI, 0) 111 #define PCI_DEVFN_USBOTG _PCI_DEVFN(XHCI, 1) 112 #define PCI_DEVFN_SRAM _PCI_DEVFN(XHCI, 2) 113 #define PCI_DEVFN_CNVI_WIFI _PCI_DEVFN(XHCI, 3) 114 #define PCI_DEV_XHCI _PCI_DEV(XHCI, 0) 115 #define PCI_DEV_USBOTG _PCI_DEV(XHCI, 1) 116 #define PCI_DEV_SRAM _PCI_DEV(XHCI, 2) 117 #define PCI_DEV_CNVI_WIFI _PCI_DEV(XHCI, 3) 118 119 #define PCI_DEV_SLOT_SIO0 0x15 120 #define PCI_DEVFN_I2C0 _PCI_DEVFN(SIO0, 0) 121 #define PCI_DEVFN_I2C1 _PCI_DEVFN(SIO0, 1) 122 #define PCI_DEVFN_I2C2 _PCI_DEVFN(SIO0, 2) 123 #define PCI_DEVFN_I2C3 _PCI_DEVFN(SIO0, 3) 124 #define PCI_DEV_I2C0 _PCI_DEV(SIO0, 0) 125 #define PCI_DEV_I2C1 _PCI_DEV(SIO0, 1) 126 #define PCI_DEV_I2C2 _PCI_DEV(SIO0, 2) 127 #define PCI_DEV_I2C3 _PCI_DEV(SIO0, 3) 128 129 #define PCI_DEV_SLOT_CSE 0x16 130 #define PCI_DEVFN_CSE _PCI_DEVFN(CSE, 0) 131 #define PCI_DEVFN_CSE_2 _PCI_DEVFN(CSE, 1) 132 #define PCI_DEVFN_CSE_IDER _PCI_DEVFN(CSE, 2) 133 #define PCI_DEVFN_CSE_KT _PCI_DEVFN(CSE, 3) 134 #define PCI_DEVFN_CSE_3 _PCI_DEVFN(CSE, 4) 135 #define PCI_DEVFN_CSE_4 _PCI_DEVFN(CSE, 5) 136 #define PCI_DEV_CSE _PCI_DEV(CSE, 0) 137 #define PCI_DEV_CSE_2 _PCI_DEV(CSE, 1) 138 #define PCI_DEV_CSE_IDER _PCI_DEV(CSE, 2) 139 #define PCI_DEV_CSE_KT _PCI_DEV(CSE, 3) 140 #define PCI_DEV_CSE_3 _PCI_DEV(CSE, 4) 141 #define PCI_DEV_CSE_4 _PCI_DEV(CSE, 5) 142 143 #define PCI_DEV_SLOT_SATA 0x17 144 #define PCI_DEVFN_SATA _PCI_DEVFN(SATA, 0) 145 #define PCI_DEV_SATA _PCI_DEV(SATA, 0) 146 147 #define PCI_DEV_SLOT_ISSE 0x18 148 #define PCI_DEVFN_ISSE1 _PCI_DEVFN(ESE, 0) 149 #define PCI_DEVFN_ISSE2 _PCI_DEVFN(ESE, 1) 150 #define PCI_DEVFN_ISSE3 _PCI_DEVFN(ESE, 2) 151 #define PCI_DEV_ISSE1 _PCI_DEV(ESE, 0) 152 #define PCI_DEV_ISSE2 _PCI_DEV(ESE, 1) 153 #define PCI_DEV_ISSE3 _PCI_DEV(ESE, 2) 154 155 #define PCI_DEV_SLOT_SIO1 0x19 156 #define PCI_DEVFN_I2C4 _PCI_DEVFN(SIO1, 0) 157 #define PCI_DEVFN_I2C5 _PCI_DEVFN(SIO1, 1) 158 #define PCI_DEVFN_UART2 _PCI_DEVFN(SIO1, 2) 159 #define PCI_DEV_I2C4 _PCI_DEV(SIO1, 0) 160 #define PCI_DEV_I2C5 _PCI_DEV(SIO1, 1) 161 #define PCI_DEV_UART2 _PCI_DEV(SIO1, 2) 162 163 #define PCI_DEV_SLOT_PCIE_1 0x1c 164 #define PCI_DEVFN_PCIE1 _PCI_DEVFN(PCIE_1, 0) 165 #define PCI_DEVFN_PCIE2 _PCI_DEVFN(PCIE_1, 1) 166 #define PCI_DEVFN_PCIE3 _PCI_DEVFN(PCIE_1, 2) 167 #define PCI_DEVFN_PCIE4 _PCI_DEVFN(PCIE_1, 3) 168 #define PCI_DEVFN_PCIE5 _PCI_DEVFN(PCIE_1, 4) 169 #define PCI_DEVFN_PCIE6 _PCI_DEVFN(PCIE_1, 5) 170 #define PCI_DEVFN_PCIE7 _PCI_DEVFN(PCIE_1, 6) 171 #define PCI_DEVFN_PCIE8 _PCI_DEVFN(PCIE_1, 7) 172 #define PCI_DEV_PCIE1 _PCI_DEV(PCIE_1, 0) 173 #define PCI_DEV_PCIE2 _PCI_DEV(PCIE_1, 1) 174 #define PCI_DEV_PCIE3 _PCI_DEV(PCIE_1, 2) 175 #define PCI_DEV_PCIE4 _PCI_DEV(PCIE_1, 3) 176 #define PCI_DEV_PCIE5 _PCI_DEV(PCIE_1, 4) 177 #define PCI_DEV_PCIE6 _PCI_DEV(PCIE_1, 5) 178 #define PCI_DEV_PCIE7 _PCI_DEV(PCIE_1, 6) 179 #define PCI_DEV_PCIE8 _PCI_DEV(PCIE_1, 7) 180 181 #define PCI_DEV_SLOT_SIO2 0x1e 182 #define PCI_DEVFN_UART0 _PCI_DEVFN(SIO2, 0) 183 #define PCI_DEVFN_UART1 _PCI_DEVFN(SIO2, 1) 184 #define PCI_DEVFN_GSPI0 _PCI_DEVFN(SIO2, 2) 185 #define PCI_DEVFN_GSPI1 _PCI_DEVFN(SIO2, 3) 186 #define PCI_DEVFN_TSN1 _PCI_DEVFN(SIO2, 4) 187 #define PCI_DEVFN_TSN2 _PCI_DEVFN(SIO2, 5) 188 #define PCI_DEV_UART0 _PCI_DEV(SIO2, 0) 189 #define PCI_DEV_UART1 _PCI_DEV(SIO2, 1) 190 #define PCI_DEV_GSPI0 _PCI_DEV(SIO2, 2) 191 #define PCI_DEV_GSPI1 _PCI_DEV(SIO2, 3) 192 #define PCI_DEV_TSN1 _PCI_DEV(SIO2, 4) 193 #define PCI_DEV_TSN2 _PCI_DEV(SIO2, 5) 194 195 #define PCI_DEV_SLOT_ESPI 0x1f 196 #define PCI_DEVFN_ESPI _PCI_DEVFN(ESPI, 0) 197 #define PCI_DEVFN_P2SB _PCI_DEVFN(ESPI, 1) 198 #define PCI_DEVFN_PMC _PCI_DEVFN(ESPI, 2) 199 #define PCI_DEVFN_HDA _PCI_DEVFN(ESPI, 3) 200 #define PCI_DEVFN_SMBUS _PCI_DEVFN(ESPI, 4) 201 #define PCI_DEVFN_SPI _PCI_DEVFN(ESPI, 5) 202 #define PCI_DEVFN_GBE _PCI_DEVFN(ESPI, 6) 203 #define PCI_DEVFN_NPK _PCI_DEVFN(ESPI, 7) 204 #define PCI_DEV_ESPI _PCI_DEV(ESPI, 0) 205 #define PCI_DEV_P2SB _PCI_DEV(ESPI, 1) 206 207 #if !ENV_RAMSTAGE 208 /* 209 * PCI_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets 210 * hidden from PCI bus after call to FSP-S. This leads to resource allocator 211 * dropping it from the root bus as unused device. All references to PCI_DEV_PMC 212 * would then return NULL and can go unnoticed if not handled properly. Since, 213 * this device does not have any special chip config associated with it, it is 214 * okay to not provide the definition for it in ramstage. 215 */ 216 #define PCI_DEV_PMC _PCI_DEV(ESPI, 2) 217 #endif 218 219 #define PCI_DEV_HDA _PCI_DEV(ESPI, 3) 220 #define PCI_DEV_SMBUS _PCI_DEV(ESPI, 4) 221 #define PCI_DEV_SPI _PCI_DEV(ESPI, 5) 222 #define PCI_DEV_GBE _PCI_DEV(ESPI, 6) 223 #define PCI_DEV_NPK _PCI_DEV(ESPI, 7) 224 225 #endif 226 227 /* for common code */ 228 #define MIN_PCH_SLOT PCI_DEV_SLOT_THC 229 #define PCH_DEV_SLOT_CSE PCI_DEV_SLOT_CSE 230 #define PCH_DEVFN_CSE PCI_DEVFN_CSE 231 #define PCH_DEV_CSE PCI_DEV_CSE 232 #define PCH_DEV_SPI PCI_DEV_SPI 233 #define PCH_DEV_LPC PCI_DEV_ESPI 234 #define PCH_DEV_P2SB PCI_DEV_P2SB 235 #define PCH_DEV_SMBUS PCI_DEV_SMBUS 236 #define PCH_DEV_XHCI PCI_DEV_XHCI 237 #define PCH_DEVFN_XHCI PCI_DEVFN_XHCI 238 #define PCH_DEVFN_PMC PCI_DEVFN_PMC 239 #define PCH_DEV_SLOT_ISH PCI_DEV_SLOT_ISH 240 #define SA_DEV_ROOT PCI_DEV_ROOT 241 #define SA_DEVFN_ROOT PCI_DEVFN_ROOT 242 #define SA_DEVFN_TCSS_DMA0 PCI_DEVFN_TCSS_DMA0 243 #define SA_DEVFN_TCSS_DMA1 PCI_DEVFN_TCSS_DMA1 244 #define SA_DEV_IGD PCI_DEV_IGD 245 #define SA_DEVFN_IGD PCI_DEVFN_IGD 246