1# SPDX-License-Identifier: GPL-2.0-only 2 3config PLATFORM_USES_FSP2_0 4 bool 5 default n 6 help 7 Include FSP 2.0 wrappers and functionality 8 9config PLATFORM_USES_FSP2_1 10 bool 11 default n 12 select PLATFORM_USES_FSP2_0 13 select FSP_USES_CB_STACK 14 help 15 Include FSP 2.1 wrappers and functionality. 16 Feature added into FSP 2.1 specification that impacts coreboot is: 17 1. Remove FSP stack switch and use the same stack with boot firmware 18 19config PLATFORM_USES_FSP2_2 20 bool 21 default n 22 select PLATFORM_USES_FSP2_1 23 help 24 Include FSP 2.2 wrappers and functionality. 25 Features added into FSP 2.2 specification that impact coreboot are: 26 1. Added multi-phase silicon initialization to increase the modularity of the 27 FspSiliconInit() API 28 2. FSP_INFO_HEADER changes to add FspMultiPhaseSiInitEntryOffset 29 3. Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP2.0/2.1 can disable 30 the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change. 31 32config PLATFORM_USES_FSP2_3 33 bool 34 default n 35 select PLATFORM_USES_FSP2_2 36 help 37 Include FSP 2.3 wrappers and functionality. 38 Features added into FSP 2.3 specification that impact coreboot are: 39 1. Added ExtendedImageRevision field in FSP_INFO_HEADER 40 2. Added FSP_NON_VOLATILE_STORAGE_HOB2 41 42config PLATFORM_USES_FSP2_4 43 bool 44 default n 45 select PLATFORM_USES_FSP2_3 46 help 47 Include FSP 2.4 wrappers and functionality. 48 Features added into FSP 2.4 specification that impact coreboot are: 49 1. FSP-M multi phase init support 50 2. FSPM_ARCH2_UPD and FSPS_ARCH2_UPD data structures must be 51 used in place of FSPM_ARCH_UPD and FSPS_ARCH_UPD respectively 52 3. 64-bits support 53 54if PLATFORM_USES_FSP2_0 55 56config PLATFORM_USES_FSP2_X86_32 57 bool 58 default n if PLATFORM_USES_FSP2_4 59 default y 60 help 61 Specify if the FSP binaries are 32-bits (yes) or 64-bits 62 (no). By default, 64-bit should be used starting with FSP 63 specification 2.4 64 65config HAVE_INTEL_FSP_REPO 66 bool 67 help 68 Select this, if the FSP binaries for the platform are public 69 and available in 3rdparty/fsp/. When selecting this option, the 70 platform must also set FSP_HEADER_PATH and FSP_FD_PATH correctly. 71 72config FSP_USE_REPO 73 bool "Use binaries of the Intel FSP repository on GitHub" 74 depends on HAVE_INTEL_FSP_REPO 75 select FSP_FULL_FD 76 default y 77 help 78 Select this option to use the default FSP headers and binaries 79 found in the IntelFsp GitHub repository at 80 81 https://github.com/IntelFsp/FSP/ 82 83 If unsure, say Y. 84 85config FSP_HEADER_PATH 86 string "Location of FSP headers" if !FSP_USE_REPO 87 help 88 Include directory with the FSP ABI header files. 89 90config ADD_FSP_BINARIES 91 bool "Add Intel FSP 2.0 binaries to CBFS" if !FSP_USE_REPO 92 default y if FSP_USE_REPO 93 help 94 Add the FSP-M and FSP-S binaries to CBFS. 95 96config PLATFORM_USES_SECOND_FSP 97 bool 98 default n 99 help 100 The platform uses two sets of FSP-M/FSP-S binaries and selects the 101 appropriate one at runtime. At least one platform requires different 102 binaries depending on CPU stepping, so supporting any stepping 103 requires embedding two FSPs. The platform indicates which is the 104 "first" and "second" FSP. 105 106config FSP_T_CBFS 107 string "Name of FSP-T in CBFS" 108 depends on FSP_CAR 109 default "fspt.bin" 110 111config FSP_T_LOCATION 112 hex 113 default 0xfffe0000 114 help 115 The location for FSP-T. 116 117config FSP_S_CBFS 118 string "Name of FSP-S in CBFS" 119 default "fsps.bin" 120 121config FSP_M_CBFS 122 string "Name of FSP-M in CBFS" 123 default "fspm.bin" 124 125config FSP_FULL_FD 126 bool "Use a combined FSP FD file" if !FSP_USE_REPO 127 depends on ADD_FSP_BINARIES 128 help 129 Use a combined FSP FD file instead of specifying individual, already split 130 binaries and split the file at build-time. 131 132config FSP_FD_PATH 133 string "Location of FSP FD file" if FSP_FULL_FD && !FSP_USE_REPO 134 help 135 Path to the FSP FD file that contains the individual FSP-T, FSP-M 136 and FSP-S binaries. The file gets split at build-time. 137 138config FSP_T_FILE 139 string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_FULL_FD 140 depends on ADD_FSP_BINARIES 141 depends on FSP_CAR 142 default "\$(obj)/Fsp_T.fd" if FSP_FULL_FD 143 help 144 The path and filename of the Intel FSP-T binary for this platform. 145 146config FSP_M_FILE 147 string "Intel FSP-M (memory init) binary path and filename" if !FSP_FULL_FD 148 depends on ADD_FSP_BINARIES 149 default "\$(obj)/Fsp_M.fd" if FSP_FULL_FD 150 help 151 The path and filename of the Intel FSP-M binary for this platform. 152 153config FSP_S_FILE 154 string "Intel FSP-S (silicon init) binary path and filename" if !FSP_FULL_FD 155 depends on ADD_FSP_BINARIES 156 default "\$(obj)/Fsp_S.fd" if FSP_FULL_FD 157 help 158 The path and filename of the Intel FSP-S binary for this platform. 159 160if PLATFORM_USES_SECOND_FSP 161 162config FSP_S_CBFS_2 163 string "Name of the second FSP-S in CBFS" 164 default "fsps_2.bin" 165 166config FSP_M_CBFS_2 167 string "Name of the second FSP-M in CBFS" 168 default "fspm_2.bin" 169 170config FSP_FD_PATH_2 171 string "Location of the second FSP FD file" if FSP_FULL_FD && !FSP_USE_REPO 172 help 173 Path to the FSP FD file that contains the individual FSP-M and FSP-S 174 binaries. The file gets split at build-time. 175 176config FSP_M_FILE_2 177 string "Intel FSP-M (memory init) second binary path and filename" if !FSP_FULL_FD 178 depends on ADD_FSP_BINARIES 179 default "\$(obj)/Fsp_2_M.fd" if FSP_FULL_FD 180 help 181 The path and filename of the second Intel FSP-M binary for this 182 platform. 183 184config FSP_S_FILE_2 185 string "Intel FSP-S (silicon init) second binary path and filename" if !FSP_FULL_FD 186 depends on ADD_FSP_BINARIES 187 default "\$(obj)/Fsp_2_S.fd" if FSP_FULL_FD 188 help 189 The path and filename of the second Intel FSP-S binary for this 190 platform. 191 192endif 193 194config FSP_CAR 195 bool 196 default n 197 select NO_CBFS_MCACHE if !NO_FSP_TEMP_RAM_EXIT 198 help 199 Use FSP APIs to initialize & Tear Down the Cache-As-Ram 200 201config FSP_T_RESERVED_SIZE 202 hex 203 default 0x100 if FSP_CAR 204 default 0x0 205 help 206 This is the size of the area reserved by FSP-T. This is not 207 defined in the FSP specification but in the SOC integration 208 guides. 209 210config NO_FSP_TEMP_RAM_EXIT 211 bool 212 depends on FSP_CAR 213 help 214 Select this on a platform where you want to use FSP-T but use 215 coreboot code to tear down CAR. 216 217config FSP_M_XIP 218 bool 219 default n 220 help 221 Select this value when FSP-M is execute-in-place. 222 223config FSP_T_XIP 224 bool 225 default n 226 help 227 Select this value when FSP-T is execute-in-place. 228 229config FSP_USES_CB_STACK 230 bool 231 default n 232 help 233 Enable support for fsp to use same stack as coreboot. 234 This option allows fsp to continue using coreboot stack 235 without reinitializing stack pointer. This feature is 236 supported Icelake onwards. 237 238config FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND 239 bool 240 help 241 Starting with Intel CPX there is a bug in there reference code during 242 the pipe init. This code synchronises the CAR between sockets in FSP-M. 243 This code implicitly assumes that the FSP heap is right above the 244 RC heap, where both of them are located at the bottom part of CAR. 245 Select this to have an explicit handling of the FSP StackBase to work 246 around this issue. This is needed on multi-socket Xeon-SP systems. 247 This will place the FSP heap right above the FSP-M RC heap. 248 249config FSP_TEMP_RAM_SIZE 250 hex 251 help 252 The amount of memory coreboot reserves for the FSP to use. In the 253 case of FSP 2.1 and newer that share the stack with coreboot instead 254 of having its own stack, this is the amount of anticipated heap usage 255 in CAR by FSP to setup HOB and needs to be the recommended value from 256 the Platform FSP integration guide. In the case of the FSP having its 257 own stack that will be placed in DRAM and not in CAR, this is the 258 amount of memory the FSP needs for its stack and heap. 259 260config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS 261 bool 262 help 263 This is selected by SoC or mainboard to supply their own 264 concept of a version for the memory settings respectively. 265 This allows deployed systems to bump their version number 266 with the same FSP which will trigger a retrain of the memory. 267 268config HAVE_FSP_LOGO_SUPPORT 269 bool 270 default n 271 272config BMP_LOGO 273 bool "Enable logo" 274 default n 275 depends on HAVE_FSP_LOGO_SUPPORT 276 help 277 Uses the FSP to display the boot logo. This method supports a 278 BMP file only. The uncompressed size can be up to 1 MB. The logo can 279 be compressed based on either `BMP_LOGO_COMPRESS_*` configs (default LZMA). 280 281config HAVE_BMP_LOGO_COMPRESS_LZMA 282 bool 283 depends on BMP_LOGO 284 default y 285 286choice 287 prompt "BMP Logo compression" 288 depends on BMP_LOGO 289 default BMP_LOGO_COMPRESS_LZMA if HAVE_BMP_LOGO_COMPRESS_LZMA 290 default BMP_LOGO_COMPRESS_LZ4 291 292config BMP_LOGO_COMPRESS_LZMA 293 bool "Use LZMA compression for BMP logo" 294 help 295 This option enables the use of LZMA compression for the BMP logo. 296 LZMA is a lossless compression algorithm that can significantly reduce 297 the size of the logo, without sacrificing quality. 298 299 If this option is not enabled, the BMP logo will be uncompressed. 300 301config BMP_LOGO_COMPRESS_LZ4 302 bool "Compress BMP logo using LZ4" 303 help 304 This option enables compression of the BMP logo using the LZ4 algorithm. 305 Although the size reduction is not as efficient as LZMA compression, however, 306 it can also make the boot process slightly faster compared to the LZMA. 307 308endchoice 309 310config FSP2_0_LOGO_FILE_NAME 311 string "Logo file" 312 depends on BMP_LOGO 313 default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp" 314 315config FSP_COMPRESS_FSP_S_LZMA 316 bool 317 318config FSP_COMPRESS_FSP_S_LZ4 319 bool 320 321config FSP_COMPRESS_FSP_M_LZMA 322 bool 323 depends on !FSP_M_XIP 324 325config FSP_COMPRESS_FSP_M_LZ4 326 bool 327 depends on !FSP_M_XIP 328 329config FSP_ALIGNMENT_FSP_S 330 int 331 help 332 Sets the CBFS alignment for FSP-S 333 334config FSP_ALIGNMENT_FSP_M 335 int 336 help 337 Sets the CBFS alignment for FSP-M 338 339config FSP_M_ADDR 340 hex 341 help 342 The address FSP-M will be relocated to during build time 343 344config FSP_STATUS_GLOBAL_RESET_REQUIRED_3 345 bool 346 help 347 FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 348 349config FSP_STATUS_GLOBAL_RESET_REQUIRED_4 350 bool 351 help 352 FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 353 354config FSP_STATUS_GLOBAL_RESET_REQUIRED_5 355 bool 356 help 357 FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 358 359config FSP_STATUS_GLOBAL_RESET_REQUIRED_6 360 bool 361 help 362 FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 363 364config FSP_STATUS_GLOBAL_RESET_REQUIRED_7 365 bool 366 help 367 FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 368 369config FSP_STATUS_GLOBAL_RESET_REQUIRED_8 370 bool 371 help 372 FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 373 374config FSP_STATUS_GLOBAL_RESET 375 hex 376 depends on SOC_INTEL_COMMON_FSP_RESET 377 default 0x40000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3 378 default 0x40000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4 379 default 0x40000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5 380 default 0x40000006 if FSP_STATUS_GLOBAL_RESET_REQUIRED_6 381 default 0x40000007 if FSP_STATUS_GLOBAL_RESET_REQUIRED_7 382 default 0x40000008 if FSP_STATUS_GLOBAL_RESET_REQUIRED_8 383 default 0xffffffff 384 help 385 If global reset is supported by SoC then select the correct status value for global 386 reset type from SoC Kconfig based on available Kconfig options 387 FSP_STATUS_GLOBAL_RESET_REQUIRED_X. Default is unsupported. 388 389config SOC_INTEL_COMMON_FSP_RESET 390 bool 391 help 392 Common code block to handle platform reset request raised by FSP. The FSP 393 will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that 394 a reset is required. 395 396config FSPS_HAS_ARCH_UPD 397 bool 398 help 399 SoC users must select this Kconfig if the `FSPS_UPD` header has architecture 400 UPD structure as `FSPS_ARCH_UPD`. Typically, platform with FSP 2.2 specification 401 onwards has support for `FSPS_ARCH_UPD` section as part of `FSPS_UPD` structure. 402 But there are some exceptions as in TGL, JSL, XEON_SP FSP header doesn't have 403 support for FSPS_ARCH_UPD. 404 405config FSPS_USE_MULTI_PHASE_INIT 406 bool 407 help 408 SoC users to select this Kconfig to set EnableMultiPhaseSiliconInit to enable and 409 execute FspMultiPhaseSiInit() API. 410 411config USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 412 bool 413 help 414 The FSP API is used to notify the FSP about different phases in the boot process. 415 The current FSP specification supports three notify phases: 416 - Post PCI enumeration 417 - Ready to Boot 418 - End of Firmware 419 This option allows FSP to execute Notify Phase API (Post PCI enumeration). 420 SoC users can override this config to use coreboot native implementations 421 to perform the required lock down and chipset register configuration prior 422 to executing any 3rd-party code during PCI enumeration (i.e. Option ROM). 423 424 coreboot native implementation to skip FSP Notify Phase (Post PCI enumeration) 425 is still WIP. 426 427config USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 428 bool 429 help 430 The FSP API is used to notify the FSP about different phases in the boot process. 431 The current FSP specification supports three notify phases: 432 - Post PCI enumeration 433 - Ready to Boot 434 - End of Firmware 435 This option allows FSP to execute Notify Phase API (Ready to Boot). 436 SoC users can override this config to use coreboot native implementations 437 to perform the required lock down and chipset register configuration prior 438 boot to payload. 439 440config USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE 441 bool 442 help 443 The FSP API is used to notify the FSP about different phases in the boot process. 444 The current FSP specification supports three notify phases: 445 - Post PCI enumeration 446 - Ready to Boot 447 - End of Firmware 448 This option allows FSP to execute Notify Phase API (End of Firmware). 449 SoC users can override this config to use coreboot native implementations 450 to perform the required lock down and chipset register configuration prior 451 boot to payload. 452 453config FSP_USES_CB_DEBUG_EVENT_HANDLER 454 bool 455 default n 456 help 457 This option allows to create `Debug Event Handler` to print FSP debug messages 458 to output device using coreboot native implementation. 459 460config DISPLAY_FSP_TIMESTAMPS 461 bool "Display FSP Timestamps" 462 default n 463 help 464 Select this config to retrieve FSP timestamps from Firmware Performance Data Table 465 (FPDT) and display from ramstage after FSP-S is executed. 466 467 To be able to use this, FSP has to be compiled with `PcdFspPerformanceEnable` set to 468 `TRUE`. 469 470config FSP_ENABLE_SERIAL_DEBUG 471 bool "Output FSP debug messages on serial console" 472 default y 473 depends on FSP_USES_CB_DEBUG_EVENT_HANDLER 474 help 475 Output FSP debug messages on serial console. 476 477 The config option is selected based on your FSP configuration i.e., debug or 478 release. Enable this option from site-local to print FSP serial messages using 479 coreboot native debug driver when coreboot has integrated the debug FSP 480 binaries. coreboot disables serial messages when this config is not enabled. 481 482config FSP_NVS_DATA_POST_SILICON_INIT 483 bool 484 default n 485 help 486 Select this config to enable the workaround for Intel SoC platforms that 487 do not adhere to the FSP 2.x specification requirement, where the FSP 488 Silicon Init API produces Non-Volatile Storage (NVS) data instead of the 489 FSP-Memory Init API. 490 491 According to the FSP 2.x specification (section 11.3), the FSP populates the 492 NVS data using the FSP_NON_VOLATILE_STORAGE_HOB and expects the boot firmware 493 to parse the FSP_NON_VOLATILE_STORAGE_HOB after the FspMemoryInit() API in API 494 mode. 495 496 However, not all Intel SoC platforms that support the FSP 2.x specification 497 adhere to this requirement. For example, the FSP binary for XEON SP platform 498 produces NVS data (aka FSP_NON_VOLATILE_STORAGE_HOB) after the FspSiliconInit() 499 API. Therefore, attempting to locate NVS data after the FspMemoryInit() API on 500 these platforms would result in an error. Use this config to find the NVS data 501 and store it in Non-Volatile Storage after the FspSiliconInit() API. 502 503config FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN 504 bool 505 default n 506 depends on PLATFORM_USES_FSP2_2 507 help 508 Select this config for Intel SoC platform where FSP MultiPhaseSiInit API is unable 509 to return ERROR status properly. 510 511 The config option will be selected based on the target SoC platform and if the 512 problem existed inside the FSP MultiPhaseSiInit. At present the problem has only 513 reported with Alder Lake and Raptor Lake FSP where MultiPhaseSiInit API is unable 514 to return any ERROR status. 515 516endif 517
