1 /* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_defs.h> 12 #include <plat/arm/board/common/board_css_def.h> 13 #include <plat/arm/board/common/v2m_def.h> 14 #include <plat/arm/common/arm_def.h> 15 #include <plat/arm/common/arm_spm_def.h> 16 #include <plat/arm/css/common/css_def.h> 17 #include <plat/arm/soc/common/soc_css_def.h> 18 #include <plat/common/common_def.h> 19 20 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 21 22 /* 23 * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, 24 * its base is ARM_AP_TZC_DRAM1_BASE. 25 * 26 * Reserve 96 MB below ARM_AP_TZC_DRAM1_BASE for: 27 * - BL32_BASE when SPD_spmd is enabled 28 * - Region to load secure partitions 29 * 30 * 31 * 0x8000_0000 ------------------ TC_NS_DRAM1_BASE 32 * | DTB | 33 * | (32K) | 34 * 0x8000_8000 ------------------ 35 * | NT_FW_CONFIG | 36 * | (4KB) | 37 * 0x8000_9000 ------------------ 38 * | ... | 39 * 0xf8a0_0000 ------------------ TC_NS_FWU_BASE 40 * | FWU shmem | 41 * | (4MB) | 42 * 0xf8e0_0000 ------------------ TC_NS_OPTEE_BASE 43 * | OP-TEE shmem | 44 * | (2MB) | 45 * 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE 46 * | | 47 * | SPMC | 48 * | SP | 49 * | (96MB) | 50 * 0xFF00_0000 ------------------ ARM_AP_TZC_DRAM1_BASE 51 * | AP | 52 * | EL3 Monitor | 53 * | SCP | 54 * | (16MB) | 55 * 0xFFFF_FFFF ------------------ 56 * 57 * 58 */ 59 #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ 60 TC_TZC_DRAM1_SIZE) 61 #define TC_TZC_DRAM1_SIZE (96 * SZ_1M) /* 96 MB */ 62 #define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \ 63 TC_TZC_DRAM1_SIZE - 1) 64 65 #define TC_NS_DRAM1_BASE ARM_DRAM1_BASE 66 #define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 67 ARM_TZC_DRAM1_SIZE - \ 68 TC_TZC_DRAM1_SIZE) 69 #define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - 1) 70 71 #define TC_NS_OPTEE_SIZE (2 * SZ_1M) 72 #define TC_NS_OPTEE_BASE (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - TC_NS_OPTEE_SIZE) 73 #define TC_NS_FWU_SIZE (4 * SZ_1M) 74 #define TC_NS_FWU_BASE (TC_NS_OPTEE_BASE - TC_NS_FWU_SIZE) 75 76 /* 77 * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure) 78 */ 79 #define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 80 TC_NS_DRAM1_BASE, \ 81 TC_NS_DRAM1_SIZE, \ 82 MT_MEMORY | MT_RW | MT_NS) 83 84 85 #define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ 86 TC_TZC_DRAM1_BASE, \ 87 TC_TZC_DRAM1_SIZE, \ 88 MT_MEMORY | MT_RW | MT_SECURE) 89 90 #define PLAT_HW_CONFIG_DTB_BASE TC_NS_DRAM1_BASE 91 #define PLAT_ARM_HW_CONFIG_SIZE ULL(0x8000) 92 93 #define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \ 94 PLAT_HW_CONFIG_DTB_BASE, \ 95 PLAT_ARM_HW_CONFIG_SIZE, \ 96 MT_MEMORY | MT_RO | MT_NS) 97 /* 98 * Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to 99 * max size of BL32 image. 100 */ 101 #if defined(SPD_spmd) 102 #define TC_EL2SPMC_LOAD_ADDR (TC_TZC_DRAM1_BASE + 0x04000000) 103 104 #define PLAT_ARM_SPMC_BASE TC_EL2SPMC_LOAD_ADDR 105 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 106 #endif 107 108 /* 109 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 110 * plat_arm_mmap array defined for each BL stage. 111 */ 112 #if defined(IMAGE_BL31) 113 # if SPM_MM 114 # define PLAT_ARM_MMAP_ENTRIES 9 115 # define MAX_XLAT_TABLES 7 116 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 117 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 118 # else 119 # define PLAT_ARM_MMAP_ENTRIES 8 120 # define MAX_XLAT_TABLES 8 121 # endif 122 #elif defined(IMAGE_BL32) 123 # define PLAT_ARM_MMAP_ENTRIES 8 124 # define MAX_XLAT_TABLES 5 125 #elif !USE_ROMLIB 126 # define PLAT_ARM_MMAP_ENTRIES 11 127 # define MAX_XLAT_TABLES 7 128 #else 129 # define PLAT_ARM_MMAP_ENTRIES 12 130 # define MAX_XLAT_TABLES 6 131 #endif 132 133 /* 134 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 135 * plus a little space for growth. 136 */ 137 #define PLAT_ARM_MAX_BL1_RW_SIZE 0x12000 138 139 /* 140 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 141 */ 142 143 #if USE_ROMLIB 144 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 145 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 146 #else 147 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 148 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 149 #endif 150 151 /* 152 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 153 * little space for growth. Current size is considering that TRUSTED_BOARD_BOOT 154 * and MEASURED_BOOT is enabled. 155 */ 156 # define PLAT_ARM_MAX_BL2_SIZE 0x29000 157 158 159 /* 160 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 161 * calculated using the current BL31 PROGBITS debug size plus the sizes of 162 * BL2 and BL1-RW. Current size is considering that TRUSTED_BOARD_BOOT and 163 * MEASURED_BOOT is enabled. 164 */ 165 #define PLAT_ARM_MAX_BL31_SIZE 0x60000 166 167 /* 168 * Size of cacheable stacks 169 */ 170 #if defined(IMAGE_BL1) 171 # define PLATFORM_STACK_SIZE 0x1000 172 #elif defined(IMAGE_BL2) 173 # define PLATFORM_STACK_SIZE 0x1000 174 #elif defined(IMAGE_BL2U) 175 # define PLATFORM_STACK_SIZE 0x400 176 #elif defined(IMAGE_BL31) 177 # if SPM_MM 178 # define PLATFORM_STACK_SIZE 0x500 179 # else 180 # define PLATFORM_STACK_SIZE 0xa00 181 # endif 182 #elif defined(IMAGE_BL32) 183 # define PLATFORM_STACK_SIZE 0x440 184 #endif 185 186 /* 187 * In the current implementation the RoT Service request that requires the 188 * biggest message buffer is the RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The 189 * maximum required buffer size is calculated based on the platform-specific 190 * needs of this request. 191 */ 192 #define PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE 0x500 193 194 #define TC_DEVICE_BASE 0x21000000 195 #define TC_DEVICE_SIZE 0x5f000000 196 197 #if defined(TARGET_FLAVOUR_FPGA) 198 #undef V2M_FLASH0_BASE 199 #undef V2M_FLASH0_SIZE 200 #define V2M_FLASH0_BASE UL(0x0C000000) 201 #define V2M_FLASH0_SIZE UL(0x02000000) 202 #endif 203 204 // TC_MAP_DEVICE covers different peripherals 205 // available to the platform 206 #define TC_MAP_DEVICE MAP_REGION_FLAT( \ 207 TC_DEVICE_BASE, \ 208 TC_DEVICE_SIZE, \ 209 MT_DEVICE | MT_RW | MT_SECURE) 210 211 212 #define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 213 V2M_FLASH0_SIZE, \ 214 MT_DEVICE | MT_RO | MT_SECURE) 215 216 #define PLAT_ARM_NSTIMER_FRAME_ID 0 217 218 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 219 220 /* PLAT_ARM_TRUSTED_ROM_SIZE 512KB minus ROM base. */ 221 #define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE) 222 223 #define PLAT_ARM_NSRAM_BASE 0x06000000 224 #if TARGET_FLAVOUR_FVP 225 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ 226 #else /* TARGET_FLAVOUR_FPGA */ 227 #define PLAT_ARM_NSRAM_SIZE 0x00008000 /* 64KB */ 228 #endif /* TARGET_FLAVOUR_FPGA */ 229 230 #if TARGET_PLATFORM <= 2 231 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 232 #elif TARGET_PLATFORM == 3 233 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 234 #endif /* TARGET_PLATFORM == 3 */ 235 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 236 #define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL) 237 238 #define TC_NS_MTE_SIZE (256 * SZ_1M) 239 /* the SCP puts the carveout at the end of DRAM2 */ 240 #define TC_NS_DRAM2_SIZE (PLAT_ARM_DRAM2_SIZE - TC_NS_MTE_SIZE) 241 242 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp) 243 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \ 244 INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \ 245 GIC_HIGHEST_SEC_PRIORITY, grp, \ 246 GIC_INTR_CFG_LEVEL) 247 248 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 249 PLAT_SP_IMAGE_NS_BUF_SIZE) 250 251 #define PLAT_ARM_SP_MAX_SIZE U(0x2000000) 252 253 /******************************************************************************* 254 * Memprotect definitions 255 ******************************************************************************/ 256 /* PSCI memory protect definitions: 257 * This variable is stored in a non-secure flash because some ARM reference 258 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 259 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 260 */ 261 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 262 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 263 264 /* Secure Watchdog Constants */ 265 #define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000) 266 #define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000) 267 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 268 #define SBSA_SECURE_WDOG_INTID 86 269 270 #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 271 272 /* Index of SDS region used in the communication with SCP */ 273 #define SDS_SCP_AP_REGION_ID U(0) 274 /* Index of SDS region used in the communication with RSE */ 275 #define SDS_RSE_AP_REGION_ID U(1) 276 /* 277 * Memory region for RSE's shared data storage (SDS) 278 * It is placed right after the SCMI payload area. 279 */ 280 #define PLAT_ARM_RSE_AP_SDS_MEM_BASE (CSS_SCMI_PAYLOAD_BASE + \ 281 CSS_SCMI_PAYLOAD_SIZE_MAX) 282 283 #define PLAT_ARM_CLUSTER_COUNT U(1) 284 #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 285 #define PLAT_MAX_CPUS_PER_CLUSTER U(14) 286 #else /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */ 287 #define PLAT_MAX_CPUS_PER_CLUSTER U(8) 288 #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */ 289 #define PLAT_MAX_PE_PER_CPU U(1) 290 291 #define PLATFORM_CORE_COUNT (PLAT_MAX_CPUS_PER_CLUSTER * PLAT_ARM_CLUSTER_COUNT) 292 293 /* Message Handling Unit (MHU) base addresses */ 294 #if TARGET_PLATFORM <= 2 295 #define PLAT_CSS_MHU_BASE UL(0x45400000) 296 #elif TARGET_PLATFORM == 3 297 #define PLAT_CSS_MHU_BASE UL(0x46000000) 298 #endif /* TARGET_PLATFORM == 3 */ 299 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 300 301 /* TC2: AP<->RSE MHUs */ 302 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x2A840000) 303 #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x2A850000) 304 305 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 306 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 307 308 /* 309 * Physical and virtual address space limits for MMU in AARCH64 310 */ 311 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 312 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 313 314 /* GIC related constants */ 315 #define PLAT_ARM_GICD_BASE UL(0x30000000) 316 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 317 #define PLAT_ARM_GICR_BASE UL(0x30080000) 318 319 /* 320 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 321 * SCP_BL2 size plus a little space for growth. 322 */ 323 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x20000 324 325 /* 326 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 327 * SCP_BL2U size plus a little space for growth. 328 */ 329 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000 330 331 /* TZC Related Constants */ 332 #define PLAT_ARM_TZC_BASE UL(0x25000000) 333 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 334 335 #define TZC400_OFFSET UL(0x1000000) 336 #define TZC400_COUNT 4 337 338 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 339 (n * TZC400_OFFSET)) 340 341 #define TZC_NSAID_DEFAULT U(0) 342 343 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 344 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT)) 345 346 /* 347 * The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to 348 * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as 349 * secure. The second and third regions gives non secure access to rest of DRAM. 350 */ 351 #define TC_TZC_REGIONS_DEF \ 352 {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \ 353 TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 354 {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 355 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 356 {PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END, \ 357 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} 358 359 /* virtual address used by dynamic mem_protect for chunk_base */ 360 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 361 362 #if ARM_GPT_SUPPORT 363 /* 364 * This overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT in board_css_def.h. 365 * Offset of the FIP in the GPT image. BL1 component uses this option 366 * as it does not load the partition table to get the FIP base 367 * address. At sector 48 for TC to align with ATU page size boundaries (8KiB) 368 * (i.e. after reserved sectors 0-47). 369 * Offset = 48 * 512 = 0x6000 370 */ 371 #undef PLAT_ARM_FIP_OFFSET_IN_GPT 372 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x6000 373 #endif /* ARM_GPT_SUPPORT */ 374 375 /* UART related constants */ 376 377 #define TC_UART0 0x2a400000 378 #define TC_UART1 0x2a410000 379 380 /* 381 * TODO: if any more undefs are needed, it's better to consider dropping the 382 * board_css_def.h include above 383 */ 384 #undef PLAT_ARM_BOOT_UART_BASE 385 #undef PLAT_ARM_RUN_UART_BASE 386 387 #undef PLAT_ARM_CRASH_UART_BASE 388 #undef PLAT_ARM_BOOT_UART_CLK_IN_HZ 389 #undef PLAT_ARM_RUN_UART_CLK_IN_HZ 390 391 #if TARGET_FLAVOUR_FVP 392 #define PLAT_ARM_BOOT_UART_BASE TC_UART1 393 #define TC_UARTCLK 7372800 394 #else /* TARGET_FLAVOUR_FPGA */ 395 #define PLAT_ARM_BOOT_UART_BASE TC_UART0 396 #if TARGET_PLATFORM <= 2 397 #define TC_UARTCLK 5000000 398 #elif TARGET_PLATFORM >= 3 399 #define TC_UARTCLK 3750000 400 #endif /* TARGET_PLATFORM >= 3 */ 401 #undef ARM_CONSOLE_BAUDRATE 402 #define ARM_CONSOLE_BAUDRATE 38400 403 #endif /* TARGET_FLAVOUR_FPGA */ 404 405 #define PLAT_ARM_RUN_UART_BASE TC_UART0 406 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 407 408 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK 409 #define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK 410 411 #endif /* PLATFORM_DEF_H */ 412