Home
last modified time | relevance | path

Searched defs:PM1_STS (Results 1 – 20 of 20) sorted by relevance

/aosp_15_r20/external/coreboot/src/southbridge/intel/common/
H A Dpmutil.h36 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/southbridge/intel/i82371eb/
H A Di82371eb.h66 #define PM1_STS (1<<6) macro
/aosp_15_r20/external/coreboot/src/soc/intel/xeon_sp/include/soc/
H A Dpm.h13 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/southbridge/intel/i82801dx/
H A Di82801dx.h79 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/soc/intel/broadwell/include/soc/
H A Dpm.h10 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/soc/intel/cannonlake/include/soc/
H A Dpm.h6 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/soc/intel/alderlake/include/soc/
H A Dpm.h12 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/soc/intel/elkhartlake/include/soc/
H A Dpm.h6 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/soc/intel/tigerlake/include/soc/
H A Dpm.h12 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/soc/intel/jasperlake/include/soc/
H A Dpm.h6 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/soc/intel/meteorlake/include/soc/
H A Dpm.h6 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/soc/intel/apollolake/include/soc/
H A Dpm.h13 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/soc/intel/skylake/include/soc/
H A Dpm.h15 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/soc/intel/braswell/include/soc/
H A Dpm.h121 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/soc/intel/denverton_ns/include/soc/
H A Dpmc.h53 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/southbridge/intel/i82801gx/
H A Di82801gx.h260 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/soc/intel/baytrail/include/soc/
H A Dpm.h122 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/southbridge/intel/ibexpeak/
H A Dpch.h384 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/southbridge/intel/bd82x6x/
H A Dpch.h432 #define PM1_STS 0x00 macro
/aosp_15_r20/external/coreboot/src/southbridge/intel/lynxpoint/
H A Dpch.h635 #define PM1_STS 0x00 macro