1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _DENVERTON_NS_PMC_H_ 4 #define _DENVERTON_NS_PMC_H_ 5 6 #include <soc/intel/common/tco.h> 7 8 /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ 9 #define PMC_ACPI_BASE 0x40 /* IO BAR */ 10 #define MASK_PMC_ACPI_BASE 0xfffc 11 #define PMC_ACPI_CNT 0x44 12 #define PMC_ACPI_CNT_PWRM_EN (1 << 8) /* PWRM enable */ 13 #define PMC_ACPI_CNT_ACPI_EN (1 << 7) /* ACPI enable */ 14 #define PMC_ACPI_CNT_SCIS ((1 << 2) | (1 << 1) | (1 << 0)) /* SCI IRQ select \ 15 */ 16 #define PMC_ACPI_CNT_SCIS_MASK 0x07 17 #define PMC_ACPI_CNT_SCIS_IRQ9 0x00 18 #define PMC_ACPI_CNT_SCIS_IRQ10 0x01 19 #define PMC_ACPI_CNT_SCIS_IRQ11 0x02 20 #define PMC_ACPI_CNT_SCIS_DISABLE 0x03 21 #define PMC_ACPI_CNT_SCIS_IRQ20 0x04 22 #define PMC_ACPI_CNT_SCIS_IRQ21 0x05 23 #define PMC_ACPI_CNT_SCIS_IRQ22 0x06 24 #define PMC_ACPI_CNT_SCIS_IRQ23 0x07 25 26 #define SCI_IRQ_ADJUST 0 27 #define SCI_IRQ_SEL (0x07 << SCI_IRQ_ADJUST) 28 #define SCIS_IRQ9 0x00 29 #define SCIS_IRQ10 0x01 30 #define SCIS_IRQ11 0x02 31 #define SCIS_IRQ20 0x04 32 #define SCIS_IRQ21 0x05 33 #define SCIS_IRQ22 0x06 34 #define SCIS_IRQ23 0x07 35 36 #define PMC_PWRM_BASE 0x48 /* MEM BAR */ 37 #define MASK_PMC_PWRM_BASE 0xfffff000 /* 4K alignment */ 38 #define GEN_PMCON_A 0xA0 39 #define MS4V (1 << 18) 40 #define GBL_RST_STS (1 << 16) 41 #define GEN_PMCON_B 0xA4 42 #define GEN_PMCON_B_SUS_PWR_FLR 0x4000 43 #define SUS_PWR_FLR GEN_PMCON_B_SUS_PWR_FLR 44 #define GEN_PMCON_B_RTC_PWR_STS 0x04 45 #define GEN_PMCON_B_PWR_FLR 0x02 46 #define PWR_FLR GEN_PMCON_B_PWR_FLR 47 #define GEN_PMCON_B_AFTERG3_EN 0x00 48 #define ETR3 0xAC 49 #define ETR3_CF9LOCK BIT31 ///< CF9h Lockdown 50 #define ETR3_CF9GR BIT20 ///< CF9h Global Reset 51 52 /* IO Mapped registers behind ACPI_BASE_ADDRESS */ 53 #define PM1_STS 0x00 54 #define WAK_STS (1 << 15) 55 #define PCIEXPWAK_STS (1 << 14) 56 #define PRBTNOR_STS (1 << 11) 57 #define RTC_STS (1 << 10) 58 #define PWRBTN_STS (1 << 8) 59 #define GBL_STS (1 << 5) 60 #define BM_STS (1 << 4) 61 #define TMROF_STS (1 << 0) 62 #define PM1_EN 0x02 63 #define PCIEXPWAK_DIS (1 << 14) 64 #define RTC_EN (1 << 10) 65 #define PWRBTN_EN (1 << 8) 66 #define GBL_EN (1 << 5) 67 #define TMROF_EN (1 << 0) 68 #define PM1_CNT 0x04 69 #define SLP_EN (1 << 13) 70 #define SLP_TYP_SHIFT 10 71 #define SLP_TYP (7 << SLP_TYP_SHIFT) 72 #define SLP_TYP_S0 0 73 #define SLP_TYP_S1 1 74 #define SLP_TYP_S3 5 75 #define SLP_TYP_S4 6 76 #define SLP_TYP_S5 7 77 #define GBL_RLS (1 << 2) 78 #define BM_RLD (1 << 1) 79 #define SCI_EN (1 << 0) 80 #define PM1_TMR 0x08 81 #define SMI_EN 0x30 82 #define LEGACY_USB3_EN (1 << 31) // Legacy USB3 SMI logic 83 #define GPIO_UNLOCK_EN (1 << 27) // GPIO unlock SMI 84 #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic 85 #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic 86 #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS 87 #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) 88 #define MCSMI_EN (1 << 11) // Trap microcontroller range access 89 #define BIOS_RLS (1 << 7) // asserts SCI on bit set 90 #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set 91 #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# 92 #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# 93 #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic 94 #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit 95 #define EOS (1 << 1) // End of SMI (deassert SMI#) 96 #define GBL_SMI_EN (1 << 0) // SMI# generation at all? 97 #define SMI_STS 0x34 98 #define SMI_STS_LEGACY_USB3 (1 << 31) 99 #define SMI_STS_GPIO_UNLOCK (1 << 27) 100 #define SMI_STS_SPI (1 << 26) 101 #define SMI_STS_MONITOR (1 << 21) 102 #define SMI_STS_PCI_EXP (1 << 20) 103 #define SMI_STS_PATCH (1 << 19) 104 #define SMI_STS_INTEL_USB2 (1 << 18) 105 #define SMI_STS_LEGACY_USB2 (1 << 17) 106 #define SMI_STS_SMBUS (1 << 16) 107 #define SMI_STS_SERIRQ (1 << 15) 108 #define SMI_STS_PERIODIC (1 << 14) 109 #define SMI_STS_TCO (1 << 13) 110 #define SMI_STS_DEVMON (1 << 12) 111 #define SMI_STS_MCSMI (1 << 11) 112 #define SMI_STS_GPE1 (1 << 10) 113 #define SMI_STS_GPE0 (1 << 9) 114 #define SMI_STS_PM1 (1 << 8) 115 #define SMI_STS_SWSMI_TMR (1 << 6) 116 #define SMI_STS_APMC (1 << 5) 117 #define SMI_STS_SLP_SMI (1 << 4) 118 #define SMI_STS_LEGACY_USB (1 << 3) 119 #define SMI_STS_BIOS (1 << 2) 120 #define GPE_CTRL 0x40 121 #define SWGPE_CTRL (1 << 17) 122 #define PM2_CNT 0x50 123 #define GPE0_REG_MAX 4 124 #define GPE0_REG_SIZE 32 125 #define GPE0_STS(x) (0x80 + (x * 4)) 126 #define GPE_STD 0 127 #define GPIO31_STS (1 << 31) 128 #define GPIO30_STS (1 << 30) 129 #define GPIO29_STS (1 << 29) 130 #define GPIO28_STS (1 << 28) 131 #define GPIO27_STS (1 << 27) 132 #define GPIO26_STS (1 << 26) 133 #define GPIO25_STS (1 << 25) 134 #define GPIO24_STS (1 << 24) 135 #define GPIO23_STS (1 << 23) 136 #define GPIO22_STS (1 << 22) 137 #define GPIO21_STS (1 << 21) 138 #define GPIO20_STS (1 << 20) 139 #define GPIO19_STS (1 << 19) 140 #define GPIO18_STS (1 << 18) 141 #define GPIO17_STS (1 << 17) 142 #define GPIO16_STS (1 << 16) 143 #define GPIO15_STS (1 << 15) 144 #define GPIO14_STS (1 << 14) 145 #define GPIO13_STS (1 << 13) 146 #define GPIO12_STS (1 << 12) 147 #define GPIO11_STS (1 << 11) 148 #define GPIO10_STS (1 << 10) 149 #define GPIO09_STS (1 << 09) 150 #define GPIO08_STS (1 << 08) 151 #define GPIO07_STS (1 << 07) 152 #define GPIO06_STS (1 << 06) 153 #define GPIO05_STS (1 << 05) 154 #define GPIO04_STS (1 << 04) 155 #define GPIO03_STS (1 << 03) 156 #define GPIO02_STS (1 << 02) 157 #define GPIO01_STS (1 << 01) 158 #define GPIO00_STS (1 << 00) 159 #define GPE0_STS_63_32 0x84 160 #define GPE0_STS_95_64 0x88 161 #define GPE0_STS_127_96 0x8c 162 #define PME_B0_STS (1 << 13) 163 #define ME_SCI_STS (1 << 12) 164 #define PME_STS (1 << 11) 165 #define PCI_EXP_STS (1 << 9) 166 #define RI_STS (1 << 8) 167 #define SMB_WAK_STS (1 << 7) 168 #define TCOSCI_STS (1 << 6) 169 #define IE_SCI_STS (1 << 3) 170 #define SWGPE_STS (1 << 2) 171 #define HOT_PLUG_STS (1 << 1) 172 #define GPE0_EN(x) (0x90 + (x * 4)) 173 #define GPIO31_EN (1 << 31) 174 #define GPIO30_EN (1 << 30) 175 #define GPIO29_EN (1 << 29) 176 #define GPIO28_EN (1 << 28) 177 #define GPIO27_EN (1 << 27) 178 #define GPIO26_EN (1 << 26) 179 #define GPIO25_EN (1 << 25) 180 #define GPIO24_EN (1 << 24) 181 #define GPIO23_EN (1 << 23) 182 #define GPIO22_EN (1 << 22) 183 #define GPIO21_EN (1 << 21) 184 #define GPIO20_EN (1 << 20) 185 #define GPIO19_EN (1 << 19) 186 #define GPIO18_EN (1 << 18) 187 #define GPIO17_EN (1 << 17) 188 #define GPIO16_EN (1 << 16) 189 #define GPIO15_EN (1 << 15) 190 #define GPIO14_EN (1 << 14) 191 #define GPIO13_EN (1 << 13) 192 #define GPIO12_EN (1 << 12) 193 #define GPIO11_EN (1 << 11) 194 #define GPIO10_EN (1 << 10) 195 #define GPIO09_EN (1 << 09) 196 #define GPIO08_EN (1 << 08) 197 #define GPIO07_EN (1 << 07) 198 #define GPIO06_EN (1 << 06) 199 #define GPIO05_EN (1 << 05) 200 #define GPIO04_EN (1 << 04) 201 #define GPIO03_EN (1 << 03) 202 #define GPIO02_EN (1 << 02) 203 #define GPIO01_EN (1 << 01) 204 #define GPIO00_EN (1 << 00) 205 #define GPE0_EN_63_32 0x94 206 #define GPE0_EN_95_64 0x98 207 #define GPE0_EN_127_96 0x9c 208 #define PME_B0_EN (1 << 13) 209 #define ME_SCI_EN (1 << 12) 210 #define PME_EN (1 << 11) 211 #define PCI_EXP_EN (1 << 9) 212 #define RI_EN (1 << 8) 213 #define SMB_WAK_EN (1 << 7) 214 #define TCOSCI_EN (1 << 6) 215 #define IE_SCI_EN (1 << 3) 216 #define SWGPE_EN (1 << 2) 217 #define HOT_PLUG_EN (1 << 1) 218 219 /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ 220 #define PRSTS 0x10 221 #define GPIO_GPE_CFG 0x120 222 #define GPE0_DWX_MASK 0x7 223 #define GPE0_DW_SHIFT(x) (4 + 4*(x)) 224 #define PCH_PWRM_ACPI_TMR_CTL 0xfc 225 #define ACPI_TIM_DIS (1 << 1) 226 227 /* I/O ports */ 228 #define RST_CNT 0xcf9 229 #define FULL_RST (1 << 3) 230 #define RST_CPU (1 << 2) 231 #define SYS_RST (1 << 1) 232 233 #endif /* _DENVERTON_NS_PMC_H_ */ 234