1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _DENVERTON_NS_PCI_DEVS_H_ 4 #define _DENVERTON_NS_PCI_DEVS_H_ 5 6 #include <device/pci_def.h> 7 8 /* All these devices live on bus 0 with the associated device and function */ 9 10 #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_##slot, func) 11 12 #if !defined(__SIMPLE_DEVICE__) 13 #include <device/device.h> 14 #define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) 15 #else 16 #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_##slot, func) 17 #endif 18 19 /* SoC transaction router */ 20 #define SA_DEV_SLOT_ROOT 0x0 21 #define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) 22 #if defined(__SIMPLE_DEVICE__) 23 #define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) 24 #else 25 #include <device/device.h> 26 #define SA_DEV_ROOT pcidev_path_on_root(PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)) 27 #endif 28 #define SA_DEV 0x0 29 #define SA_FUNC 0 30 #define SOC_DEV SA_DEV 31 #define SOC_FUNC SA_FUNC 32 33 /* RAS */ 34 #define RAS_DEV 0x4 35 #define RAS_FUNC 0 36 37 /* Root Complex Event Collector */ 38 #define PCH_DEV_SLOT_RCEC 0x5 39 #define PCH_DEVFN_RCEC _PCH_DEVFN(RCEC, 0) 40 #define PCH_DEV_RCEC _PCH_DEV(RCEC, 0) 41 #define RCEC_DEV 0x5 42 #define RCEC_FUNC 0 43 44 /* Virtual Root Port 2 */ 45 #define PCH_DEV_SLOT_QAT 0x6 46 #define PCH_DEVFN_QAT _PCH_DEVFN(QAT, 0) 47 #define PCH_DEV_QAT _PCH_DEV(QAT, 0) 48 #define VRP2_DEV 0x6 49 #define VRP2_FUNC 0 50 51 /* PCIe Root Ports */ 52 #define PCH_DEV_SLOT_PCIE1 0x9 53 #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE1, 0) 54 #define PCH_DEV_PCIE1 _PCH_DEV(PCIE1, 0) 55 #define PCH_DEV_SLOT_PCIE2 0xa 56 #define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE2, 0) 57 #define PCH_DEV_PCIE2 _PCH_DEV(PCIE2, 0) 58 #define PCH_DEV_SLOT_PCIE3 0xb 59 #define PCH_DEVFN_PCIE3 _PCH_DEVFN(PCIE3, 0) 60 #define PCH_DEV_PCIE3 _PCH_DEV(PCIE3, 0) 61 #define PCH_DEV_SLOT_PCIE4 0xc 62 #define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE4, 0) 63 #define PCH_DEV_PCIE4 _PCH_DEV(PCIE4, 0) 64 #define PCH_DEV_SLOT_PCIE5 0xe 65 #define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE5, 0) 66 #define PCH_DEV_PCIE5 _PCH_DEV(PCIE5, 0) 67 #define PCH_DEV_SLOT_PCIE6 0xf 68 #define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE6, 0) 69 #define PCH_DEV_PCIE6 _PCH_DEV(PCIE6, 0) 70 #define PCH_DEV_SLOT_PCIE7 0x10 71 #define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE7, 0) 72 #define PCH_DEV_PCIE7 _PCH_DEV(PCIE7, 0) 73 #define PCH_DEV_SLOT_PCIE8 0x11 74 #define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE8, 0) 75 #define PCH_DEV_PCIE8 _PCH_DEV(PCIE8, 0) 76 77 #define PCIE_DEV 0x09 78 #define MAX_PCIE_PORT 0x8 79 #define PCIE_PORT1_DEV 0x09 80 #define PCIE_PORT1_FUNC 0 81 #define PCIE_PORT2_DEV 0x0a 82 #define PCIE_PORT2_FUNC 0 83 #define PCIE_PORT3_DEV 0x0b 84 #define PCIE_PORT3_FUNC 0 85 #define PCIE_PORT4_DEV 0x0c 86 #define PCIE_PORT4_FUNC 0 87 #define PCIE_PORT5_DEV 0x0e 88 #define PCIE_PORT5_FUNC 0 89 #define PCIE_PORT6_DEV 0x0f 90 #define PCIE_PORT6_FUNC 0 91 #define PCIE_PORT7_DEV 0x10 92 #define PCIE_PORT7_FUNC 0 93 #define PCIE_PORT8_DEV 0x11 94 #define PCIE_PORT8_FUNC 0 95 96 /* SMBUS 2 */ 97 #define PCH_DEV_SLOT_SMBUS_HOST 0x12 98 #define PCH_DEVFN_SMBUS_HOST _PCH_DEVFN(SMBUS_HOST, 0) 99 #define PCH_DEV_SMBUS_HOST _PCH_DEV(SMBUS_HOST, 0) 100 #define SMBUS2_DEV 0x12 101 #define SMBUS2_FUNC 0 102 103 /* SATA */ 104 #define PCH_DEV_SLOT_SATA_0 0x13 105 #define PCH_DEVFN_SATA_0 _PCH_DEVFN(SATA_0, 0) 106 #define PCH_DEV_SATA_0 _PCH_DEV(SATA_0, 0) 107 #define PCH_DEV_SLOT_SATA_1 0x14 108 #define PCH_DEVFN_SATA_1 _PCH_DEVFN(SATA_1, 0) 109 #define PCH_DEV_SATA_1 _PCH_DEV(SATA_1, 0) 110 #define SATA_DEV 0x13 111 #define SATA_FUNC 0 112 #define SATA2_DEV 0x14 113 #define SATA2_FUNC 0 114 115 /* xHCI */ 116 #define PCH_DEV_SLOT_XHCI 0x15 117 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) 118 #define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) 119 #define XHCI_DEV 0x15 120 #define XHCI_FUNC 0 121 122 /* Virtual Root Port 0 */ 123 #define PCH_DEV_SLOT_LAN0 0x16 124 #define PCH_DEVFN_LAN0 _PCH_DEVFN(LAN0, 0) 125 #define PCH_DEV_LAN0 _PCH_DEV(LAN0, 0) 126 #define VRP0_DEV 0x16 127 #define VRP0_FUNC 0 128 129 /* Virtual Root Port 1 */ 130 #define PCH_DEV_SLOT_LAN1 0x17 131 #define PCH_DEVFN_LAN1 _PCH_DEVFN(LAN1, 0) 132 #define PCH_DEV_LAN1 _PCH_DEVFN(LAN1, 0) 133 #define VRP1_DEV 0x17 134 #define VRP1_FUNC 0 135 136 /* CSME */ 137 #define PCH_DEV_SLOT_ME 0x18 138 #define PCH_DEVFN_ME_HECI1 _PCH_DEVFN(ME, 0) 139 #define PCH_DEVFN_ME_HECI2 _PCH_DEVFN(ME, 1) 140 #define PCH_DEVFN_ME_HECI3 _PCH_DEVFN(ME, 4) 141 #define PCH_DEVFN_ME_KT _PCH_DEVFN(ME, 3) 142 #define PCH_DEV_ME_HECI1 _PCH_DEV(ME, 0) 143 #define PCH_DEV_ME_HECI2 _PCH_DEV(ME, 1) 144 #define PCH_DEV_ME_HECI3 _PCH_DEV(ME, 4) 145 #define PCH_DEV_ME_KT _PCH_DEV(ME, 3) 146 147 #define ME_HECI_DEV 0x18 148 #define ME_HECI1_DEV ME_HECI_DEV 149 #define ME_HECI1_FUNC 0 150 #define ME_HECI2_DEV ME_HECI_DEV 151 #define ME_HECI2_FUNC 1 152 #define ME_IEDR_DEV ME_HECI_DEV 153 #define ME_IEDR_FUNC 2 154 #define ME_MEKT_DEV ME_HECI_DEV 155 #define ME_MEKT_FUNC 3 156 #define ME_HECI3_DEV ME_HECI_DEV 157 #define ME_HECI3_FUNC 4 158 159 /* HSUART */ 160 #define PCH_DEV_SLOT_UART 0x1a 161 #define PCH_DEVFN_UART0 _PCH_DEVFN(UART, 0) 162 #define PCH_DEVFN_UART1 _PCH_DEVFN(UART, 1) 163 #define PCH_DEVFN_UART2 _PCH_DEVFN(UART, 2) 164 #define PCH_DEV_UART0 _PCH_DEV(UART, 0) 165 #define PCH_DEV_UART1 _PCH_DEV(UART, 1) 166 #define PCH_DEV_UART2 _PCH_DEV(UART, 2) 167 #define HSUART_DEV 0x1a 168 #define HSUART1_DEV HSUART_DEV 169 #define HSUART1_FUNC 0 170 #define HSUART2_DEV HSUART_DEV 171 #define HSUART2_FUNC 1 172 #define HSUART3_DEV HSUART_DEV 173 #define HSUART3_FUNC 2 174 175 /* IE */ 176 #define PCH_DEV_SLOT_IE 0x1b 177 #define PCH_DEVFN_IE_HECI1 _PCH_DEVFN(IE, 0) 178 #define PCH_DEVFN_IE_HECI2 _PCH_DEVFN(IE, 1) 179 #define PCH_DEVFN_IE_HECI3 _PCH_DEVFN(IE, 4) 180 #define PCH_DEVFN_IE_KT _PCH_DEVFN(IE, 3) 181 #define PCH_DEV_IE_HECI1 _PCH_DEV(IE, 0) 182 #define PCH_DEV_IE_HECI2 _PCH_DEV(IE, 1) 183 #define PCH_DEV_IE_HECI3 _PCH_DEV(IE, 4) 184 #define PCH_DEV_IE_KT _PCH_DEV(IE, 3) 185 #define IE_HECI_DEV 0x1b 186 #define IE_HECI1_DEV IE_HECI_DEV 187 #define IE_HECI1_FUNC 0 188 #define IE_HECI2_DEV IE_HECI_DEV 189 #define IE_HECI2_FUNC 1 190 #define IE_IEDR_DEV IE_HECI_DEV 191 #define IE_IEDR_FUNC 2 192 #define IE_MEKT_DEV IE_HECI_DEV 193 #define IE_MEKT_FUNC 3 194 #define IE_HECI3_DEV IE_HECI_DEV 195 #define IE_HECI3_FUNC 4 196 197 /* MMC Port */ 198 #define PCH_DEV_SLOT_EMMC 0x1c 199 #define PCH_DEVFN_EMMC _PCH_DEVFN(EMMC, 0) 200 #define PCH_DEV_EMMC _PCH_DEV(EMMC, 0) 201 #define MMC_DEV 0x1c 202 #define MMC_FUNC 0 203 204 /* Platform Controller Unit */ 205 #define PCH_DEV_SLOT_LPC 0x1f 206 #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) 207 #define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) 208 #define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) 209 #define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) 210 #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) 211 #define PCH_DEVFN_TRACE _PCH_DEVFN(LPC, 7) 212 #define PCH_DEV_LPC _PCH_DEV(LPC, 0) 213 #define PCH_DEV_P2SB _PCH_DEV(LPC, 1) 214 #define PCH_DEV_PMC _PCH_DEV(LPC, 2) 215 #define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) 216 #define PCH_DEV_SPI _PCH_DEV(LPC, 5) 217 #define PCH_DEV_TRACE _PCH_DEV(LPC, 7) 218 #define PCU_DEV 0x1f 219 #define LPC_DEV PCU_DEV 220 #define LPC_FUNC 0 221 #define P2SB_DEV PCU_DEV 222 #define P2SB_FUNC 1 223 #define PMC_DEV PCU_DEV 224 #define PMC_FUNC 2 225 #define SMBUS_DEV PCU_DEV 226 #define SMBUS_FUNC 4 227 #define SPI_DEV PCU_DEV 228 #define SPI_FUNC 5 229 #define NPK_DEV PCU_DEV 230 #define NPK_FUNC 7 231 232 /* VT-d support value to match FSP settings */ 233 /* "PCH IOAPIC Config" */ 234 #define PCH_IOAPIC_PCI_BUS 0xf0 235 #define PCH_IOAPIC_PCI_SLOT 0x1f 236 /* "PCH HPET Config" */ 237 #define PCH_HPET_PCI_BUS 0 238 #define PCH_HPET_PCI_SLOT 0 239 240 #endif /* _DENVERTON_NS_PCI_DEVS_H_ */ 241